clean these up (mostly rename bus_space_{tag,handle}_t variables) so that
this code makes equal sense for memory and I/O space, prefer to map the PCI front end via memory space (conditionalized on a patchable kernel variable), and do a bit of other random NetBSD-specific cleanup. (These changes were sent to Justin Gibbs on March 28.)
This commit is contained in:
cgd
parent
319b64a8f7
commit
db0f072019
@ -1,4 +1,4 @@
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/* $NetBSD: aic7xxx.c,v 1.22 1997/03/13 00:38:48 cgd Exp $ */
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/* $NetBSD: aic7xxx.c,v 1.23 1997/04/10 02:48:38 cgd Exp $ */
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/*
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* Generic driver for the aic7xxx based adaptec SCSI controllers
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@ -428,10 +428,10 @@ ahc_alloc(unit, iobase, type, flags)
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u_long iobase;
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#elif defined(__NetBSD__)
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void
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ahc_construct(ahc, iot, ioh, type, flags)
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ahc_construct(ahc, st, sh, type, flags)
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struct ahc_data *ahc;
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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bus_space_tag_t st;
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bus_space_handle_t sh;
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#endif
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ahc_type type;
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ahc_flag flags;
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@ -465,8 +465,8 @@ ahc_construct(ahc, iot, ioh, type, flags)
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#if defined(__FreeBSD__)
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ahc->baseport = iobase;
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#elif defined(__NetBSD__)
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ahc->sc_iot = iot;
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ahc->sc_ioh = ioh;
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ahc->sc_st = st;
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ahc->sc_sh = sh;
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#endif
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ahc->type = type;
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ahc->flags = flags;
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@ -493,10 +493,10 @@ void
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ahc_reset(iobase)
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u_long iobase;
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#elif defined(__NetBSD__)
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ahc_reset(devname, iot, ioh)
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ahc_reset(devname, st, sh)
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char *devname;
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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bus_space_tag_t st;
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bus_space_handle_t sh;
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#endif
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{
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u_char hcntrl;
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@ -508,9 +508,9 @@ ahc_reset(devname, iot, ioh)
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outb(HCNTRL + iobase, CHIPRST | PAUSE);
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#elif defined(__NetBSD__)
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hcntrl = (bus_space_read_1(iot, ioh, HCNTRL) & IRQMS) | INTEN;
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hcntrl = (bus_space_read_1(st, sh, HCNTRL) & IRQMS) | INTEN;
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bus_space_write_1(iot, ioh, HCNTRL, CHIPRST | PAUSE);
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bus_space_write_1(st, sh, HCNTRL, CHIPRST | PAUSE);
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#endif
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/*
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* Ensure that the reset has finished
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@ -519,7 +519,7 @@ ahc_reset(devname, iot, ioh)
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#if defined(__FreeBSD__)
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while (--wait && !(inb(HCNTRL + iobase) & CHIPRSTACK))
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#elif defined(__NetBSD__)
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while (--wait && !(bus_space_read_1(iot, ioh, HCNTRL) & CHIPRSTACK))
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while (--wait && !(bus_space_read_1(st, sh, HCNTRL) & CHIPRSTACK))
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#endif
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DELAY(1000);
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if(wait == 0) {
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@ -534,7 +534,7 @@ ahc_reset(devname, iot, ioh)
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#if defined(__FreeBSD__)
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outb(HCNTRL + iobase, hcntrl | PAUSE);
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#elif defined(__NetBSD__)
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bus_space_write_1(iot, ioh, HCNTRL, hcntrl | PAUSE);
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bus_space_write_1(st, sh, HCNTRL, hcntrl | PAUSE);
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#endif
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: aic7xxxvar.h,v 1.12 1997/03/13 00:38:50 cgd Exp $ */
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/* $NetBSD: aic7xxxvar.h,v 1.13 1997/04/10 02:48:41 cgd Exp $ */
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/*
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* Interface to the generic driver for the aic7xxx based adaptec
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@ -70,15 +70,15 @@
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outsl((ahc)->baseport+(port), valp, size)
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#elif defined(__NetBSD__)
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#define AHC_INB(ahc, port) \
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bus_space_read_1((ahc)->sc_iot, (ahc)->sc_ioh, port)
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bus_space_read_1((ahc)->sc_st, (ahc)->sc_sh, port)
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#define AHC_INSB(ahc, port, valp, size) \
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bus_space_read_multi_1((ahc)->sc_iot, (ahc)->sc_ioh, port, (u_int8_t *) valp, size)
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bus_space_read_multi_1((ahc)->sc_st, (ahc)->sc_sh, port, (u_int8_t *) valp, size)
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#define AHC_OUTB(ahc, port, val) \
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bus_space_write_1((ahc)->sc_iot, (ahc)->sc_ioh, port, val)
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bus_space_write_1((ahc)->sc_st, (ahc)->sc_sh, port, val)
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#define AHC_OUTSB(ahc, port, valp, size) \
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bus_space_write_multi_1((ahc)->sc_iot, (ahc)->sc_ioh, port, (u_int8_t *) valp, size)
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bus_space_write_multi_1((ahc)->sc_st, (ahc)->sc_sh, port, (u_int8_t *) valp, size)
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#define AHC_OUTSL(ahc, port, valp, size) \
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bus_space_write_multi_4((ahc)->sc_iot, (ahc)->sc_ioh, port, (u_int32_t *) valp, size)
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bus_space_write_multi_4((ahc)->sc_st, (ahc)->sc_sh, port, (u_int32_t *) valp, size)
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#endif
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#define AHC_NSEG 256 /* number of dma segments supported */
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@ -211,8 +211,8 @@ struct ahc_data {
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#elif defined(__NetBSD__)
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struct device sc_dev;
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void *sc_ih;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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bus_space_tag_t sc_st;
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bus_space_handle_t sc_sh;
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LIST_HEAD(, scsi_xfer) sc_xxxq; /* XXX software request queue */
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struct scsi_xfer *sc_xxxqlast; /* last entry in queue */
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#endif
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@ -292,10 +292,10 @@ struct ahc_data *ahc_alloc __P((int unit, u_long io_base, ahc_type type, ahc_fla
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#define ahc_name(ahc) (ahc)->sc_dev.dv_xname
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void ahc_reset __P((char *devname, bus_space_tag_t iot,
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bus_space_handle_t ioh));
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void ahc_construct __P((struct ahc_data *ahc, bus_space_tag_t iot,
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bus_space_handle_t ioh, ahc_type type, ahc_flag flags));
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void ahc_reset __P((char *devname, bus_space_tag_t st,
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bus_space_handle_t sh));
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void ahc_construct __P((struct ahc_data *ahc, bus_space_tag_t st,
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bus_space_handle_t sh, ahc_type type, ahc_flag flags));
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#endif
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void ahc_free __P((struct ahc_data *));
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int ahc_init __P((struct ahc_data *));
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@ -1,4 +1,4 @@
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/* $NetBSD: smc93cx6var.h,v 1.3 1996/10/21 22:34:41 thorpej Exp $ */
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/* $NetBSD: smc93cx6var.h,v 1.4 1997/04/10 02:48:42 cgd Exp $ */
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/*
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* Interface to the 93C46 serial EEPROM that is used to store BIOS
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@ -34,8 +34,8 @@ struct seeprom_descriptor {
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#if defined(__FreeBSD__)
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u_long sd_iobase;
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#elif defined(__NetBSD__)
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bus_space_tag_t sd_iot;
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bus_space_handle_t sd_ioh;
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bus_space_tag_t sd_st;
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bus_space_handle_t sd_sh;
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bus_size_t sd_offset;
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#endif
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u_int16_t sd_MS;
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@ -67,9 +67,9 @@ struct seeprom_descriptor {
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#define SEEPROM_OUTB(sd, value) outb(sd->sd_iobase, value)
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#elif defined(__NetBSD__)
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#define SEEPROM_INB(sd) \
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bus_space_read_1(sd->sd_iot, sd->sd_ioh, sd->sd_offset)
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bus_space_read_1(sd->sd_st, sd->sd_sh, sd->sd_offset)
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#define SEEPROM_OUTB(sd, value) \
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bus_space_write_1(sd->sd_iot, sd->sd_ioh, sd->sd_offset, value)
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bus_space_write_1(sd->sd_st, sd->sd_sh, sd->sd_offset, value)
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#endif
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#if defined(__FreeBSD__)
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@ -1,4 +1,4 @@
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/* $NetBSD: ahc_pci.c,v 1.11 1997/03/13 01:04:02 cgd Exp $ */
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/* $NetBSD: ahc_pci.c,v 1.12 1997/04/10 02:48:45 cgd Exp $ */
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/*
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* Product specific probe and attach routines for:
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@ -85,7 +85,10 @@
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#define bootverbose 0
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#endif
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#define PCI_BASEADR0 PCI_MAPREG_START
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#define PCI_BASEADR_IO 0x10
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#define PCI_BASEADR_MEM 0x14
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int ahc_pci_prefer_io = 0; /* 1 -> map via I/O (patchable data) */
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#endif /* defined(__NetBSD__) */
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@ -315,9 +318,10 @@ ahc_pci_attach(parent, self, aux)
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#elif defined(__NetBSD__)
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struct pci_attach_args *pa = aux;
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struct ahc_data *ahc = (void *)self;
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bus_addr_t iobase;
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bus_size_t iosize;
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bus_space_handle_t ioh;
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bus_addr_t busbase;
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bus_size_t bussize;
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bus_space_tag_t st;
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bus_space_handle_t sh;
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pci_intr_handle_t ih;
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const char *intrstr;
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#endif
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@ -340,10 +344,27 @@ ahc_pci_attach(parent, self, aux)
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*/
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io_port &= 0xfffffffe;
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#elif defined(__NetBSD__)
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if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_BASEADR0, &iobase, &iosize))
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if (ahc_pci_prefer_io) {
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if (pci_io_find(pa->pa_pc, pa->pa_tag, PCI_BASEADR_IO,
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&busbase, &bussize)) {
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printf(": unable to find PCI I/O base\n");
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return;
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if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &ioh))
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}
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st = pa->pa_iot;
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} else {
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if (pci_mem_find(pa->pa_pc, pa->pa_tag, PCI_BASEADR_MEM,
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&busbase, &bussize, NULL)) {
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printf(": unable to find PCI memory base\n");
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return;
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}
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st = pa->pa_memt;
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}
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if (bus_space_map(st, busbase, bussize, 0, &sh)) {
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printf(": unable to map %s registers\n",
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ahc_pci_prefer_io ? "I/O" : "memory");
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return;
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}
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printf("\n");
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#endif
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#if defined(__FreeBSD__)
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@ -399,17 +420,15 @@ ahc_pci_attach(parent, self, aux)
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if(ahc_t & AHC_ULTRA)
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ultra_enb = inb(SXFRCTL0 + io_port) & ULTRAEN;
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#else
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our_id = bus_space_read_1(pa->pa_iot, ioh, SCSIID) & OID;
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our_id = bus_space_read_1(st, sh, SCSIID) & OID;
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if(ahc_t & AHC_ULTRA)
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ultra_enb = bus_space_read_1(pa->pa_iot, ioh,
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SXFRCTL0) & ULTRAEN;
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ultra_enb = bus_space_read_1(st, sh, SXFRCTL0) & ULTRAEN;
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#endif
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#if defined(__FreeBSD__)
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ahc_reset(io_port);
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#elif defined(__NetBSD__)
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printf("\n");
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ahc_reset(ahc->sc_dev.dv_xname, pa->pa_iot, ioh);
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ahc_reset(ahc->sc_dev.dv_xname, st, sh);
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#endif
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if(ahc_t & AHC_AIC7870){
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@ -459,7 +478,7 @@ ahc_pci_attach(parent, self, aux)
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return;
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}
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#elif defined(__NetBSD__)
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ahc_construct(ahc, pa->pa_iot, ioh, ahc_t, ahc_f);
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ahc_construct(ahc, st, sh, ahc_t, ahc_f);
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if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
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pa->pa_intrline, &ih)) {
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@ -630,8 +649,8 @@ load_seeprom(ahc)
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#if defined(__FreeBSD__)
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sd.sd_iobase = ahc->baseport + SEECTL;
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#elif defined(__NetBSD__)
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sd.sd_iot = ahc->sc_iot;
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sd.sd_ioh = ahc->sc_ioh;
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sd.sd_st = ahc->sc_st;
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sd.sd_sh = ahc->sc_sh;
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sd.sd_offset = SEECTL;
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#endif
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sd.sd_MS = SEEMS;
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