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Recognize Cortex-A57 FPU, GIC, and Generic Timer.

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This commit is contained in:
jmcneill 2017-05-26 21:17:46 +00:00
parent b0a72e63a8
commit da90d24c20
4 changed files with 21 additions and 5 deletions
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3
sys/arch/arm/conf/files.arm
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@ -1,4 +1,4 @@
# $NetBSD: files.arm,v 1.131 2015/11/11 17:54:17 skrll Exp $
# $NetBSD: files.arm,v 1.132 2017/05/26 21:17:46 jmcneill Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@ -50,6 +50,7 @@ defflag opt_cputypes.h CPU_CORTEXA8: CPU_CORTEX
defflag opt_cputypes.h CPU_CORTEXA9: CPU_CORTEX
defflag opt_cputypes.h CPU_CORTEXA15: CPU_CORTEX
defflag opt_cputypes.h CPU_CORTEXA17: CPU_CORTEX
defflag opt_cputypes.h CPU_CORTEXA57: CPU_CORTEX
defflag opt_cputypes.h FPU_VFP
defparam opt_cpuoptions.h XSCALE_CCLKCFG

15
sys/arch/arm/cortex/armperiph.c
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@ -31,7 +31,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.10 2015/04/02 06:15:40 matt Exp $");
__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.11 2017/05/26 21:17:46 jmcneill Exp $");
#include <sys/param.h>
#include <sys/device.h>
@ -106,6 +106,14 @@ static const struct armperiph_info a17_devices[] = {
};
#endif
#ifdef CPU_CORTEXA57
static const struct armperiph_info a57_devices[] = {
{ "armgic", 0x1000, 0x2000 },
{ "armgtmr", 0, 0 },
{ "", 0, 0 },
};
#endif
static const struct mpcore_config {
const struct armperiph_info *cfg_devices;
@ -127,6 +135,9 @@ static const struct mpcore_config {
#ifdef CPU_CORTEXA17
{ a17_devices, 0x410fc0e0, 8*4096 },
#endif
#ifdef CPU_CORTEXA57
{ a57_devices, 0x410fd070, 8*4096 },
#endif
};
static const struct mpcore_config *
@ -218,7 +229,7 @@ armperiph_attach(device_t parent, device_t self, void *aux)
.mpcaa_off1 = cfg->cfg_devices[i].pi_off1,
.mpcaa_off2 = cfg->cfg_devices[i].pi_off2,
};
#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA57)
if (strcmp(mpcaa.mpcaa_name, "armgtmr") == 0) {
mpcaa.mpcaa_irq = IRQ_GTMR_PPI_VTIMER;
}

3
sys/arch/arm/include/vfpreg.h
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@ -1,4 +1,4 @@
/* $NetBSD: vfpreg.h,v 1.15 2016/03/03 17:01:31 skrll Exp $ */
/* $NetBSD: vfpreg.h,v 1.16 2017/05/26 21:17:46 jmcneill Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@ -66,6 +66,7 @@
#define FPU_VFP_CORTEXA15 0x410330f0
#define FPU_VFP_CORTEXA15_QEMU 0x410430f0
#define FPU_VFP_CORTEXA53 0x41034030
#define FPU_VFP_CORTEXA57 0x41034070
#define FPU_VFP_MV88SV58XX 0x56022090
#define VFP_FPEXC_EX 0x80000000 /* EXception status bit */

5
sys/arch/arm/vfp/vfp_init.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: vfp_init.c,v 1.52 2017/03/22 23:36:02 chs Exp $ */
/* $NetBSD: vfp_init.c,v 1.53 2017/05/26 21:17:46 jmcneill Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@ -96,6 +96,7 @@ load_vfpregs(const struct vfpreg *fregs)
case FPU_VFP_CORTEXA15:
case FPU_VFP_CORTEXA15_QEMU:
case FPU_VFP_CORTEXA53:
case FPU_VFP_CORTEXA57:
#endif
load_vfpregs_hi(fregs->vfp_regs);
#ifdef CPU_ARM11
@ -119,6 +120,7 @@ save_vfpregs(struct vfpreg *fregs)
case FPU_VFP_CORTEXA15:
case FPU_VFP_CORTEXA15_QEMU:
case FPU_VFP_CORTEXA53:
case FPU_VFP_CORTEXA57:
#endif
save_vfpregs_hi(fregs->vfp_regs);
#ifdef CPU_ARM11
@ -320,6 +322,7 @@ vfp_attach(struct cpu_info *ci)
case FPU_VFP_CORTEXA15:
case FPU_VFP_CORTEXA15_QEMU:
case FPU_VFP_CORTEXA53:
case FPU_VFP_CORTEXA57:
if (armreg_cpacr_read() & CPACR_V7_ASEDIS) {
model = "VFP 4.0+";
} else {