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Delete files that have been moved to powrpc/ibm4xx.

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eeh 2002-03-15 20:56:42 +00:00
parent 8bf657ddf1
commit d9df83b6a9
3 changed files with 0 additions and 824 deletions
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214
sys/arch/walnut/walnut/clock.c
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@ -1,214 +0,0 @@
/* $NetBSD: clock.c,v 1.3 2002/03/13 19:32:25 eeh Exp $ */
/* $OpenBSD: clock.c,v 1.3 1997/10/13 13:42:53 pefo Exp $ */
/*
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
* Copyright (C) 1995, 1996 TooLs GmbH.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by TooLs GmbH.
* 4. The name of TooLs GmbH may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <machine/walnut.h>
#include <machine/dcr.h>
#include <powerpc/spr.h>
/*
* Initially we assume a processor with a bus frequency of 12.5 MHz.
*/
static u_long ticks_per_sec;
static u_long ns_per_tick;
static long ticks_per_intr;
static volatile u_long lasttb;
static u_long ticksmissed;
static volatile int tickspending;
void decr_intr(struct clockframe *); /* called from trap_subr.S */
void stat_intr(struct clockframe *); /* called from trap_subr.S */
static inline u_quad_t mftb(void);
#ifdef FAST_STAT_CLOCK
/* Stat clock runs at ~ 1.5KHz */
#define PERIOD_POWER 17
#define TCR_PERIOD TCR_FP_2_17
#else
/* Stat clock runs at ~ 95Hz */
#define PERIOD_POWER 21
#define TCR_PERIOD TCR_FP_2_21
#endif
void
stat_intr(struct clockframe *frame)
{
extern u_long intrcnt[];
mtspr(SPR_TSR, TSR_FIS); /* Clear TSR[FIS] */
intrcnt[CNT_STATCLOCK]++;
statclock(frame);
}
void
decr_intr(struct clockframe *frame)
{
int pri;
long tick, xticks;
int nticks;
extern u_long intrcnt[];
/*
* Check whether we are initialized.
*/
if (!ticks_per_intr)
return;
asm volatile("mftb %0":"=r"(tick):);
mtspr(SPR_TSR, TSR_PIS); /* Clear TSR[PIS] */
/*
* lasttb is used during microtime. Set it to the virtual
* start of this tick interval.
*/
xticks = tick - lasttb; /* Number of TLB cycles since last exception */
for (nticks = 0; xticks > ticks_per_intr; nticks++)
xticks -= ticks_per_intr;
lasttb = tick - xticks;
intrcnt[CNT_CLOCK]++;
pri = splclock();
if (pri & SPL_CLOCK) {
tickspending += nticks;
ticksmissed+= nticks;
} else {
nticks += tickspending;
tickspending = 0;
/*
* Reenable interrupts
*/
asm volatile ("wrteei 1");
/*
* Do standard timer interrupt stuff.
* Do softclock stuff only on the last iteration.
*/
frame->pri = pri | SINT_CLOCK;
while (--nticks > 0)
hardclock(frame);
frame->pri = pri;
hardclock(frame);
}
splx(pri);
}
void
cpu_initclocks(void)
{
ticks_per_intr = ticks_per_sec / hz;
stathz = profhz = ticks_per_sec / (1<<PERIOD_POWER);
printf("Setting PIT to %ld/%d = %ld\n", ticks_per_sec, hz, ticks_per_intr);
asm volatile ("mftb %0" : "=r"(lasttb));
mtspr(SPR_PIT, ticks_per_intr);
/* Enable PIT & FIT(2^17c = 0.655ms) interrupts and auto-reload */
mtspr(SPR_TCR, TCR_PIE | TCR_ARE | TCR_FIE | TCR_PERIOD);
}
void
calc_delayconst(void)
{
ticks_per_sec = board_data.processor_speed;
ns_per_tick = 1000000000 / ticks_per_sec;
/* Make sure that timers run at CPU frequency */
mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
}
static inline u_quad_t
mftb(void)
{
u_long scratch;
u_quad_t tb;
asm ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw %0,%1; bne 1b"
: "=r"(tb), "=r"(scratch));
return tb;
}
/*
* Fill in *tvp with current time with microsecond resolution.
*/
void
microtime(struct timeval *tvp)
{
u_long tb;
u_long ticks;
int msr;
asm volatile ("mfmsr %0; wrteei 0" : "=r"(msr) :);
asm ("mftb %0" : "=r"(tb));
ticks = (tb - lasttb) * ns_per_tick;
*tvp = time;
asm volatile ("mtmsr %0" :: "r"(msr));
ticks /= 1000;
tvp->tv_usec += ticks;
while (tvp->tv_usec >= 1000000) {
tvp->tv_usec -= 1000000;
tvp->tv_sec++;
}
}
/*
* Wait for about n microseconds (at least!).
*/
void
delay(unsigned int n)
{
u_quad_t tb;
u_long tbh, tbl, scratch;
tb = mftb();
/* use 1000ULL to force 64 bit math to avoid 32 bit overflows */
tb += (n * 1000ULL + ns_per_tick - 1) / ns_per_tick;
tbh = tb >> 32;
tbl = tb;
asm volatile ("1: mftbu %0; cmplw %0,%1; blt 1b; bgt 2f;"
"mftb %0; cmplw %0,%2; blt 1b; 2:"
: "=r"(scratch) : "r"(tbh), "r"(tbl));
}
/*
* Nothing to do.
*/
void
setstatclockrate(int arg)
{
/* Do nothing */
}

107
sys/arch/walnut/walnut/cpu.c
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@ -1,107 +0,0 @@
/* $NetBSD: cpu.c,v 1.2 2001/06/24 01:16:18 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <machine/autoconf.h>
#include <machine/walnut.h>
#include <powerpc/ibm4xx/ibm405gp.h>
struct cputab {
int version;
char *name;
};
static struct cputab models[] = {
{ PVR_405GP >> 16, "405GP" },
{ 0, NULL }
};
static int cpumatch(struct device *, struct cfdata *, void *);
static void cpuattach(struct device *, struct device *, void *);
struct cfattach cpu_ca = {
sizeof(struct device), cpumatch, cpuattach
};
int ncpus;
struct cpu_info cpu_info_store;
int cpufound = 0;
static int
cpumatch(struct device *parent, struct cfdata *cf, void *aux)
{
union mainbus_attach_args *maa = aux;
/* make sure that we're looking for a CPU */
if (strcmp(maa->mba_rmb.rmb_name, cf->cf_driver->cd_name) != 0)
return (0);
return !cpufound;
}
static void
cpuattach(struct device *parent, struct device *self, void *aux)
{
int pvr, cpu;
struct cputab *cp = models;
cpufound++;
ncpus++;
asm ("mfpvr %0" : "=r"(pvr));
cpu = pvr >> 16;
while (cp->name) {
if (cp->version == cpu)
break;
cp++;
}
if (cp->name)
strcpy(cpu_model, cp->name);
else
sprintf(cpu_model, "Version 0x%x", cpu);
sprintf(cpu_model + strlen(cpu_model), " (Revision %d.%d)",
(pvr >> 8) & 0xff, pvr & 0xff);
printf(": %dMHz %s\n", board_data.processor_speed / 1000 / 1000,
cpu_model);
}

503
sys/arch/walnut/walnut/extintr.c
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@ -1,503 +0,0 @@
/* $NetBSD: extintr.c,v 1.4 2001/11/08 23:28:15 eeh Exp $ */
/* $OpenBSD: isabus.c,v 1.1 1997/10/11 11:53:00 pefo Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1995 Per Fogelstrom
* Copyright (c) 1993, 1994 Charles M. Hannum.
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz and Don Ahn.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)isa.c 7.2 (Berkeley) 5/12/91
*/
#include <sys/param.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <uvm/uvm_extern.h>
#include <machine/intr.h>
#include <machine/psl.h>
#include <powerpc/spr.h>
#include <powerpc/ibm4xx/dcr.h>
static inline void galaxy_disable_irq(int irq);
static inline void galaxy_enable_irq(int irq);
static void intr_calculatemasks(void);
static char *intr_typename(int);
static int fakeintr(void *);
static inline int cntlzw(int);
volatile int cpl, ipending, astpending;
u_long imask[NIPL];
static int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN];
static struct intrhand *intrhand[ICU_LEN];
static inline int
cntlzw(int x)
{
int a;
__asm __volatile ("cntlzw %0,%1" : "=r"(a) : "r"(x));
return a;
}
static int
fakeintr(void *arg)
{
return 0;
}
/*
* Set up interrupt mapping array.
*/
void
intr_init(void)
{
}
/*
* external interrupt handler
*/
void
ext_intr(void)
{
int i, bits_to_clear;
int r_imen, msr;
int pcpl;
struct intrhand *ih;
u_long int_state;
pcpl = cpl;
asm volatile ("mfmsr %0" : "=r"(msr));
int_state = mfdcr(DCR_UIC0_MSR); /* Read non-masked interrupt status */
bits_to_clear = int_state;
while (int_state) {
i = cntlzw(int_state);
int_state &= ~IRQ_TO_MASK(i);
r_imen = IRQ_TO_MASK(i);
if ((pcpl & r_imen) != 0) {
ipending |= r_imen; /* Masked! Mark this as pending */
galaxy_disable_irq(i);
} else {
splraise(intrmask[i]);
asm volatile ("mtmsr %0" :: "r"(msr | PSL_EE));
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
ih = intrhand[i];
while (ih) {
(*ih->ih_fun)(ih->ih_arg);
ih = ih->ih_next;
}
KERNEL_UNLOCK();
asm volatile ("mtmsr %0" :: "r"(msr));
cpl = pcpl;
uvmexp.intrs++;
intrcnt[i]++;
}
}
mtdcr(DCR_UIC0_SR, bits_to_clear); /* Acknowledge all pending interrupts */
asm volatile ("mtmsr %0" :: "r"(msr | PSL_EE));
splx(pcpl);
asm volatile ("mtmsr %0" :: "r"(msr));
}
static inline void
galaxy_disable_irq(int irq)
{
int mask, omask;
mask = omask = mfdcr(DCR_UIC0_ER);
mask &= ~IRQ_TO_MASK(irq);
if (mask == omask)
return;
mtdcr(DCR_UIC0_ER, mask);
#ifdef IRQ_DEBUG
printf("irq_disable: irq=%d, mask=%08x\n",irq,mask);
#endif
}
static inline void
galaxy_enable_irq(int irq)
{
int mask, omask;
mask = omask = mfdcr(DCR_UIC0_ER);
mask |= IRQ_TO_MASK(irq);
if (mask == omask)
return;
mtdcr(DCR_UIC0_ER, mask);
#ifdef IRQ_DEBUG
printf("irq_enable: irq=%d, mask=%08x\n",irq,mask);
#endif
}
static char *
intr_typename(int type)
{
switch (type) {
case IST_NONE :
return ("none");
case IST_PULSE:
return ("pulsed");
case IST_EDGE:
return ("edge-triggered");
case IST_LEVEL:
return ("level-triggered");
default:
panic("isa_intr_typename: invalid type %d", type);
}
}
/*
* Register an interrupt handler.
*/
void *
intr_establish(int irq, int type, int level, int (*ih_fun)(void *), void *ih_arg)
{
struct intrhand **p, *q, *ih;
static struct intrhand fakehand = { fakeintr };
/* no point in sleeping unless someone can free memory. */
ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
if (ih == NULL)
panic("intr_establish: can't malloc handler info");
if (!LEGAL_IRQ(irq) || type == IST_NONE)
panic("intr_establish: bogus irq or type");
switch (intrtype[irq]) {
case IST_EDGE:
case IST_LEVEL:
if (type == intrtype[irq])
break;
case IST_PULSE:
if (type != IST_NONE)
panic("intr_establish: can't share %s with %s",
intr_typename(intrtype[irq]),
intr_typename(type));
break;
}
/*
* Figure out where to put the handler.
* This is O(N^2), but we want to preserve the order, and N is
* generally small.
*/
for (p = &intrhand[irq]; (q = *p) != NULL; p = &q->ih_next)
;
/*
* Actually install a fake handler momentarily, since we might be doing
* this with interrupts enabled and don't want the real routine called
* until masking is set up.
*/
fakehand.ih_level = level;
*p = &fakehand;
intr_calculatemasks();
/*
* Poke the real handler in now.
*/
ih->ih_fun = ih_fun;
ih->ih_arg = ih_arg;
ih->ih_count = 0;
ih->ih_next = NULL;
ih->ih_level = level;
ih->ih_irq = irq;
*p = ih;
#ifdef IRQ_DEBUG
printf("***** intr_establish: irq%d h=%p arg=%p\n",irq, ih_fun, ih_arg);
#endif
return (ih);
}
/*
* Deregister an interrupt handler.
*/
void
intr_disestablish(void *arg)
{
struct intrhand *ih = arg;
int irq = ih->ih_irq;
struct intrhand **p, *q;
if (!LEGAL_IRQ(irq))
panic("intr_disestablish: bogus irq");
/*
* Remove the handler from the chain.
* This is O(n^2), too.
*/
for (p = &intrhand[irq]; (q = *p) != NULL && q != ih; p = &q->ih_next)
;
if (q)
*p = q->ih_next;
else
panic("intr_disestablish: handler not registered");
free((void *)ih, M_DEVBUF);
intr_calculatemasks();
if (intrhand[irq] == NULL)
intrtype[irq] = IST_NONE;
}
/*
* Recalculate the interrupt masks from scratch.
* We could code special registry and deregistry versions of this function that
* would be faster, but the code would be nastier, and we don't expect this to
* happen very much anyway.
*/
static void
intr_calculatemasks(void)
{
int irq, level;
struct intrhand *q;
/* First, figure out which levels each IRQ uses. */
for (irq = 0; irq < ICU_LEN; irq++) {
register int levels = 0;
for (q = intrhand[irq]; q; q = q->ih_next)
levels |= 1 << q->ih_level;
intrlevel[irq] = levels;
}
/* Then figure out which IRQs use each level. */
for (level = 0; level < NIPL; level++) {
register int irqs = 0;
for (irq = 0; irq < ICU_LEN; irq++)
if (intrlevel[irq] & (1 << level))
irqs |= IRQ_TO_MASK(irq);
imask[level] = irqs | SINT_MASK;
}
/*
* IPL_CLOCK should mask clock interrupt even if interrupt handler
* is not registered.
*/
imask[IPL_CLOCK] |= SPL_CLOCK;
/*
* Initialize the soft interrupt masks to block themselves.
*/
imask[IPL_SOFTCLOCK] = SINT_CLOCK;
imask[IPL_SOFTNET] = SINT_NET;
imask[IPL_SOFTSERIAL] = SINT_SERIAL;
/*
* IPL_NONE is used for hardware interrupts that are never blocked,
* and do not block anything else.
*/
imask[IPL_NONE] = 0;
/*
* Enforce a hierarchy that gives slow devices a better chance at not
* dropping data.
*/
imask[IPL_SOFTCLOCK] |= imask[IPL_NONE];
imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK];
imask[IPL_BIO] |= imask[IPL_SOFTNET];
imask[IPL_NET] |= imask[IPL_BIO];
imask[IPL_SOFTSERIAL] |= imask[IPL_NET];
imask[IPL_TTY] |= imask[IPL_SOFTSERIAL];
/*
* There are tty, network and disk drivers that use free() at interrupt
* time, so imp > (tty | net | bio).
*/
imask[IPL_IMP] |= imask[IPL_TTY];
imask[IPL_AUDIO] |= imask[IPL_IMP];
/*
* Since run queues may be manipulated by both the statclock and tty,
* network, and disk drivers, clock > imp.
*/
imask[IPL_CLOCK] |= imask[IPL_AUDIO];
/*
* IPL_HIGH must block everything that can manipulate a run queue.
*/
imask[IPL_HIGH] |= imask[IPL_CLOCK];
/*
* We need serial drivers to run at the absolute highest priority to
* avoid overruns, so serial > high.
*/
imask[IPL_SERIAL] |= imask[IPL_HIGH];
/* And eventually calculate the complete masks. */
for (irq = 0; irq < ICU_LEN; irq++) {
register int irqs = IRQ_TO_MASK(irq);
for (q = intrhand[irq]; q; q = q->ih_next)
irqs |= imask[q->ih_level];
intrmask[irq] = irqs;
}
for (irq = 0; irq < ICU_LEN; irq++)
if (intrhand[irq])
galaxy_enable_irq(irq);
else
galaxy_disable_irq(irq);
}
void
do_pending_int(void)
{
struct intrhand *ih;
int irq;
int pcpl;
int hwpend;
int emsr, dmsr;
static int processing;
if (processing)
return;
processing = 1;
asm volatile("mfmsr %0" : "=r"(emsr));
dmsr = emsr & ~PSL_EE;
asm volatile("mtmsr %0" :: "r"(dmsr));
pcpl = cpl; /* Turn off all */
again:
while ((hwpend = ipending & ~pcpl & HWINT_MASK)) {
irq = cntlzw(hwpend);
galaxy_enable_irq(irq);
ipending &= ~IRQ_TO_MASK(irq);
splraise(intrmask[irq]);
asm volatile("mtmsr %0" :: "r"(emsr));
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
ih = intrhand[irq];
while(ih) {
(*ih->ih_fun)(ih->ih_arg);
ih = ih->ih_next;
}
KERNEL_UNLOCK();
asm volatile("mtmsr %0" :: "r"(dmsr));
cpl = pcpl;
intrcnt[irq]++;
}
if ((ipending & ~pcpl) & SINT_SERIAL) {
ipending &= ~SINT_SERIAL;
splsoftserial();
asm volatile("mtmsr %0" :: "r"(emsr));
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
softserial();
KERNEL_UNLOCK();
asm volatile("mtmsr %0" :: "r"(dmsr));
cpl = pcpl;
intrcnt[CNT_SINT_SERIAL]++;
goto again;
}
if ((ipending & ~pcpl) & SINT_NET) {
ipending &= ~SINT_NET;
splsoftnet();
asm volatile("mtmsr %0" :: "r"(emsr));
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
softnet();
KERNEL_UNLOCK();
asm volatile("mtmsr %0" :: "r"(dmsr));
cpl = pcpl;
intrcnt[CNT_SINT_NET]++;
goto again;
}
if ((ipending & ~pcpl) & SINT_CLOCK) {
ipending &= ~SINT_CLOCK;
splsoftclock();
asm volatile("mtmsr %0" :: "r"(emsr));
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
softclock(NULL);
KERNEL_UNLOCK();
asm volatile("mtmsr %0" :: "r"(dmsr));
cpl = pcpl;
intrcnt[CNT_SINT_CLOCK]++;
goto again;
}
cpl = pcpl; /* Don't use splx... we are here already! */
asm volatile("mtmsr %0" :: "r"(emsr));
processing = 0;
}