Use <powerpc/powerpc/trap_subr.S>
This commit is contained in:
thorpej
parent
216902b8d2
commit
d96bb89daf
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.18 2000/08/21 18:46:03 tsubai Exp $ */
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/* $NetBSD: locore.s,v 1.19 2000/11/16 05:34:03 thorpej Exp $ */
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/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
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/*
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@ -399,575 +399,9 @@ switch_return:
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mtlr 0
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blr
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/*
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* Data used during primary/secondary traps/interrupts
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*/
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#define tempsave 0x2e0 /* primary save area for trap handling */
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#define disisave 0x3e0 /* primary save area for dsi/isi traps */
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#define INTSTK (8*1024) /* 8K interrupt stack */
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.data
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.align 4
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intstk:
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.space INTSTK /* interrupt stack */
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GLOBAL(intr_depth)
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.long -1 /* in-use marker */
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#define SPILLSTK 1024 /* 1K spill stack */
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.comm spillstk,SPILLSTK,8
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/*
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* This code gets copied to all the trap vectors
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* (except ISI/DSI, ALI, the interrupts, and possibly the debugging
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* traps when using IPKDB).
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*/
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.text
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.globl _C_LABEL(trapcode),_C_LABEL(trapsize)
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_C_LABEL(trapcode):
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mtsprg 1,1 /* save SP */
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stmw 28,tempsave(0) /* free r28-r31 */
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mflr 28 /* save LR */
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mfcr 29 /* save CR */
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/* Test whether we already had PR set */
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mfsrr1 31
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mtcr 31
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bc 4,17,1f /* branch if PSL_PR is clear */
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lis 1,_C_LABEL(curpcb)@ha
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lwz 1,_C_LABEL(curpcb)@l(1)
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addi 1,1,USPACE /* stack is top of user struct */
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1:
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bla s_trap
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_C_LABEL(trapsize) = .-_C_LABEL(trapcode)
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/*
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* For ALI: has to save DSISR and DAR
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*/
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.globl _C_LABEL(alitrap),_C_LABEL(alisize)
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_C_LABEL(alitrap):
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mtsprg 1,1 /* save SP */
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stmw 28,tempsave(0) /* free r28-r31 */
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mfdar 30
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mfdsisr 31
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stmw 30,tempsave+16(0)
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mflr 28 /* save LR */
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mfcr 29 /* save CR */
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/* Test whether we already had PR set */
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mfsrr1 31
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mtcr 31
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bc 4,17,1f /* branch if PSL_PR is clear */
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lis 1,_C_LABEL(curpcb)@ha
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lwz 1,_C_LABEL(curpcb)@l(1)
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addi 1,1,USPACE /* stack is top of user struct */
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1:
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bla s_trap
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_C_LABEL(alisize) = .-_C_LABEL(alitrap)
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/*
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* Similar to the above for DSI
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* Has to handle BAT spills
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* and standard pagetable spills
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*/
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.globl _C_LABEL(dsitrap),_C_LABEL(dsisize)
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_C_LABEL(dsitrap):
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stmw 28,disisave(0) /* free r28-r31 */
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mfcr 29 /* save CR */
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mfxer 30 /* save XER */
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mtsprg 2,30 /* in SPRG2 */
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mfsrr1 31 /* test kernel mode */
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mtcr 31
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bc 12,17,1f /* branch if PSL_PR is set */
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mfdar 31 /* get fault address */
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rlwinm 31,31,7,25,28 /* get segment * 8 */
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/* get batu */
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addis 31,31,_C_LABEL(battable)@ha
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lwz 30,_C_LABEL(battable)@l(31)
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mtcr 30
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bc 4,30,1f /* branch if supervisor valid is
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false */
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/* get batl */
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lwz 31,_C_LABEL(battable)+4@l(31)
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/* We randomly use the highest two bat registers here */
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mftb 28
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andi. 28,28,1
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bne 2f
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mtdbatu 2,30
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mtdbatl 2,31
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b 3f
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2:
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mtdbatu 3,30
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mtdbatl 3,31
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3:
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mfsprg 30,2 /* restore XER */
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mtxer 30
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mtcr 29 /* restore CR */
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lmw 28,disisave(0) /* restore r28-r31 */
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rfi /* return to trapped code */
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1:
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mflr 28 /* save LR */
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bla s_dsitrap
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_C_LABEL(dsisize) = .-_C_LABEL(dsitrap)
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/*
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* Similar to the above for ISI
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*/
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.globl _C_LABEL(isitrap),_C_LABEL(isisize)
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_C_LABEL(isitrap):
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stmw 28,disisave(0) /* free r28-r31 */
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mflr 28 /* save LR */
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mfcr 29 /* save CR */
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mfsrr1 31 /* test kernel mode */
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mtcr 31
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bc 12,17,1f /* branch if PSL_PR is set */
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mfsrr0 31 /* get fault address */
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rlwinm 31,31,7,25,28 /* get segment * 8 */
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/* get batu */
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addis 31,31,_C_LABEL(battable)@ha
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lwz 30,_C_LABEL(battable)@l(31)
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mtcr 30
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bc 4,30,1f /* branch if supervisor valid is
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false */
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mtibatu 3,30
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/* get batl */
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lwz 30,_C_LABEL(battable)+4@l(31)
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mtibatl 3,30
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mtcr 29 /* restore CR */
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lmw 28,disisave(0) /* restore r28-r31 */
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rfi /* return to trapped code */
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1:
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bla s_isitrap
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_C_LABEL(isisize)= .-_C_LABEL(isitrap)
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/*
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* This one for the external interrupt handler.
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*/
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.globl _C_LABEL(extint),_C_LABEL(extsize)
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_C_LABEL(extint):
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mtsprg 1,1 /* save SP */
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stmw 28,tempsave(0) /* free r28-r31 */
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mflr 28 /* save LR */
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mfcr 29 /* save CR */
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mfxer 30 /* save XER */
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lis 1,intstk+INTSTK@ha /* get interrupt stack */
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addi 1,1,intstk+INTSTK@l
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lwz 31,0(1) /* were we already running on intstk? */
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addic. 31,31,1
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stw 31,0(1)
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beq 1f
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mfsprg 1,1 /* yes, get old SP */
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1:
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ba extintr
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_C_LABEL(extsize) = .-_C_LABEL(extint)
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/*
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* And this one for the decrementer interrupt handler.
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*/
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.globl _C_LABEL(decrint),_C_LABEL(decrsize)
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_C_LABEL(decrint):
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mtsprg 1,1 /* save SP */
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stmw 28,tempsave(0) /* free r28-r31 */
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mflr 28 /* save LR */
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mfcr 29 /* save CR */
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mfxer 30 /* save XER */
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lis 1,intstk+INTSTK@ha /* get interrupt stack */
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addi 1,1,intstk+INTSTK@l
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lwz 31,0(1) /* were we already running on intstk? */
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addic. 31,31,1
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stw 31,0(1)
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beq 1f
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mfsprg 1,1 /* yes, get old SP */
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1:
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ba decrintr
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_C_LABEL(decrsize) = .-_C_LABEL(decrint)
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/*
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* Now the tlb software load for 603 processors:
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* (Code essentially from the 603e User Manual, Chapter 5, but
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* corrected a lot.)
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*/
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#define DMISS 976
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#define DCMP 977
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#define HASH1 978
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#define HASH2 979
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#define IMISS 980
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#define ICMP 981
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#define RPA 982
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.globl _C_LABEL(tlbimiss),_C_LABEL(tlbimsize)
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_C_LABEL(tlbimiss):
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mfspr 2,HASH1 /* get first pointer */
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li 1,8
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mfctr 0 /* save counter */
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mfspr 3,ICMP /* get first compare value */
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addi 2,2,-8 /* predec pointer */
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1:
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mtctr 1 /* load counter */
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2:
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lwzu 1,8(2) /* get next pte */
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cmpl 0,1,3 /* see if found pte */
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bdneq 2b /* loop if not eq */
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bne 3f /* not found */
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lwz 1,4(2) /* load tlb entry lower word */
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andi. 3,1,8 /* check G-bit */
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bne 4f /* if guarded, take ISI */
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mtctr 0 /* restore counter */
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mfspr 0,IMISS /* get the miss address for the tlbli */
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mfsrr1 3 /* get the saved cr0 bits */
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mtcrf 0x80,3 /* and restore */
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ori 1,1,0x100 /* set the reference bit */
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mtspr RPA,1 /* set the pte */
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srwi 1,1,8 /* get byte 7 of pte */
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tlbli 0 /* load the itlb */
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stb 1,6(2) /* update page table */
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rfi
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3: /* not found in pteg */
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andi. 1,3,0x40 /* have we already done second hash? */
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bne 5f
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mfspr 2,HASH2 /* get the second pointer */
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ori 3,3,0x40 /* change the compare value */
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li 1,8
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addi 2,2,-8 /* predec pointer */
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b 1b
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4: /* guarded */
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mfsrr1 3
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andi. 2,3,0xffff /* clean upper srr1 */
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oris 2,2,0x8000000@h /* set srr<4> to flag prot violation */
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b 6f
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5: /* not found anywhere */
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mfsrr1 3
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andi. 2,3,0xffff /* clean upper srr1 */
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oris 2,2,0x40000000@h /* set srr1<1> to flag pte not found */
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6:
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mtctr 0 /* restore counter */
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mtsrr1 2
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mfmsr 0
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xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
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mtcrf 0x80,3 /* restore cr0 */
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mtmsr 0 /* now with native gprs */
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isync
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ba EXC_ISI
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_C_LABEL(tlbimsize) = .-_C_LABEL(tlbimiss)
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.globl _C_LABEL(tlbdlmiss),_C_LABEL(tlbdlmsize)
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_C_LABEL(tlbdlmiss):
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mfspr 2,HASH1 /* get first pointer */
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li 1,8
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mfctr 0 /* save counter */
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mfspr 3,DCMP /* get first compare value */
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addi 2,2,-8 /* predec pointer */
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1:
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mtctr 1 /* load counter */
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2:
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lwzu 1,8(2) /* get next pte */
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cmpl 0,1,3 /* see if found pte */
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bdneq 2b /* loop if not eq */
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bne 3f /* not found */
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lwz 1,4(2) /* load tlb entry lower word */
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mtctr 0 /* restore counter */
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mfspr 0,DMISS /* get the miss address for the tlbld */
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mfsrr1 3 /* get the saved cr0 bits */
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mtcrf 0x80,3 /* and restore */
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ori 1,1,0x100 /* set the reference bit */
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mtspr RPA,1 /* set the pte */
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srwi 1,1,8 /* get byte 7 of pte */
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tlbld 0 /* load the dtlb */
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stb 1,6(2) /* update page table */
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rfi
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3: /* not found in pteg */
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andi. 1,3,0x40 /* have we already done second hash? */
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bne 5f
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mfspr 2,HASH2 /* get the second pointer */
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ori 3,3,0x40 /* change the compare value */
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li 1,8
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addi 2,2,-8 /* predec pointer */
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b 1b
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5: /* not found anywhere */
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mfsrr1 3
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lis 1,0x40000000@h /* set dsisr<1> to flag pte not found */
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mtctr 0 /* restore counter */
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andi. 2,3,0xffff /* clean upper srr1 */
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mtsrr1 2
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mtdsisr 1 /* load the dsisr */
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mfspr 1,DMISS /* get the miss address */
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mtdar 1 /* put in dar */
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mfmsr 0
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xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
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mtcrf 0x80,3 /* restore cr0 */
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mtmsr 0 /* now with native gprs */
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isync
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ba EXC_DSI
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_C_LABEL(tlbdlmsize) = .-_C_LABEL(tlbdlmiss)
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.globl _C_LABEL(tlbdsmiss),_C_LABEL(tlbdsmsize)
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_C_LABEL(tlbdsmiss):
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mfspr 2,HASH1 /* get first pointer */
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li 1,8
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mfctr 0 /* save counter */
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mfspr 3,DCMP /* get first compare value */
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addi 2,2,-8 /* predec pointer */
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1:
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mtctr 1 /* load counter */
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2:
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lwzu 1,8(2) /* get next pte */
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cmpl 0,1,3 /* see if found pte */
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bdneq 2b /* loop if not eq */
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bne 3f /* not found */
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lwz 1,4(2) /* load tlb entry lower word */
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andi. 3,1,0x80 /* check the C-bit */
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beq 4f
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5:
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mtctr 0 /* restore counter */
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mfspr 0,DMISS /* get the miss address for the tlbld */
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mfsrr1 3 /* get the saved cr0 bits */
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mtcrf 0x80,3 /* and restore */
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mtspr RPA,1 /* set the pte */
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tlbld 0 /* load the dtlb */
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rfi
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3: /* not found in pteg */
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andi. 1,3,0x40 /* have we already done second hash? */
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bne 5f
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mfspr 2,HASH2 /* get the second pointer */
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ori 3,3,0x40 /* change the compare value */
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li 1,8
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addi 2,2,-8 /* predec pointer */
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b 1b
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4: /* found, but C-bit = 0 */
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rlwinm. 3,1,30,0,1 /* test PP */
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bge- 7f
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andi. 3,1,1
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beq+ 8f
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9: /* found, but protection violation (PP==00)*/
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mfsrr1 3
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lis 1,0xa000000@h /* indicate protection violation
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on store */
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b 1f
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7: /* found, PP=1x */
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mfspr 3,DMISS /* get the miss address */
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mfsrin 1,3 /* get the segment register */
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mfsrr1 3
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rlwinm 3,3,18,31,31 /* get PR-bit */
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rlwnm. 2,2,3,1,1 /* get the key */
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bne- 9b /* protection violation */
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8: /* found, set reference/change bits */
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lwz 1,4(2) /* reload tlb entry */
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ori 1,1,0x180
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sth 1,6(2)
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b 5b
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5: /* not found anywhere */
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mfsrr1 3
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lis 1,0x42000000@h /* set dsisr<1> to flag pte not found */
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/* dsisr<6> to flag store */
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1:
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mtctr 0 /* restore counter */
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andi. 2,3,0xffff /* clean upper srr1 */
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mtsrr1 2
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mtdsisr 1 /* load the dsisr */
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mfspr 1,DMISS /* get the miss address */
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mtdar 1 /* put in dar */
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mfmsr 0
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xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
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mtcrf 0x80,3 /* restore cr0 */
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mtmsr 0 /* now with native gprs */
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isync
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ba EXC_DSI
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_C_LABEL(tlbdsmsize) = .-_C_LABEL(tlbdsmiss)
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#ifdef DDB
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#define ddbsave 0xde0 /* primary save area for DDB */
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/*
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* In case of DDB we want a separate trap catcher for it
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*/
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.local ddbstk
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.comm ddbstk,INTSTK,8 /* ddb stack */
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.globl _C_LABEL(ddblow),_C_LABEL(ddbsize)
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_C_LABEL(ddblow):
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mtsprg 1,1 /* save SP */
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stmw 28,ddbsave(0) /* free r28-r31 */
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mflr 28 /* save LR */
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mfcr 29 /* save CR */
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lis 1,ddbstk+INTSTK@ha /* get new SP */
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addi 1,1,ddbstk+INTSTK@l
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bla ddbtrap
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_C_LABEL(ddbsize) = .-_C_LABEL(ddblow)
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#endif /* DDB */
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#ifdef IPKDB
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#define ipkdbsave 0xde0 /* primary save area for IPKDB */
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/*
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* In case of IPKDB we want a separate trap catcher for it
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*/
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.local ipkdbstk
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.comm ipkdbstk,INTSTK,8 /* ipkdb stack */
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.globl _C_LABEL(ipkdblow),_C_LABEL(ipkdbsize)
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_C_LABEL(ipkdblow):
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mtsprg 1,1 /* save SP */
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stmw 28,ipkdbsave(0) /* free r28-r31 */
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mflr 28 /* save LR */
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mfcr 29 /* save CR */
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lis 1,ipkdbstk+INTSTK@ha /* get new SP */
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addi 1,1,ipkdbstk+INTSTK@l
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bla ipkdbtrap
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_C_LABEL(ipkdbsize) = .-_C_LABEL(ipkdblow)
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#endif /* IPKDB */
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/*
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* FRAME_SETUP assumes:
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* SPRG1 SP (1)
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* savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
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* 28 LR
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* 29 CR
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* 1 kernel stack
|
||||
* LR trap type
|
||||
* SRR0/1 as at start of trap
|
||||
*/
|
||||
#define FRAME_SETUP(savearea) \
|
||||
/* Have to enable translation to allow access of kernel stack: */ \
|
||||
mfsrr0 30; \
|
||||
mfsrr1 31; \
|
||||
stmw 30,savearea+24(0); \
|
||||
mfmsr 30; \
|
||||
ori 30,30,(PSL_DR|PSL_IR); \
|
||||
mtmsr 30; \
|
||||
isync; \
|
||||
mfsprg 31,1; \
|
||||
stwu 31,-FRAMELEN(1); \
|
||||
stw 0,FRAME_0+8(1); \
|
||||
stw 31,FRAME_1+8(1); \
|
||||
stw 28,FRAME_LR+8(1); \
|
||||
stw 29,FRAME_CR+8(1); \
|
||||
lmw 28,savearea(0); \
|
||||
stmw 2,FRAME_2+8(1); \
|
||||
lmw 28,savearea+16(0); \
|
||||
mfxer 3; \
|
||||
mfctr 4; \
|
||||
mflr 5; \
|
||||
andi. 5,5,0xff00; \
|
||||
stw 3,FRAME_XER+8(1); \
|
||||
stw 4,FRAME_CTR+8(1); \
|
||||
stw 5,FRAME_EXC+8(1); \
|
||||
stw 28,FRAME_DAR+8(1); \
|
||||
stw 29,FRAME_DSISR+8(1); \
|
||||
stw 30,FRAME_SRR0+8(1); \
|
||||
stw 31,FRAME_SRR1+8(1)
|
||||
|
||||
#define FRAME_LEAVE(savearea) \
|
||||
/* Now restore regs: */ \
|
||||
lwz 2,FRAME_SRR0+8(1); \
|
||||
lwz 3,FRAME_SRR1+8(1); \
|
||||
lwz 4,FRAME_CTR+8(1); \
|
||||
lwz 5,FRAME_XER+8(1); \
|
||||
lwz 6,FRAME_LR+8(1); \
|
||||
lwz 7,FRAME_CR+8(1); \
|
||||
stw 2,savearea(0); \
|
||||
stw 3,savearea+4(0); \
|
||||
mtctr 4; \
|
||||
mtxer 5; \
|
||||
mtlr 6; \
|
||||
mtsprg 1,7; /* save cr */ \
|
||||
lmw 2,FRAME_2+8(1); \
|
||||
lwz 0,FRAME_0+8(1); \
|
||||
lwz 1,FRAME_1+8(1); \
|
||||
mtsprg 2,2; /* save r2 & r3 */ \
|
||||
mtsprg 3,3; \
|
||||
/* Disable translation, machine check and recoverability: */ \
|
||||
mfmsr 2; \
|
||||
andi. 2,2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
|
||||
mtmsr 2; \
|
||||
isync; \
|
||||
/* Decide whether we return to user mode: */ \
|
||||
lwz 3,savearea+4(0); \
|
||||
mtcr 3; \
|
||||
bc 4,17,1f; /* branch if PSL_PR is false */ \
|
||||
/* Restore user & kernel access SR: */ \
|
||||
lis 2,_C_LABEL(curpm)@ha; /* get real address of pmap */ \
|
||||
lwz 2,_C_LABEL(curpm)@l(2); \
|
||||
lwz 3,PM_USRSR(2); \
|
||||
mtsr USER_SR,3; \
|
||||
lwz 3,PM_KERNELSR(2); \
|
||||
mtsr KERNEL_SR,3; \
|
||||
1: mfsprg 2,1; /* restore cr */ \
|
||||
mtcr 2; \
|
||||
lwz 2,savearea(0); \
|
||||
lwz 3,savearea+4(0); \
|
||||
mtsrr0 2; \
|
||||
mtsrr1 3; \
|
||||
mfsprg 2,2; /* restore r2 & r3 */ \
|
||||
mfsprg 3,3
|
||||
|
||||
/*
|
||||
* Preamble code for DSI/ISI traps
|
||||
*/
|
||||
disitrap:
|
||||
lmw 30,disisave(0)
|
||||
stmw 30,tempsave(0)
|
||||
lmw 30,disisave+8(0)
|
||||
stmw 30,tempsave+8(0)
|
||||
mfdar 30
|
||||
mfdsisr 31
|
||||
stmw 30,tempsave+16(0)
|
||||
realtrap:
|
||||
/* Test whether we already had PR set */
|
||||
mfsrr1 1
|
||||
mtcr 1
|
||||
mfsprg 1,1 /* restore SP (might have been
|
||||
overwritten) */
|
||||
bc 4,17,s_trap /* branch if PSL_PR is false */
|
||||
lis 1,_C_LABEL(curpcb)@ha
|
||||
lwz 1,_C_LABEL(curpcb)@l(1)
|
||||
addi 1,1,USPACE /* stack is top of user struct */
|
||||
|
||||
/*
|
||||
* Now the common trap catching code.
|
||||
*/
|
||||
s_trap:
|
||||
/* First have to enable KERNEL mapping */
|
||||
lis 31,KERNEL_SEGMENT@h
|
||||
ori 31,31,KERNEL_SEGMENT@l
|
||||
mtsr KERNEL_SR,31
|
||||
FRAME_SETUP(tempsave)
|
||||
/* Now we can recover interrupts again: */
|
||||
mfmsr 7
|
||||
ori 7,7,(PSL_EE|PSL_ME|PSL_RI)@l
|
||||
mtmsr 7
|
||||
isync
|
||||
/* Call C trap code: */
|
||||
trapagain:
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(trap)
|
||||
trapexit:
|
||||
/* Disable interrupts: */
|
||||
mfmsr 3
|
||||
andi. 3,3,~PSL_EE@l
|
||||
mtmsr 3
|
||||
/* Test AST pending: */
|
||||
lwz 5,FRAME_SRR1+8(1)
|
||||
mtcr 5
|
||||
bc 4,17,1f /* branch if PSL_PR is false */
|
||||
lis 3,_C_LABEL(astpending)@ha
|
||||
lwz 4,_C_LABEL(astpending)@l(3)
|
||||
andi. 4,4,1
|
||||
beq 1f
|
||||
li 6,EXC_AST
|
||||
stw 6,FRAME_EXC+8(1)
|
||||
b trapagain
|
||||
1:
|
||||
FRAME_LEAVE(tempsave)
|
||||
rfi
|
||||
|
||||
/*
|
||||
* Child comes here at the end of a fork.
|
||||
* Mostly similar to the above.
|
||||
* Return to userspace via the trap return path.
|
||||
*/
|
||||
.globl _C_LABEL(fork_trampoline)
|
||||
_C_LABEL(fork_trampoline):
|
||||
|
|
@ -979,367 +413,10 @@ _C_LABEL(fork_trampoline):
|
|||
b trapexit
|
||||
|
||||
/*
|
||||
* DSI second stage fault handler
|
||||
* Pull in common trap vector code.
|
||||
*/
|
||||
s_dsitrap:
|
||||
mfdsisr 31 /* test whether this may be a
|
||||
spill fault */
|
||||
mtcr 31
|
||||
mtsprg 1,1 /* save SP */
|
||||
bc 4,1,disitrap /* branch if table miss is false */
|
||||
lis 1,spillstk+SPILLSTK@ha
|
||||
addi 1,1,spillstk+SPILLSTK@l /* get spill stack */
|
||||
stwu 1,-52(1)
|
||||
stw 0,48(1) /* save non-volatile registers */
|
||||
stw 3,44(1)
|
||||
stw 4,40(1)
|
||||
stw 5,36(1)
|
||||
stw 6,32(1)
|
||||
stw 7,28(1)
|
||||
stw 8,24(1)
|
||||
stw 9,20(1)
|
||||
stw 10,16(1)
|
||||
stw 11,12(1)
|
||||
stw 12,8(1)
|
||||
mflr 30 /* save trap type */
|
||||
mfctr 31 /* & CTR */
|
||||
mfdar 3
|
||||
s_pte_spill:
|
||||
bl _C_LABEL(pte_spill) /* try a spill */
|
||||
or. 3,3,3
|
||||
mtctr 31 /* restore CTR */
|
||||
mtlr 30 /* and trap type */
|
||||
mfsprg 31,2 /* get saved XER */
|
||||
mtxer 31 /* restore XER */
|
||||
lwz 12,8(1) /* restore non-volatile registers */
|
||||
lwz 11,12(1)
|
||||
lwz 10,16(1)
|
||||
lwz 9,20(1)
|
||||
lwz 8,24(1)
|
||||
lwz 7,28(1)
|
||||
lwz 6,32(1)
|
||||
lwz 5,36(1)
|
||||
lwz 4,40(1)
|
||||
lwz 3,44(1)
|
||||
lwz 0,48(1)
|
||||
beq disitrap
|
||||
mfsprg 1,1 /* restore SP */
|
||||
mtcr 29 /* restore CR */
|
||||
mtlr 28 /* restore LR */
|
||||
lmw 28,disisave(0) /* restore r28-r31 */
|
||||
rfi /* return to trapped code */
|
||||
#include <powerpc/powerpc/trap_subr.S>
|
||||
|
||||
/*
|
||||
* ISI second stage fault handler
|
||||
*/
|
||||
s_isitrap:
|
||||
mfsrr1 31 /* test whether this may be a
|
||||
spill fault */
|
||||
mtcr 31
|
||||
mtsprg 1,1 /* save SP */
|
||||
bc 4,1,disitrap /* branch if table miss is false */
|
||||
lis 1,spillstk+SPILLSTK@ha
|
||||
addi 1,1,spillstk+SPILLSTK@l /* get spill stack */
|
||||
stwu 1,-52(1)
|
||||
stw 0,48(1) /* save non-volatile registers */
|
||||
stw 3,44(1)
|
||||
stw 4,40(1)
|
||||
stw 5,36(1)
|
||||
stw 6,32(1)
|
||||
stw 7,28(1)
|
||||
stw 8,24(1)
|
||||
stw 9,20(1)
|
||||
stw 10,16(1)
|
||||
stw 11,12(1)
|
||||
stw 12,8(1)
|
||||
mfxer 30 /* save XER */
|
||||
mtsprg 2,30
|
||||
mflr 30 /* save trap type */
|
||||
mfctr 31 /* & ctr */
|
||||
mfsrr0 3
|
||||
b s_pte_spill /* above */
|
||||
|
||||
/*
|
||||
* External interrupt second level handler
|
||||
*/
|
||||
#define INTRENTER \
|
||||
/* Save non-volatile registers: */ \
|
||||
stwu 1,-88(1); /* temporarily */ \
|
||||
stw 0,84(1); \
|
||||
mfsprg 0,1; /* get original SP */ \
|
||||
stw 0,0(1); /* and store it */ \
|
||||
stw 3,80(1); \
|
||||
stw 4,76(1); \
|
||||
stw 5,72(1); \
|
||||
stw 6,68(1); \
|
||||
stw 7,64(1); \
|
||||
stw 8,60(1); \
|
||||
stw 9,56(1); \
|
||||
stw 10,52(1); \
|
||||
stw 11,48(1); \
|
||||
stw 12,44(1); \
|
||||
stw 28,40(1); /* saved LR */ \
|
||||
stw 29,36(1); /* saved CR */ \
|
||||
stw 30,32(1); /* saved XER */ \
|
||||
lmw 28,tempsave(0); /* restore r28-r31 */ \
|
||||
mfctr 6; \
|
||||
lis 5,_C_LABEL(intr_depth)@ha; \
|
||||
lwz 5,_C_LABEL(intr_depth)@l(5); \
|
||||
mfsrr0 4; \
|
||||
mfsrr1 3; \
|
||||
stw 6,28(1); \
|
||||
stw 5,20(1); \
|
||||
stw 4,12(1); \
|
||||
stw 3,8(1); \
|
||||
/* interrupts are recoverable here, and enable translation */ \
|
||||
lis 3,(KERNEL_SEGMENT|SR_SUKEY|SR_PRKEY)@h; \
|
||||
ori 3,3,(KERNEL_SEGMENT|SR_SUKEY|SR_PRKEY)@l; \
|
||||
mtsr KERNEL_SR,3; \
|
||||
mfmsr 5; \
|
||||
ori 5,5,(PSL_IR|PSL_DR|PSL_RI); \
|
||||
mtmsr 5; \
|
||||
isync
|
||||
|
||||
.globl _C_LABEL(extint_call)
|
||||
extintr:
|
||||
INTRENTER
|
||||
_C_LABEL(extint_call):
|
||||
bl _C_LABEL(extint_call) /* to be filled in later */
|
||||
|
||||
intr_exit:
|
||||
/* Disable interrupts (should already be disabled) and MMU here: */
|
||||
mfmsr 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME|PSL_RI|PSL_DR|PSL_IR)@l
|
||||
mtmsr 3
|
||||
isync
|
||||
/* restore possibly overwritten registers: */
|
||||
lwz 12,44(1)
|
||||
lwz 11,48(1)
|
||||
lwz 10,52(1)
|
||||
lwz 9,56(1)
|
||||
lwz 8,60(1)
|
||||
lwz 7,64(1)
|
||||
lwz 6,8(1)
|
||||
lwz 5,12(1)
|
||||
lwz 4,28(1)
|
||||
lwz 3,32(1)
|
||||
mtsrr1 6
|
||||
mtsrr0 5
|
||||
mtctr 4
|
||||
mtxer 3
|
||||
/* Returning to user mode? */
|
||||
mtcr 6 /* saved SRR1 */
|
||||
bc 4,17,1f /* branch if PSL_PR is false */
|
||||
lis 3,_C_LABEL(curpm)@ha /* get current pmap real address */
|
||||
lwz 3,_C_LABEL(curpm)@l(3)
|
||||
lwz 3,PM_KERNELSR(3)
|
||||
mtsr KERNEL_SR,3 /* Restore kernel SR */
|
||||
lis 3,_C_LABEL(astpending)@ha /* Test AST pending */
|
||||
lwz 4,_C_LABEL(astpending)@l(3)
|
||||
andi. 4,4,1
|
||||
beq 1f
|
||||
/* Setup for entry to realtrap: */
|
||||
lwz 3,0(1) /* get saved SP */
|
||||
mtsprg 1,3
|
||||
li 6,EXC_AST
|
||||
stmw 28,tempsave(0) /* establish tempsave again */
|
||||
mtlr 6
|
||||
lwz 28,40(1) /* saved LR */
|
||||
lwz 29,36(1) /* saved CR */
|
||||
lwz 6,68(1)
|
||||
lwz 5,72(1)
|
||||
lwz 4,76(1)
|
||||
lwz 3,80(1)
|
||||
lwz 0,84(1)
|
||||
lis 30,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
|
||||
lwz 31,_C_LABEL(intr_depth)@l(30)
|
||||
addi 31,31,-1
|
||||
stw 31,_C_LABEL(intr_depth)@l(30)
|
||||
b realtrap
|
||||
1:
|
||||
/* Here is the normal exit of extintr: */
|
||||
lwz 5,36(1)
|
||||
lwz 6,40(1)
|
||||
mtcr 5
|
||||
mtlr 6
|
||||
lwz 6,68(1)
|
||||
lwz 5,72(1)
|
||||
lis 3,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
|
||||
lwz 4,_C_LABEL(intr_depth)@l(3)
|
||||
addi 4,4,-1
|
||||
stw 4,_C_LABEL(intr_depth)@l(3)
|
||||
lwz 4,76(1)
|
||||
lwz 3,80(1)
|
||||
lwz 0,84(1)
|
||||
lwz 1,0(1)
|
||||
rfi
|
||||
|
||||
/*
|
||||
* Decrementer interrupt second level handler
|
||||
*/
|
||||
decrintr:
|
||||
INTRENTER
|
||||
addi 3,1,8 /* intr frame */
|
||||
bl _C_LABEL(decr_intr)
|
||||
b intr_exit
|
||||
|
||||
#ifdef DDB
|
||||
/*
|
||||
* Deliberate entry to ddbtrap
|
||||
*/
|
||||
.globl _C_LABEL(ddb_trap)
|
||||
_C_LABEL(ddb_trap):
|
||||
mtsprg 1,1
|
||||
mfmsr 3
|
||||
mtsrr1 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME)@l
|
||||
mtmsr 3 /* disable interrupts */
|
||||
isync
|
||||
stmw 28,ddbsave(0)
|
||||
mflr 28
|
||||
li 29,EXC_BPT
|
||||
mtlr 29
|
||||
mfcr 29
|
||||
mtsrr0 28
|
||||
|
||||
/*
|
||||
* Now the ddb trap catching code.
|
||||
*/
|
||||
ddbtrap:
|
||||
FRAME_SETUP(ddbsave)
|
||||
/* Call C trap code: */
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(ddb_trap_glue)
|
||||
or. 3,3,3
|
||||
bne ddbleave
|
||||
/* This wasn't for DDB, so switch to real trap: */
|
||||
lwz 3,FRAME_EXC+8(1) /* save exception */
|
||||
stw 3,ddbsave+8(0)
|
||||
FRAME_LEAVE(ddbsave)
|
||||
mtsprg 1,1 /* prepare for entrance to realtrap */
|
||||
stmw 28,tempsave(0)
|
||||
mflr 28
|
||||
mfcr 29
|
||||
lwz 31,ddbsave+8(0)
|
||||
mtlr 31
|
||||
b realtrap
|
||||
ddbleave:
|
||||
FRAME_LEAVE(ddbsave)
|
||||
rfi
|
||||
#endif /* DDB */
|
||||
|
||||
#ifdef IPKDB
|
||||
/*
|
||||
* Deliberate entry to ipkdbtrap
|
||||
*/
|
||||
.globl _C_LABEL(ipkdb_trap)
|
||||
_C_LABEL(ipkdb_trap):
|
||||
mtsprg 1,1
|
||||
mfmsr 3
|
||||
mtsrr1 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME)@l
|
||||
mtmsr 3 /* disable interrupts */
|
||||
isync
|
||||
stmw 28,ipkdbsave(0)
|
||||
mflr 28
|
||||
li 29,EXC_BPT
|
||||
mtlr 29
|
||||
mfcr 29
|
||||
mtsrr0 28
|
||||
|
||||
/*
|
||||
* Now the ipkdb trap catching code.
|
||||
*/
|
||||
ipkdbtrap:
|
||||
FRAME_SETUP(ipkdbsave)
|
||||
/* Call C trap code: */
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(ipkdb_trap_glue)
|
||||
or. 3,3,3
|
||||
bne ipkdbleave
|
||||
/* This wasn't for IPKDB, so switch to real trap: */
|
||||
lwz 3,FRAME_EXC+8(1) /* save exception */
|
||||
stw 3,ipkdbsave+8(0)
|
||||
FRAME_LEAVE(ipkdbsave)
|
||||
mtsprg 1,1 /* prepare for entrance to realtrap */
|
||||
stmw 28,tempsave(0)
|
||||
mflr 28
|
||||
mfcr 29
|
||||
lwz 31,ipkdbsave+8(0)
|
||||
mtlr 31
|
||||
b realtrap
|
||||
ipkdbleave:
|
||||
FRAME_LEAVE(ipkdbsave)
|
||||
rfi
|
||||
|
||||
ipkdbfault:
|
||||
ba _ipkdbfault
|
||||
_ipkdbfault:
|
||||
mfsrr0 3
|
||||
addi 3,3,4
|
||||
mtsrr0 3
|
||||
li 3,-1
|
||||
rfi
|
||||
|
||||
/*
|
||||
* int ipkdbfbyte(unsigned char *p)
|
||||
*/
|
||||
.globl _C_LABEL(ipkdbfbyte)
|
||||
_C_LABEL(ipkdbfbyte):
|
||||
li 9,EXC_DSI /* establish new fault routine */
|
||||
lwz 5,0(9)
|
||||
lis 6,ipkdbfault@ha
|
||||
lwz 6,ipkdbfault@l(6)
|
||||
stw 6,0(9)
|
||||
#ifdef IPKDBUSERHACK
|
||||
lis 8,_C_LABEL(ipkdbsr)@ha
|
||||
lwz 8,_C_LABEL(ipkdbsr)@l(8)
|
||||
mtsr USER_SR,8
|
||||
isync
|
||||
#endif
|
||||
dcbst 0,9 /* flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
lbz 3,0(3) /* fetch data */
|
||||
stw 5,0(9) /* restore previous fault handler */
|
||||
dcbst 0,9 /* and flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
blr
|
||||
|
||||
/*
|
||||
* int ipkdbsbyte(unsigned char *p, int c)
|
||||
*/
|
||||
.globl _C_LABEL(ipkdbsbyte)
|
||||
_C_LABEL(ipkdbsbyte):
|
||||
li 9,EXC_DSI /* establish new fault routine */
|
||||
lwz 5,0(9)
|
||||
lis 6,ipkdbfault@ha
|
||||
lwz 6,ipkdbfault@l(6)
|
||||
stw 6,0(9)
|
||||
#ifdef IPKDBUSERHACK
|
||||
lis 8,_C_LABEL(ipkdbsr)@ha
|
||||
lwz 8,_C_LABEL(ipkdbsr)@l(8)
|
||||
mtsr USER_SR,8
|
||||
isync
|
||||
#endif
|
||||
dcbst 0,9 /* flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
mr 6,3
|
||||
xor 3,3,3
|
||||
stb 4,0(6)
|
||||
dcbst 0,6 /* Now do appropriate flushes
|
||||
to data... */
|
||||
sync
|
||||
icbi 0,6 /* and instruction caches */
|
||||
stw 5,0(9) /* restore previous fault handler */
|
||||
dcbst 0,9 /* and flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
blr
|
||||
#endif /* IPKDB */
|
||||
|
||||
/*
|
||||
* int setfault()
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: locore.S,v 1.27 2000/08/21 18:46:03 tsubai Exp $ */
|
||||
/* $NetBSD: locore.S,v 1.28 2000/11/16 05:34:03 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
|
||||
|
|
@ -593,600 +593,9 @@ switch_return:
|
|||
mtlr 0
|
||||
blr
|
||||
|
||||
|
||||
/*
|
||||
* Data used during primary/secondary traps/interrupts
|
||||
*/
|
||||
#define tempsave 0x2e0 /* primary save area for trap handling */
|
||||
#define disisave 0x3e0 /* primary save area for dsi/isi traps */
|
||||
|
||||
#define INTSTK (8*1024) /* 8K interrupt stack */
|
||||
.data
|
||||
.align 4
|
||||
intstk:
|
||||
.space INTSTK /* interrupt stack */
|
||||
|
||||
GLOBAL(intr_depth)
|
||||
.long -1 /* in-use marker */
|
||||
|
||||
#define SPILLSTK 1024 /* 1K spill stack */
|
||||
|
||||
.comm spillstk,SPILLSTK,8
|
||||
|
||||
/*
|
||||
* This code gets copied to all the trap vectors
|
||||
* (except ISI/DSI, ALI, the interrupts, and possibly the debugging
|
||||
* traps when using IPKDB).
|
||||
*/
|
||||
.text
|
||||
.globl _C_LABEL(trapcode),_C_LABEL(trapsize)
|
||||
_C_LABEL(trapcode):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
/* Test whether we already had PR set */
|
||||
mfsrr1 31
|
||||
mtcr 31
|
||||
bc 4,17,1f /* branch if PSL_PR is clear */
|
||||
#if defined(MULTIPROCESSOR)
|
||||
GET_CPUINFO(1)
|
||||
lwz 1,CI_CURPCB(1)
|
||||
#else
|
||||
lis 1,_C_LABEL(curpcb)@ha
|
||||
lwz 1,_C_LABEL(curpcb)@l(1)
|
||||
#endif
|
||||
addi 1,1,USPACE /* stack is top of user struct */
|
||||
1:
|
||||
bla s_trap
|
||||
_C_LABEL(trapsize) = .-_C_LABEL(trapcode)
|
||||
|
||||
/*
|
||||
* For ALI: has to save DSISR and DAR
|
||||
*/
|
||||
.globl _C_LABEL(alitrap),_C_LABEL(alisize)
|
||||
_C_LABEL(alitrap):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mfdar 30
|
||||
mfdsisr 31
|
||||
stmw 30,tempsave+16(0)
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
/* Test whether we already had PR set */
|
||||
mfsrr1 31
|
||||
mtcr 31
|
||||
bc 4,17,1f /* branch if PSL_PR is clear */
|
||||
#if defined(MULTIPROCESSOR)
|
||||
GET_CPUINFO(1)
|
||||
lwz 1,CI_CURPCB(1)
|
||||
#else
|
||||
lis 1,_C_LABEL(curpcb)@ha
|
||||
lwz 1,_C_LABEL(curpcb)@l(1)
|
||||
#endif
|
||||
addi 1,1,USPACE /* stack is top of user struct */
|
||||
1:
|
||||
bla s_trap
|
||||
_C_LABEL(alisize) = .-_C_LABEL(alitrap)
|
||||
|
||||
/*
|
||||
* Similar to the above for DSI
|
||||
* Has to handle BAT spills
|
||||
* and standard pagetable spills
|
||||
*/
|
||||
.globl _C_LABEL(dsitrap),_C_LABEL(dsisize)
|
||||
_C_LABEL(dsitrap):
|
||||
stmw 28,disisave(0) /* free r28-r31 */
|
||||
mfcr 29 /* save CR */
|
||||
mfxer 30 /* save XER */
|
||||
mtsprg 2,30 /* in SPRG2 */
|
||||
mfsrr1 31 /* test kernel mode */
|
||||
mtcr 31
|
||||
bc 12,17,1f /* branch if PSL_PR is set */
|
||||
mfdar 31 /* get fault address */
|
||||
rlwinm 31,31,7,25,28 /* get segment * 8 */
|
||||
|
||||
/* get batu */
|
||||
addis 31,31,_C_LABEL(battable)@ha
|
||||
lwz 30,_C_LABEL(battable)@l(31)
|
||||
mtcr 30
|
||||
bc 4,30,1f /* branch if supervisor valid is
|
||||
false */
|
||||
/* get batl */
|
||||
lwz 31,_C_LABEL(battable)+4@l(31)
|
||||
/* We randomly use the highest two bat registers here */
|
||||
mftb 28
|
||||
andi. 28,28,1
|
||||
bne 2f
|
||||
mtdbatu 2,30
|
||||
mtdbatl 2,31
|
||||
b 3f
|
||||
2:
|
||||
mtdbatu 3,30
|
||||
mtdbatl 3,31
|
||||
3:
|
||||
mfsprg 30,2 /* restore XER */
|
||||
mtxer 30
|
||||
mtcr 29 /* restore CR */
|
||||
lmw 28,disisave(0) /* restore r28-r31 */
|
||||
rfi /* return to trapped code */
|
||||
1:
|
||||
mflr 28 /* save LR */
|
||||
bla s_dsitrap
|
||||
_C_LABEL(dsisize) = .-_C_LABEL(dsitrap)
|
||||
|
||||
/*
|
||||
* Similar to the above for ISI
|
||||
*/
|
||||
.globl _C_LABEL(isitrap),_C_LABEL(isisize)
|
||||
_C_LABEL(isitrap):
|
||||
stmw 28,disisave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
mfsrr1 31 /* test kernel mode */
|
||||
mtcr 31
|
||||
bc 12,17,1f /* branch if PSL_PR is set */
|
||||
mfsrr0 31 /* get fault address */
|
||||
rlwinm 31,31,7,25,28 /* get segment * 8 */
|
||||
|
||||
/* get batu */
|
||||
addis 31,31,_C_LABEL(battable)@ha
|
||||
lwz 30,_C_LABEL(battable)@l(31)
|
||||
mtcr 30
|
||||
bc 4,30,1f /* branch if supervisor valid is
|
||||
false */
|
||||
mtibatu 3,30
|
||||
|
||||
/* get batl */
|
||||
lwz 30,_C_LABEL(battable)+4@l(31)
|
||||
mtibatl 3,30
|
||||
|
||||
mtcr 29 /* restore CR */
|
||||
lmw 28,disisave(0) /* restore r28-r31 */
|
||||
rfi /* return to trapped code */
|
||||
1:
|
||||
bla s_isitrap
|
||||
_C_LABEL(isisize)= .-_C_LABEL(isitrap)
|
||||
|
||||
/*
|
||||
* This one for the external interrupt handler.
|
||||
*/
|
||||
.globl _C_LABEL(extint),_C_LABEL(extsize)
|
||||
_C_LABEL(extint):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
mfxer 30 /* save XER */
|
||||
lis 1,intstk+INTSTK@ha /* get interrupt stack */
|
||||
addi 1,1,intstk+INTSTK@l
|
||||
lwz 31,0(1) /* were we already running on intstk? */
|
||||
addic. 31,31,1
|
||||
stw 31,0(1)
|
||||
beq 1f
|
||||
mfsprg 1,1 /* yes, get old SP */
|
||||
1:
|
||||
ba extintr
|
||||
_C_LABEL(extsize) = .-_C_LABEL(extint)
|
||||
|
||||
/*
|
||||
* And this one for the decrementer interrupt handler.
|
||||
*/
|
||||
.globl _C_LABEL(decrint),_C_LABEL(decrsize)
|
||||
_C_LABEL(decrint):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
mfxer 30 /* save XER */
|
||||
lis 1,intstk+INTSTK@ha /* get interrupt stack */
|
||||
addi 1,1,intstk+INTSTK@l
|
||||
lwz 31,0(1) /* were we already running on intstk? */
|
||||
addic. 31,31,1
|
||||
stw 31,0(1)
|
||||
beq 1f
|
||||
mfsprg 1,1 /* yes, get old SP */
|
||||
1:
|
||||
ba decrintr
|
||||
_C_LABEL(decrsize) = .-_C_LABEL(decrint)
|
||||
|
||||
/*
|
||||
* Now the tlb software load for 603 processors:
|
||||
* (Code essentially from the 603e User Manual, Chapter 5, but
|
||||
* corrected a lot.)
|
||||
*/
|
||||
#define DMISS 976
|
||||
#define DCMP 977
|
||||
#define HASH1 978
|
||||
#define HASH2 979
|
||||
#define IMISS 980
|
||||
#define ICMP 981
|
||||
#define RPA 982
|
||||
|
||||
.globl _C_LABEL(tlbimiss),_C_LABEL(tlbimsize)
|
||||
_C_LABEL(tlbimiss):
|
||||
mfspr 2,HASH1 /* get first pointer */
|
||||
li 1,8
|
||||
mfctr 0 /* save counter */
|
||||
mfspr 3,ICMP /* get first compare value */
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
1:
|
||||
mtctr 1 /* load counter */
|
||||
2:
|
||||
lwzu 1,8(2) /* get next pte */
|
||||
cmpl 0,1,3 /* see if found pte */
|
||||
bdneq 2b /* loop if not eq */
|
||||
bne 3f /* not found */
|
||||
lwz 1,4(2) /* load tlb entry lower word */
|
||||
andi. 3,1,8 /* check G-bit */
|
||||
bne 4f /* if guarded, take ISI */
|
||||
mtctr 0 /* restore counter */
|
||||
mfspr 0,IMISS /* get the miss address for the tlbli */
|
||||
mfsrr1 3 /* get the saved cr0 bits */
|
||||
mtcrf 0x80,3 /* and restore */
|
||||
ori 1,1,0x100 /* set the reference bit */
|
||||
mtspr RPA,1 /* set the pte */
|
||||
srwi 1,1,8 /* get byte 7 of pte */
|
||||
tlbli 0 /* load the itlb */
|
||||
stb 1,6(2) /* update page table */
|
||||
rfi
|
||||
|
||||
3: /* not found in pteg */
|
||||
andi. 1,3,0x40 /* have we already done second hash? */
|
||||
bne 5f
|
||||
mfspr 2,HASH2 /* get the second pointer */
|
||||
ori 3,3,0x40 /* change the compare value */
|
||||
li 1,8
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
b 1b
|
||||
4: /* guarded */
|
||||
mfsrr1 3
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
oris 2,2,0x8000000@h /* set srr<4> to flag prot violation */
|
||||
b 6f
|
||||
5: /* not found anywhere */
|
||||
mfsrr1 3
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
oris 2,2,0x40000000@h /* set srr1<1> to flag pte not found */
|
||||
6:
|
||||
mtctr 0 /* restore counter */
|
||||
mtsrr1 2
|
||||
mfmsr 0
|
||||
xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
|
||||
mtcrf 0x80,3 /* restore cr0 */
|
||||
mtmsr 0 /* now with native gprs */
|
||||
isync
|
||||
ba EXC_ISI
|
||||
_C_LABEL(tlbimsize) = .-_C_LABEL(tlbimiss)
|
||||
|
||||
.globl _C_LABEL(tlbdlmiss),_C_LABEL(tlbdlmsize)
|
||||
_C_LABEL(tlbdlmiss):
|
||||
mfspr 2,HASH1 /* get first pointer */
|
||||
li 1,8
|
||||
mfctr 0 /* save counter */
|
||||
mfspr 3,DCMP /* get first compare value */
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
1:
|
||||
mtctr 1 /* load counter */
|
||||
2:
|
||||
lwzu 1,8(2) /* get next pte */
|
||||
cmpl 0,1,3 /* see if found pte */
|
||||
bdneq 2b /* loop if not eq */
|
||||
bne 3f /* not found */
|
||||
lwz 1,4(2) /* load tlb entry lower word */
|
||||
mtctr 0 /* restore counter */
|
||||
mfspr 0,DMISS /* get the miss address for the tlbld */
|
||||
mfsrr1 3 /* get the saved cr0 bits */
|
||||
mtcrf 0x80,3 /* and restore */
|
||||
ori 1,1,0x100 /* set the reference bit */
|
||||
mtspr RPA,1 /* set the pte */
|
||||
srwi 1,1,8 /* get byte 7 of pte */
|
||||
tlbld 0 /* load the dtlb */
|
||||
stb 1,6(2) /* update page table */
|
||||
rfi
|
||||
|
||||
3: /* not found in pteg */
|
||||
andi. 1,3,0x40 /* have we already done second hash? */
|
||||
bne 5f
|
||||
mfspr 2,HASH2 /* get the second pointer */
|
||||
ori 3,3,0x40 /* change the compare value */
|
||||
li 1,8
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
b 1b
|
||||
5: /* not found anywhere */
|
||||
mfsrr1 3
|
||||
lis 1,0x40000000@h /* set dsisr<1> to flag pte not found */
|
||||
mtctr 0 /* restore counter */
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
mtsrr1 2
|
||||
mtdsisr 1 /* load the dsisr */
|
||||
mfspr 1,DMISS /* get the miss address */
|
||||
mtdar 1 /* put in dar */
|
||||
mfmsr 0
|
||||
xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
|
||||
mtcrf 0x80,3 /* restore cr0 */
|
||||
mtmsr 0 /* now with native gprs */
|
||||
isync
|
||||
ba EXC_DSI
|
||||
_C_LABEL(tlbdlmsize) = .-_C_LABEL(tlbdlmiss)
|
||||
|
||||
.globl _C_LABEL(tlbdsmiss),_C_LABEL(tlbdsmsize)
|
||||
_C_LABEL(tlbdsmiss):
|
||||
mfspr 2,HASH1 /* get first pointer */
|
||||
li 1,8
|
||||
mfctr 0 /* save counter */
|
||||
mfspr 3,DCMP /* get first compare value */
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
1:
|
||||
mtctr 1 /* load counter */
|
||||
2:
|
||||
lwzu 1,8(2) /* get next pte */
|
||||
cmpl 0,1,3 /* see if found pte */
|
||||
bdneq 2b /* loop if not eq */
|
||||
bne 3f /* not found */
|
||||
lwz 1,4(2) /* load tlb entry lower word */
|
||||
andi. 3,1,0x80 /* check the C-bit */
|
||||
beq 4f
|
||||
5:
|
||||
mtctr 0 /* restore counter */
|
||||
mfspr 0,DMISS /* get the miss address for the tlbld */
|
||||
mfsrr1 3 /* get the saved cr0 bits */
|
||||
mtcrf 0x80,3 /* and restore */
|
||||
mtspr RPA,1 /* set the pte */
|
||||
tlbld 0 /* load the dtlb */
|
||||
rfi
|
||||
|
||||
3: /* not found in pteg */
|
||||
andi. 1,3,0x40 /* have we already done second hash? */
|
||||
bne 5f
|
||||
mfspr 2,HASH2 /* get the second pointer */
|
||||
ori 3,3,0x40 /* change the compare value */
|
||||
li 1,8
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
b 1b
|
||||
4: /* found, but C-bit = 0 */
|
||||
rlwinm. 3,1,30,0,1 /* test PP */
|
||||
bge- 7f
|
||||
andi. 3,1,1
|
||||
beq+ 8f
|
||||
9: /* found, but protection violation (PP==00)*/
|
||||
mfsrr1 3
|
||||
lis 1,0xa000000@h /* indicate protection violation
|
||||
on store */
|
||||
b 1f
|
||||
7: /* found, PP=1x */
|
||||
mfspr 3,DMISS /* get the miss address */
|
||||
mfsrin 1,3 /* get the segment register */
|
||||
mfsrr1 3
|
||||
rlwinm 3,3,18,31,31 /* get PR-bit */
|
||||
rlwnm. 2,2,3,1,1 /* get the key */
|
||||
bne- 9b /* protection violation */
|
||||
8: /* found, set reference/change bits */
|
||||
lwz 1,4(2) /* reload tlb entry */
|
||||
ori 1,1,0x180
|
||||
sth 1,6(2)
|
||||
b 5b
|
||||
5: /* not found anywhere */
|
||||
mfsrr1 3
|
||||
lis 1,0x42000000@h /* set dsisr<1> to flag pte not found */
|
||||
/* dsisr<6> to flag store */
|
||||
1:
|
||||
mtctr 0 /* restore counter */
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
mtsrr1 2
|
||||
mtdsisr 1 /* load the dsisr */
|
||||
mfspr 1,DMISS /* get the miss address */
|
||||
mtdar 1 /* put in dar */
|
||||
mfmsr 0
|
||||
xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
|
||||
mtcrf 0x80,3 /* restore cr0 */
|
||||
mtmsr 0 /* now with native gprs */
|
||||
isync
|
||||
ba EXC_DSI
|
||||
_C_LABEL(tlbdsmsize) = .-_C_LABEL(tlbdsmiss)
|
||||
|
||||
#ifdef DDB
|
||||
#define ddbsave 0xde0 /* primary save area for DDB */
|
||||
/*
|
||||
* In case of DDB we want a separate trap catcher for it
|
||||
*/
|
||||
.local ddbstk
|
||||
.comm ddbstk,INTSTK,8 /* ddb stack */
|
||||
|
||||
.globl _C_LABEL(ddblow),_C_LABEL(ddbsize)
|
||||
_C_LABEL(ddblow):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,ddbsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
lis 1,ddbstk+INTSTK@ha /* get new SP */
|
||||
addi 1,1,ddbstk+INTSTK@l
|
||||
bla ddbtrap
|
||||
_C_LABEL(ddbsize) = .-_C_LABEL(ddblow)
|
||||
#endif /* DDB */
|
||||
|
||||
#ifdef IPKDB
|
||||
#define ipkdbsave 0xde0 /* primary save area for IPKDB */
|
||||
/*
|
||||
* In case of IPKDB we want a separate trap catcher for it
|
||||
*/
|
||||
|
||||
.local ipkdbstk
|
||||
.comm ipkdbstk,INTSTK,8 /* ipkdb stack */
|
||||
|
||||
.globl _C_LABEL(ipkdblow),_C_LABEL(ipkdbsize)
|
||||
_C_LABEL(ipkdblow):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,ipkdbsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
lis 1,ipkdbstk+INTSTK@ha /* get new SP */
|
||||
addi 1,1,ipkdbstk+INTSTK@l
|
||||
bla ipkdbtrap
|
||||
_C_LABEL(ipkdbsize) = .-_C_LABEL(ipkdblow)
|
||||
#endif /* IPKDB */
|
||||
|
||||
/*
|
||||
* FRAME_SETUP assumes:
|
||||
* SPRG1 SP (1)
|
||||
* savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
|
||||
* 28 LR
|
||||
* 29 CR
|
||||
* 1 kernel stack
|
||||
* LR trap type
|
||||
* SRR0/1 as at start of trap
|
||||
*/
|
||||
#define FRAME_SETUP(savearea) \
|
||||
/* Have to enable translation to allow access of kernel stack: */ \
|
||||
mfsrr0 30; \
|
||||
mfsrr1 31; \
|
||||
stmw 30,savearea+24(0); \
|
||||
mfmsr 30; \
|
||||
ori 30,30,(PSL_DR|PSL_IR); \
|
||||
mtmsr 30; \
|
||||
isync; \
|
||||
mfsprg 31,1; \
|
||||
stwu 31,-FRAMELEN(1); \
|
||||
stw 0,FRAME_0+8(1); \
|
||||
stw 31,FRAME_1+8(1); \
|
||||
stw 28,FRAME_LR+8(1); \
|
||||
stw 29,FRAME_CR+8(1); \
|
||||
lmw 28,savearea(0); \
|
||||
stmw 2,FRAME_2+8(1); \
|
||||
lmw 28,savearea+16(0); \
|
||||
mfxer 3; \
|
||||
mfctr 4; \
|
||||
mflr 5; \
|
||||
andi. 5,5,0xff00; \
|
||||
stw 3,FRAME_XER+8(1); \
|
||||
stw 4,FRAME_CTR+8(1); \
|
||||
stw 5,FRAME_EXC+8(1); \
|
||||
stw 28,FRAME_DAR+8(1); \
|
||||
stw 29,FRAME_DSISR+8(1); \
|
||||
stw 30,FRAME_SRR0+8(1); \
|
||||
stw 31,FRAME_SRR1+8(1)
|
||||
|
||||
#define FRAME_LEAVE(savearea) \
|
||||
/* Now restore regs: */ \
|
||||
lwz 2,FRAME_SRR0+8(1); \
|
||||
lwz 3,FRAME_SRR1+8(1); \
|
||||
lwz 4,FRAME_CTR+8(1); \
|
||||
lwz 5,FRAME_XER+8(1); \
|
||||
lwz 6,FRAME_LR+8(1); \
|
||||
lwz 7,FRAME_CR+8(1); \
|
||||
stw 2,savearea(0); \
|
||||
stw 3,savearea+4(0); \
|
||||
mtctr 4; \
|
||||
mtxer 5; \
|
||||
mtlr 6; \
|
||||
mtsprg 1,7; /* save cr */ \
|
||||
lmw 2,FRAME_2+8(1); \
|
||||
lwz 0,FRAME_0+8(1); \
|
||||
lwz 1,FRAME_1+8(1); \
|
||||
mtsprg 2,2; /* save r2 & r3 */ \
|
||||
mtsprg 3,3; \
|
||||
/* Disable translation, machine check and recoverability: */ \
|
||||
mfmsr 2; \
|
||||
andi. 2,2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
|
||||
mtmsr 2; \
|
||||
isync; \
|
||||
/* Decide whether we return to user mode: */ \
|
||||
lwz 3,savearea+4(0); \
|
||||
mtcr 3; \
|
||||
bc 4,17,1f; /* branch if PSL_PR is false */ \
|
||||
/* Restore user & kernel access SR: */ \
|
||||
GET_CURPM(2); /* get real address of pmap */ \
|
||||
lwz 3,PM_USRSR(2); \
|
||||
mtsr USER_SR,3; \
|
||||
lwz 3,PM_KERNELSR(2); \
|
||||
mtsr KERNEL_SR,3; \
|
||||
1: mfsprg 2,1; /* restore cr */ \
|
||||
mtcr 2; \
|
||||
lwz 2,savearea(0); \
|
||||
lwz 3,savearea+4(0); \
|
||||
mtsrr0 2; \
|
||||
mtsrr1 3; \
|
||||
mfsprg 2,2; /* restore r2 & r3 */ \
|
||||
mfsprg 3,3
|
||||
|
||||
#if defined(MULTIPROCESSOR)
|
||||
#define GET_CURPM(r) \
|
||||
GET_CPUINFO(r); \
|
||||
lwz r,CI_CURPM(r);
|
||||
#else
|
||||
#define GET_CURPM(r) \
|
||||
lis r,_C_LABEL(curpm)@ha; \
|
||||
lwz r,_C_LABEL(curpm)@l(r);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Preamble code for DSI/ISI traps
|
||||
*/
|
||||
disitrap:
|
||||
lmw 30,disisave(0)
|
||||
stmw 30,tempsave(0)
|
||||
lmw 30,disisave+8(0)
|
||||
stmw 30,tempsave+8(0)
|
||||
mfdar 30
|
||||
mfdsisr 31
|
||||
stmw 30,tempsave+16(0)
|
||||
realtrap:
|
||||
/* Test whether we already had PR set */
|
||||
mfsrr1 1
|
||||
mtcr 1
|
||||
mfsprg 1,1 /* restore SP (might have been
|
||||
overwritten) */
|
||||
bc 4,17,s_trap /* branch if PSL_PR is false */
|
||||
#if defined(MULTIPROCESSOR)
|
||||
GET_CPUINFO(1)
|
||||
lwz 1,CI_CURPCB(1)
|
||||
#else
|
||||
lis 1,_C_LABEL(curpcb)@ha
|
||||
lwz 1,_C_LABEL(curpcb)@l(1)
|
||||
#endif
|
||||
addi 1,1,USPACE /* stack is top of user struct */
|
||||
|
||||
/*
|
||||
* Now the common trap catching code.
|
||||
*/
|
||||
s_trap:
|
||||
/* First have to enable KERNEL mapping */
|
||||
lis 31,KERNEL_SEGMENT@h
|
||||
ori 31,31,KERNEL_SEGMENT@l
|
||||
mtsr KERNEL_SR,31
|
||||
FRAME_SETUP(tempsave)
|
||||
/* Now we can recover interrupts again: */
|
||||
mfmsr 7
|
||||
ori 7,7,(PSL_EE|PSL_ME|PSL_RI)@l
|
||||
mtmsr 7
|
||||
isync
|
||||
/* Call C trap code: */
|
||||
trapagain:
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(trap)
|
||||
trapexit:
|
||||
/* Disable interrupts: */
|
||||
mfmsr 3
|
||||
andi. 3,3,~PSL_EE@l
|
||||
mtmsr 3
|
||||
/* Test AST pending: */
|
||||
lwz 5,FRAME_SRR1+8(1)
|
||||
mtcr 5
|
||||
bc 4,17,1f /* branch if PSL_PR is false */
|
||||
lis 3,_C_LABEL(astpending)@ha
|
||||
lwz 4,_C_LABEL(astpending)@l(3)
|
||||
andi. 4,4,1
|
||||
beq 1f
|
||||
li 6,EXC_AST
|
||||
stw 6,FRAME_EXC+8(1)
|
||||
b trapagain
|
||||
1:
|
||||
FRAME_LEAVE(tempsave)
|
||||
rfi
|
||||
|
||||
/*
|
||||
* Child comes here at the end of a fork.
|
||||
* Mostly similar to the above.
|
||||
* Return to userspace via the trap return path.
|
||||
*/
|
||||
.globl _C_LABEL(fork_trampoline)
|
||||
_C_LABEL(fork_trampoline):
|
||||
|
|
@ -1198,372 +607,10 @@ _C_LABEL(fork_trampoline):
|
|||
b trapexit
|
||||
|
||||
/*
|
||||
* DSI second stage fault handler
|
||||
* Pull in common trap vector code.
|
||||
*/
|
||||
s_dsitrap:
|
||||
mfdsisr 31 /* test whether this may be a
|
||||
spill fault */
|
||||
mtcr 31
|
||||
mtsprg 1,1 /* save SP */
|
||||
bc 4,1,disitrap /* branch if table miss is false */
|
||||
lis 1,spillstk+SPILLSTK@ha
|
||||
addi 1,1,spillstk+SPILLSTK@l /* get spill stack */
|
||||
stwu 1,-52(1)
|
||||
stw 0,48(1) /* save non-volatile registers */
|
||||
stw 3,44(1)
|
||||
stw 4,40(1)
|
||||
stw 5,36(1)
|
||||
stw 6,32(1)
|
||||
stw 7,28(1)
|
||||
stw 8,24(1)
|
||||
stw 9,20(1)
|
||||
stw 10,16(1)
|
||||
stw 11,12(1)
|
||||
stw 12,8(1)
|
||||
mflr 30 /* save trap type */
|
||||
mfctr 31 /* & CTR */
|
||||
mfdar 3
|
||||
s_pte_spill:
|
||||
bl _C_LABEL(pte_spill) /* try a spill */
|
||||
or. 3,3,3
|
||||
mtctr 31 /* restore CTR */
|
||||
mtlr 30 /* and trap type */
|
||||
mfsprg 31,2 /* get saved XER */
|
||||
mtxer 31 /* restore XER */
|
||||
lwz 12,8(1) /* restore non-volatile registers */
|
||||
lwz 11,12(1)
|
||||
lwz 10,16(1)
|
||||
lwz 9,20(1)
|
||||
lwz 8,24(1)
|
||||
lwz 7,28(1)
|
||||
lwz 6,32(1)
|
||||
lwz 5,36(1)
|
||||
lwz 4,40(1)
|
||||
lwz 3,44(1)
|
||||
lwz 0,48(1)
|
||||
beq disitrap
|
||||
mfsprg 1,1 /* restore SP */
|
||||
mtcr 29 /* restore CR */
|
||||
mtlr 28 /* restore LR */
|
||||
lmw 28,disisave(0) /* restore r28-r31 */
|
||||
rfi /* return to trapped code */
|
||||
#include <powerpc/powerpc/trap_subr.S>
|
||||
|
||||
/*
|
||||
* ISI second stage fault handler
|
||||
*/
|
||||
s_isitrap:
|
||||
mfsrr1 31 /* test whether this may be a
|
||||
spill fault */
|
||||
mtcr 31
|
||||
mtsprg 1,1 /* save SP */
|
||||
bc 4,1,disitrap /* branch if table miss is false */
|
||||
lis 1,spillstk+SPILLSTK@ha
|
||||
addi 1,1,spillstk+SPILLSTK@l /* get spill stack */
|
||||
stwu 1,-52(1)
|
||||
stw 0,48(1) /* save non-volatile registers */
|
||||
stw 3,44(1)
|
||||
stw 4,40(1)
|
||||
stw 5,36(1)
|
||||
stw 6,32(1)
|
||||
stw 7,28(1)
|
||||
stw 8,24(1)
|
||||
stw 9,20(1)
|
||||
stw 10,16(1)
|
||||
stw 11,12(1)
|
||||
stw 12,8(1)
|
||||
mfxer 30 /* save XER */
|
||||
mtsprg 2,30
|
||||
mflr 30 /* save trap type */
|
||||
mfctr 31 /* & ctr */
|
||||
mfsrr0 3
|
||||
b s_pte_spill /* above */
|
||||
|
||||
/*
|
||||
* External interrupt second level handler
|
||||
*/
|
||||
#define INTRENTER \
|
||||
/* Save non-volatile registers: */ \
|
||||
stwu 1,-88(1); /* temporarily */ \
|
||||
stw 0,84(1); \
|
||||
mfsprg 0,1; /* get original SP */ \
|
||||
stw 0,0(1); /* and store it */ \
|
||||
stw 3,80(1); \
|
||||
stw 4,76(1); \
|
||||
stw 5,72(1); \
|
||||
stw 6,68(1); \
|
||||
stw 7,64(1); \
|
||||
stw 8,60(1); \
|
||||
stw 9,56(1); \
|
||||
stw 10,52(1); \
|
||||
stw 11,48(1); \
|
||||
stw 12,44(1); \
|
||||
stw 28,40(1); /* saved LR */ \
|
||||
stw 29,36(1); /* saved CR */ \
|
||||
stw 30,32(1); /* saved XER */ \
|
||||
lmw 28,tempsave(0); /* restore r28-r31 */ \
|
||||
mfctr 6; \
|
||||
lis 5,_C_LABEL(intr_depth)@ha; \
|
||||
lwz 5,_C_LABEL(intr_depth)@l(5); \
|
||||
mfsrr0 4; \
|
||||
mfsrr1 3; \
|
||||
stw 6,28(1); \
|
||||
stw 5,20(1); \
|
||||
stw 4,12(1); \
|
||||
stw 3,8(1); \
|
||||
/* interrupts are recoverable here, and enable translation */ \
|
||||
lis 3,(KERNEL_SEGMENT|SR_SUKEY|SR_PRKEY)@h; \
|
||||
ori 3,3,(KERNEL_SEGMENT|SR_SUKEY|SR_PRKEY)@l; \
|
||||
mtsr KERNEL_SR,3; \
|
||||
mfmsr 5; \
|
||||
ori 5,5,(PSL_IR|PSL_DR|PSL_RI); \
|
||||
mtmsr 5; \
|
||||
isync
|
||||
|
||||
.globl _C_LABEL(extint_call)
|
||||
extintr:
|
||||
INTRENTER
|
||||
_C_LABEL(extint_call):
|
||||
bl _C_LABEL(extint_call) /* to be filled in later */
|
||||
|
||||
intr_exit:
|
||||
/* Disable interrupts (should already be disabled) and MMU here: */
|
||||
mfmsr 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME|PSL_RI|PSL_DR|PSL_IR)@l
|
||||
mtmsr 3
|
||||
isync
|
||||
/* restore possibly overwritten registers: */
|
||||
lwz 12,44(1)
|
||||
lwz 11,48(1)
|
||||
lwz 10,52(1)
|
||||
lwz 9,56(1)
|
||||
lwz 8,60(1)
|
||||
lwz 7,64(1)
|
||||
lwz 6,8(1)
|
||||
lwz 5,12(1)
|
||||
lwz 4,28(1)
|
||||
lwz 3,32(1)
|
||||
mtsrr1 6
|
||||
mtsrr0 5
|
||||
mtctr 4
|
||||
mtxer 3
|
||||
/* Returning to user mode? */
|
||||
mtcr 6 /* saved SRR1 */
|
||||
bc 4,17,1f /* branch if PSL_PR is false */
|
||||
#if defined(MULTIPROCESSOR)
|
||||
GET_CPUINFO(3)
|
||||
lwz 3,CI_CURPM(3)
|
||||
#else
|
||||
lis 3,_C_LABEL(curpm)@ha /* get current pmap real address */
|
||||
lwz 3,_C_LABEL(curpm)@l(3)
|
||||
#endif
|
||||
lwz 3,PM_KERNELSR(3)
|
||||
mtsr KERNEL_SR,3 /* Restore kernel SR */
|
||||
lis 3,_C_LABEL(astpending)@ha /* Test AST pending */
|
||||
lwz 4,_C_LABEL(astpending)@l(3)
|
||||
andi. 4,4,1
|
||||
beq 1f
|
||||
/* Setup for entry to realtrap: */
|
||||
lwz 3,0(1) /* get saved SP */
|
||||
mtsprg 1,3
|
||||
li 6,EXC_AST
|
||||
stmw 28,tempsave(0) /* establish tempsave again */
|
||||
mtlr 6
|
||||
lwz 28,40(1) /* saved LR */
|
||||
lwz 29,36(1) /* saved CR */
|
||||
lwz 6,68(1)
|
||||
lwz 5,72(1)
|
||||
lwz 4,76(1)
|
||||
lwz 3,80(1)
|
||||
lwz 0,84(1)
|
||||
lis 30,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
|
||||
lwz 31,_C_LABEL(intr_depth)@l(30)
|
||||
addi 31,31,-1
|
||||
stw 31,_C_LABEL(intr_depth)@l(30)
|
||||
b realtrap
|
||||
1:
|
||||
/* Here is the normal exit of extintr: */
|
||||
lwz 5,36(1)
|
||||
lwz 6,40(1)
|
||||
mtcr 5
|
||||
mtlr 6
|
||||
lwz 6,68(1)
|
||||
lwz 5,72(1)
|
||||
lis 3,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
|
||||
lwz 4,_C_LABEL(intr_depth)@l(3)
|
||||
addi 4,4,-1
|
||||
stw 4,_C_LABEL(intr_depth)@l(3)
|
||||
lwz 4,76(1)
|
||||
lwz 3,80(1)
|
||||
lwz 0,84(1)
|
||||
lwz 1,0(1)
|
||||
rfi
|
||||
|
||||
/*
|
||||
* Decrementer interrupt second level handler
|
||||
*/
|
||||
decrintr:
|
||||
INTRENTER
|
||||
addi 3,1,8 /* intr frame */
|
||||
bl _C_LABEL(decr_intr)
|
||||
b intr_exit
|
||||
|
||||
#ifdef DDB
|
||||
/*
|
||||
* Deliberate entry to ddbtrap
|
||||
*/
|
||||
.globl _C_LABEL(ddb_trap)
|
||||
_C_LABEL(ddb_trap):
|
||||
mtsprg 1,1
|
||||
mfmsr 3
|
||||
mtsrr1 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME)@l
|
||||
mtmsr 3 /* disable interrupts */
|
||||
isync
|
||||
stmw 28,ddbsave(0)
|
||||
mflr 28
|
||||
li 29,EXC_BPT
|
||||
mtlr 29
|
||||
mfcr 29
|
||||
mtsrr0 28
|
||||
|
||||
/*
|
||||
* Now the ddb trap catching code.
|
||||
*/
|
||||
ddbtrap:
|
||||
FRAME_SETUP(ddbsave)
|
||||
/* Call C trap code: */
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(ddb_trap_glue)
|
||||
or. 3,3,3
|
||||
bne ddbleave
|
||||
/* This wasn't for DDB, so switch to real trap: */
|
||||
lwz 3,FRAME_EXC+8(1) /* save exception */
|
||||
stw 3,ddbsave+8(0)
|
||||
FRAME_LEAVE(ddbsave)
|
||||
mtsprg 1,1 /* prepare for entrance to realtrap */
|
||||
stmw 28,tempsave(0)
|
||||
mflr 28
|
||||
mfcr 29
|
||||
lwz 31,ddbsave+8(0)
|
||||
mtlr 31
|
||||
b realtrap
|
||||
ddbleave:
|
||||
FRAME_LEAVE(ddbsave)
|
||||
rfi
|
||||
#endif /* DDB */
|
||||
|
||||
#ifdef IPKDB
|
||||
/*
|
||||
* Deliberate entry to ipkdbtrap
|
||||
*/
|
||||
.globl _C_LABEL(ipkdb_trap)
|
||||
_C_LABEL(ipkdb_trap):
|
||||
mtsprg 1,1
|
||||
mfmsr 3
|
||||
mtsrr1 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME)@l
|
||||
mtmsr 3 /* disable interrupts */
|
||||
isync
|
||||
stmw 28,ipkdbsave(0)
|
||||
mflr 28
|
||||
li 29,EXC_BPT
|
||||
mtlr 29
|
||||
mfcr 29
|
||||
mtsrr0 28
|
||||
|
||||
/*
|
||||
* Now the ipkdb trap catching code.
|
||||
*/
|
||||
ipkdbtrap:
|
||||
FRAME_SETUP(ipkdbsave)
|
||||
/* Call C trap code: */
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(ipkdb_trap_glue)
|
||||
or. 3,3,3
|
||||
bne ipkdbleave
|
||||
/* This wasn't for IPKDB, so switch to real trap: */
|
||||
lwz 3,FRAME_EXC+8(1) /* save exception */
|
||||
stw 3,ipkdbsave+8(0)
|
||||
FRAME_LEAVE(ipkdbsave)
|
||||
mtsprg 1,1 /* prepare for entrance to realtrap */
|
||||
stmw 28,tempsave(0)
|
||||
mflr 28
|
||||
mfcr 29
|
||||
lwz 31,ipkdbsave+8(0)
|
||||
mtlr 31
|
||||
b realtrap
|
||||
ipkdbleave:
|
||||
FRAME_LEAVE(ipkdbsave)
|
||||
rfi
|
||||
|
||||
ipkdbfault:
|
||||
ba _ipkdbfault
|
||||
_ipkdbfault:
|
||||
mfsrr0 3
|
||||
addi 3,3,4
|
||||
mtsrr0 3
|
||||
li 3,-1
|
||||
rfi
|
||||
|
||||
/*
|
||||
* int ipkdbfbyte(unsigned char *p)
|
||||
*/
|
||||
.globl _C_LABEL(ipkdbfbyte)
|
||||
_C_LABEL(ipkdbfbyte):
|
||||
li 9,EXC_DSI /* establish new fault routine */
|
||||
lwz 5,0(9)
|
||||
lis 6,ipkdbfault@ha
|
||||
lwz 6,ipkdbfault@l(6)
|
||||
stw 6,0(9)
|
||||
#ifdef IPKDBUSERHACK
|
||||
lis 8,_C_LABEL(ipkdbsr)@ha
|
||||
lwz 8,_C_LABEL(ipkdbsr)@l(8)
|
||||
mtsr USER_SR,8
|
||||
isync
|
||||
#endif
|
||||
dcbst 0,9 /* flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
lbz 3,0(3) /* fetch data */
|
||||
stw 5,0(9) /* restore previous fault handler */
|
||||
dcbst 0,9 /* and flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
blr
|
||||
|
||||
/*
|
||||
* int ipkdbsbyte(unsigned char *p, int c)
|
||||
*/
|
||||
.globl _C_LABEL(ipkdbsbyte)
|
||||
_C_LABEL(ipkdbsbyte):
|
||||
li 9,EXC_DSI /* establish new fault routine */
|
||||
lwz 5,0(9)
|
||||
lis 6,ipkdbfault@ha
|
||||
lwz 6,ipkdbfault@l(6)
|
||||
stw 6,0(9)
|
||||
#ifdef IPKDBUSERHACK
|
||||
lis 8,_C_LABEL(ipkdbsr)@ha
|
||||
lwz 8,_C_LABEL(ipkdbsr)@l(8)
|
||||
mtsr USER_SR,8
|
||||
isync
|
||||
#endif
|
||||
dcbst 0,9 /* flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
mr 6,3
|
||||
xor 3,3,3
|
||||
stb 4,0(6)
|
||||
dcbst 0,6 /* Now do appropriate flushes
|
||||
to data... */
|
||||
sync
|
||||
icbi 0,6 /* and instruction caches */
|
||||
stw 5,0(9) /* restore previous fault handler */
|
||||
dcbst 0,9 /* and flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
blr
|
||||
#endif /* IPKDB */
|
||||
|
||||
/*
|
||||
* int setfault()
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: locore.S,v 1.19 2000/08/21 18:46:03 tsubai Exp $ */
|
||||
/* $NetBSD: locore.S,v 1.20 2000/11/16 05:34:04 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
|
||||
|
|
@ -460,573 +460,6 @@ switch_return:
|
|||
mtlr 0
|
||||
blr
|
||||
|
||||
|
||||
/*
|
||||
* Data used during primary/secondary traps/interrupts
|
||||
*/
|
||||
#define tempsave 0x2e0 /* primary save area for trap handling */
|
||||
#define disisave 0x3e0 /* primary save area for dsi/isi traps */
|
||||
|
||||
#define INTSTK (8*1024) /* 8K interrupt stack */
|
||||
.data
|
||||
.align 4
|
||||
intstk:
|
||||
.space INTSTK /* interrupt stack */
|
||||
|
||||
GLOBAL(intr_depth)
|
||||
.long -1 /* in-use marker */
|
||||
|
||||
#define SPILLSTK 1024 /* 1K spill stack */
|
||||
|
||||
.comm spillstk,SPILLSTK,8
|
||||
|
||||
/*
|
||||
* This code gets copied to all the trap vectors
|
||||
* (except ISI/DSI, ALI, the interrupts, and possibly the debugging
|
||||
* traps when using IPKDB).
|
||||
*/
|
||||
.text
|
||||
.globl _C_LABEL(trapcode),_C_LABEL(trapsize)
|
||||
_C_LABEL(trapcode):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
/* Test whether we already had PR set */
|
||||
mfsrr1 31
|
||||
mtcr 31
|
||||
bc 4,17,1f /* branch if PSL_PR is clear */
|
||||
lis 1,_C_LABEL(curpcb)@ha
|
||||
lwz 1,_C_LABEL(curpcb)@l(1)
|
||||
addi 1,1,USPACE /* stack is top of user struct */
|
||||
1:
|
||||
bla s_trap
|
||||
_C_LABEL(trapsize) = .-_C_LABEL(trapcode)
|
||||
|
||||
/*
|
||||
* For ALI: has to save DSISR and DAR
|
||||
*/
|
||||
.globl _C_LABEL(alitrap),_C_LABEL(alisize)
|
||||
_C_LABEL(alitrap):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mfdar 30
|
||||
mfdsisr 31
|
||||
stmw 30,tempsave+16(0)
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
/* Test whether we already had PR set */
|
||||
mfsrr1 31
|
||||
mtcr 31
|
||||
bc 4,17,1f /* branch if PSL_PR is clear */
|
||||
lis 1,_C_LABEL(curpcb)@ha
|
||||
lwz 1,_C_LABEL(curpcb)@l(1)
|
||||
addi 1,1,USPACE /* stack is top of user struct */
|
||||
1:
|
||||
bla s_trap
|
||||
_C_LABEL(alisize) = .-_C_LABEL(alitrap)
|
||||
|
||||
/*
|
||||
* Similar to the above for DSI
|
||||
* Has to handle BAT spills
|
||||
* and standard pagetable spills
|
||||
*/
|
||||
.globl _C_LABEL(dsitrap),_C_LABEL(dsisize)
|
||||
_C_LABEL(dsitrap):
|
||||
stmw 28,disisave(0) /* free r28-r31 */
|
||||
mfcr 29 /* save CR */
|
||||
mfxer 30 /* save XER */
|
||||
mtsprg 2,30 /* in SPRG2 */
|
||||
mfsrr1 31 /* test kernel mode */
|
||||
mtcr 31
|
||||
bc 12,17,1f /* branch if PSL_PR is set */
|
||||
mfdar 31 /* get fault address */
|
||||
rlwinm 31,31,7,25,28 /* get segment * 8 */
|
||||
|
||||
/* get batu */
|
||||
addis 31,31,_C_LABEL(battable)@ha
|
||||
lwz 30,_C_LABEL(battable)@l(31)
|
||||
mtcr 30
|
||||
bc 4,30,1f /* branch if supervisor valid is
|
||||
false */
|
||||
/* get batl */
|
||||
lwz 31,_C_LABEL(battable)+4@l(31)
|
||||
/* We randomly use the highest two bat registers here */
|
||||
mftb 28
|
||||
andi. 28,28,1
|
||||
bne 2f
|
||||
mtdbatu 2,30
|
||||
mtdbatl 2,31
|
||||
b 3f
|
||||
2:
|
||||
mtdbatu 3,30
|
||||
mtdbatl 3,31
|
||||
3:
|
||||
mfsprg 30,2 /* restore XER */
|
||||
mtxer 30
|
||||
mtcr 29 /* restore CR */
|
||||
lmw 28,disisave(0) /* restore r28-r31 */
|
||||
rfi /* return to trapped code */
|
||||
1:
|
||||
mflr 28 /* save LR */
|
||||
bla s_dsitrap
|
||||
_C_LABEL(dsisize) = .-_C_LABEL(dsitrap)
|
||||
|
||||
/*
|
||||
* Similar to the above for ISI
|
||||
*/
|
||||
.globl _C_LABEL(isitrap),_C_LABEL(isisize)
|
||||
_C_LABEL(isitrap):
|
||||
stmw 28,disisave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
mfsrr1 31 /* test kernel mode */
|
||||
mtcr 31
|
||||
bc 12,17,1f /* branch if PSL_PR is set */
|
||||
mfsrr0 31 /* get fault address */
|
||||
rlwinm 31,31,7,25,28 /* get segment * 8 */
|
||||
|
||||
/* get batu */
|
||||
addis 31,31,_C_LABEL(battable)@ha
|
||||
lwz 30,_C_LABEL(battable)@l(31)
|
||||
mtcr 30
|
||||
bc 4,30,1f /* branch if supervisor valid is
|
||||
false */
|
||||
mtibatu 3,30
|
||||
|
||||
/* get batl */
|
||||
lwz 30,_C_LABEL(battable)+4@l(31)
|
||||
mtibatl 3,30
|
||||
|
||||
mtcr 29 /* restore CR */
|
||||
lmw 28,disisave(0) /* restore r28-r31 */
|
||||
rfi /* return to trapped code */
|
||||
1:
|
||||
bla s_isitrap
|
||||
_C_LABEL(isisize)= .-_C_LABEL(isitrap)
|
||||
|
||||
/*
|
||||
* This one for the external interrupt handler.
|
||||
*/
|
||||
.globl _C_LABEL(extint),_C_LABEL(extsize)
|
||||
_C_LABEL(extint):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
mfxer 30 /* save XER */
|
||||
lis 1,intstk+INTSTK@ha /* get interrupt stack */
|
||||
addi 1,1,intstk+INTSTK@l
|
||||
lwz 31,0(1) /* were we already running on intstk? */
|
||||
addic. 31,31,1
|
||||
stw 31,0(1)
|
||||
beq 1f
|
||||
mfsprg 1,1 /* yes, get old SP */
|
||||
1:
|
||||
ba extintr
|
||||
_C_LABEL(extsize) = .-_C_LABEL(extint)
|
||||
|
||||
/*
|
||||
* And this one for the decrementer interrupt handler.
|
||||
*/
|
||||
.globl _C_LABEL(decrint),_C_LABEL(decrsize)
|
||||
_C_LABEL(decrint):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
mfxer 30 /* save XER */
|
||||
lis 1,intstk+INTSTK@ha /* get interrupt stack */
|
||||
addi 1,1,intstk+INTSTK@l
|
||||
lwz 31,0(1) /* were we already running on intstk? */
|
||||
addic. 31,31,1
|
||||
stw 31,0(1)
|
||||
beq 1f
|
||||
mfsprg 1,1 /* yes, get old SP */
|
||||
1:
|
||||
ba decrintr
|
||||
_C_LABEL(decrsize) = .-_C_LABEL(decrint)
|
||||
|
||||
/*
|
||||
* Now the tlb software load for 603 processors:
|
||||
* (Code essentially from the 603e User Manual, Chapter 5, but
|
||||
* corrected a lot.)
|
||||
*/
|
||||
#define DMISS 976
|
||||
#define DCMP 977
|
||||
#define HASH1 978
|
||||
#define HASH2 979
|
||||
#define IMISS 980
|
||||
#define ICMP 981
|
||||
#define RPA 982
|
||||
|
||||
.globl _C_LABEL(tlbimiss),_C_LABEL(tlbimsize)
|
||||
_C_LABEL(tlbimiss):
|
||||
mfspr 2,HASH1 /* get first pointer */
|
||||
li 1,8
|
||||
mfctr 0 /* save counter */
|
||||
mfspr 3,ICMP /* get first compare value */
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
1:
|
||||
mtctr 1 /* load counter */
|
||||
2:
|
||||
lwzu 1,8(2) /* get next pte */
|
||||
cmpl 0,1,3 /* see if found pte */
|
||||
bdneq 2b /* loop if not eq */
|
||||
bne 3f /* not found */
|
||||
lwz 1,4(2) /* load tlb entry lower word */
|
||||
andi. 3,1,8 /* check G-bit */
|
||||
bne 4f /* if guarded, take ISI */
|
||||
mtctr 0 /* restore counter */
|
||||
mfspr 0,IMISS /* get the miss address for the tlbli */
|
||||
mfsrr1 3 /* get the saved cr0 bits */
|
||||
mtcrf 0x80,3 /* and restore */
|
||||
ori 1,1,0x100 /* set the reference bit */
|
||||
mtspr RPA,1 /* set the pte */
|
||||
srwi 1,1,8 /* get byte 7 of pte */
|
||||
tlbli 0 /* load the itlb */
|
||||
stb 1,6(2) /* update page table */
|
||||
rfi
|
||||
|
||||
3: /* not found in pteg */
|
||||
andi. 1,3,0x40 /* have we already done second hash? */
|
||||
bne 5f
|
||||
mfspr 2,HASH2 /* get the second pointer */
|
||||
ori 3,3,0x40 /* change the compare value */
|
||||
li 1,8
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
b 1b
|
||||
4: /* guarded */
|
||||
mfsrr1 3
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
oris 2,2,0x8000000@h /* set srr<4> to flag prot violation */
|
||||
b 6f
|
||||
5: /* not found anywhere */
|
||||
mfsrr1 3
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
oris 2,2,0x40000000@h /* set srr1<1> to flag pte not found */
|
||||
6:
|
||||
mtctr 0 /* restore counter */
|
||||
mtsrr1 2
|
||||
mfmsr 0
|
||||
xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
|
||||
mtcrf 0x80,3 /* restore cr0 */
|
||||
mtmsr 0 /* now with native gprs */
|
||||
isync
|
||||
ba EXC_ISI
|
||||
_C_LABEL(tlbimsize) = .-_C_LABEL(tlbimiss)
|
||||
|
||||
.globl _C_LABEL(tlbdlmiss),_C_LABEL(tlbdlmsize)
|
||||
_C_LABEL(tlbdlmiss):
|
||||
mfspr 2,HASH1 /* get first pointer */
|
||||
li 1,8
|
||||
mfctr 0 /* save counter */
|
||||
mfspr 3,DCMP /* get first compare value */
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
1:
|
||||
mtctr 1 /* load counter */
|
||||
2:
|
||||
lwzu 1,8(2) /* get next pte */
|
||||
cmpl 0,1,3 /* see if found pte */
|
||||
bdneq 2b /* loop if not eq */
|
||||
bne 3f /* not found */
|
||||
lwz 1,4(2) /* load tlb entry lower word */
|
||||
mtctr 0 /* restore counter */
|
||||
mfspr 0,DMISS /* get the miss address for the tlbld */
|
||||
mfsrr1 3 /* get the saved cr0 bits */
|
||||
mtcrf 0x80,3 /* and restore */
|
||||
ori 1,1,0x100 /* set the reference bit */
|
||||
mtspr RPA,1 /* set the pte */
|
||||
srwi 1,1,8 /* get byte 7 of pte */
|
||||
tlbld 0 /* load the dtlb */
|
||||
stb 1,6(2) /* update page table */
|
||||
rfi
|
||||
|
||||
3: /* not found in pteg */
|
||||
andi. 1,3,0x40 /* have we already done second hash? */
|
||||
bne 5f
|
||||
mfspr 2,HASH2 /* get the second pointer */
|
||||
ori 3,3,0x40 /* change the compare value */
|
||||
li 1,8
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
b 1b
|
||||
5: /* not found anywhere */
|
||||
mfsrr1 3
|
||||
lis 1,0x40000000@h /* set dsisr<1> to flag pte not found */
|
||||
mtctr 0 /* restore counter */
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
mtsrr1 2
|
||||
mtdsisr 1 /* load the dsisr */
|
||||
mfspr 1,DMISS /* get the miss address */
|
||||
mtdar 1 /* put in dar */
|
||||
mfmsr 0
|
||||
xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
|
||||
mtcrf 0x80,3 /* restore cr0 */
|
||||
mtmsr 0 /* now with native gprs */
|
||||
isync
|
||||
ba EXC_DSI
|
||||
_C_LABEL(tlbdlmsize) = .-_C_LABEL(tlbdlmiss)
|
||||
|
||||
.globl _C_LABEL(tlbdsmiss),_C_LABEL(tlbdsmsize)
|
||||
_C_LABEL(tlbdsmiss):
|
||||
mfspr 2,HASH1 /* get first pointer */
|
||||
li 1,8
|
||||
mfctr 0 /* save counter */
|
||||
mfspr 3,DCMP /* get first compare value */
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
1:
|
||||
mtctr 1 /* load counter */
|
||||
2:
|
||||
lwzu 1,8(2) /* get next pte */
|
||||
cmpl 0,1,3 /* see if found pte */
|
||||
bdneq 2b /* loop if not eq */
|
||||
bne 3f /* not found */
|
||||
lwz 1,4(2) /* load tlb entry lower word */
|
||||
andi. 3,1,0x80 /* check the C-bit */
|
||||
beq 4f
|
||||
5:
|
||||
mtctr 0 /* restore counter */
|
||||
mfspr 0,DMISS /* get the miss address for the tlbld */
|
||||
mfsrr1 3 /* get the saved cr0 bits */
|
||||
mtcrf 0x80,3 /* and restore */
|
||||
mtspr RPA,1 /* set the pte */
|
||||
tlbld 0 /* load the dtlb */
|
||||
rfi
|
||||
|
||||
3: /* not found in pteg */
|
||||
andi. 1,3,0x40 /* have we already done second hash? */
|
||||
bne 5f
|
||||
mfspr 2,HASH2 /* get the second pointer */
|
||||
ori 3,3,0x40 /* change the compare value */
|
||||
li 1,8
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
b 1b
|
||||
4: /* found, but C-bit = 0 */
|
||||
rlwinm. 3,1,30,0,1 /* test PP */
|
||||
bge- 7f
|
||||
andi. 3,1,1
|
||||
beq+ 8f
|
||||
9: /* found, but protection violation (PP==00)*/
|
||||
mfsrr1 3
|
||||
lis 1,0xa000000@h /* indicate protection violation
|
||||
on store */
|
||||
b 1f
|
||||
7: /* found, PP=1x */
|
||||
mfspr 3,DMISS /* get the miss address */
|
||||
mfsrin 1,3 /* get the segment register */
|
||||
mfsrr1 3
|
||||
rlwinm 3,3,18,31,31 /* get PR-bit */
|
||||
rlwnm. 2,2,3,1,1 /* get the key */
|
||||
bne- 9b /* protection violation */
|
||||
8: /* found, set reference/change bits */
|
||||
lwz 1,4(2) /* reload tlb entry */
|
||||
ori 1,1,0x180
|
||||
sth 1,6(2)
|
||||
b 5b
|
||||
5: /* not found anywhere */
|
||||
mfsrr1 3
|
||||
lis 1,0x42000000@h /* set dsisr<1> to flag pte not found */
|
||||
/* dsisr<6> to flag store */
|
||||
1:
|
||||
mtctr 0 /* restore counter */
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
mtsrr1 2
|
||||
mtdsisr 1 /* load the dsisr */
|
||||
mfspr 1,DMISS /* get the miss address */
|
||||
mtdar 1 /* put in dar */
|
||||
mfmsr 0
|
||||
xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
|
||||
mtcrf 0x80,3 /* restore cr0 */
|
||||
mtmsr 0 /* now with native gprs */
|
||||
isync
|
||||
ba EXC_DSI
|
||||
_C_LABEL(tlbdsmsize) = .-_C_LABEL(tlbdsmiss)
|
||||
|
||||
#ifdef DDB
|
||||
#define ddbsave 0xde0 /* primary save area for DDB */
|
||||
/*
|
||||
* In case of DDB we want a separate trap catcher for it
|
||||
*/
|
||||
.local ddbstk
|
||||
.comm ddbstk,INTSTK,8 /* ddb stack */
|
||||
|
||||
.globl _C_LABEL(ddblow),_C_LABEL(ddbsize)
|
||||
_C_LABEL(ddblow):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,ddbsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
lis 1,ddbstk+INTSTK@ha /* get new SP */
|
||||
addi 1,1,ddbstk+INTSTK@l
|
||||
bla ddbtrap
|
||||
_C_LABEL(ddbsize) = .-_C_LABEL(ddblow)
|
||||
#endif /* DDB */
|
||||
|
||||
#ifdef IPKDB
|
||||
#define ipkdbsave 0xde0 /* primary save area for IPKDB */
|
||||
/*
|
||||
* In case of IPKDB we want a separate trap catcher for it
|
||||
*/
|
||||
|
||||
.local ipkdbstk
|
||||
.comm ipkdbstk,INTSTK,8 /* ipkdb stack */
|
||||
|
||||
.globl _C_LABEL(ipkdblow),_C_LABEL(ipkdbsize)
|
||||
_C_LABEL(ipkdblow):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,ipkdbsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
lis 1,ipkdbstk+INTSTK@ha /* get new SP */
|
||||
addi 1,1,ipkdbstk+INTSTK@l
|
||||
bla ipkdbtrap
|
||||
_C_LABEL(ipkdbsize) = .-_C_LABEL(ipkdblow)
|
||||
#endif /* IPKDB */
|
||||
|
||||
/*
|
||||
* FRAME_SETUP assumes:
|
||||
* SPRG1 SP (1)
|
||||
* savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
|
||||
* 28 LR
|
||||
* 29 CR
|
||||
* 1 kernel stack
|
||||
* LR trap type
|
||||
* SRR0/1 as at start of trap
|
||||
*/
|
||||
#define FRAME_SETUP(savearea) \
|
||||
/* Have to enable translation to allow access of kernel stack: */ \
|
||||
mfsrr0 30; \
|
||||
mfsrr1 31; \
|
||||
stmw 30,savearea+24(0); \
|
||||
mfmsr 30; \
|
||||
ori 30,30,(PSL_DR|PSL_IR); \
|
||||
mtmsr 30; \
|
||||
isync; \
|
||||
mfsprg 31,1; \
|
||||
stwu 31,-FRAMELEN(1); \
|
||||
stw 0,FRAME_0+8(1); \
|
||||
stw 31,FRAME_1+8(1); \
|
||||
stw 28,FRAME_LR+8(1); \
|
||||
stw 29,FRAME_CR+8(1); \
|
||||
lmw 28,savearea(0); \
|
||||
stmw 2,FRAME_2+8(1); \
|
||||
lmw 28,savearea+16(0); \
|
||||
mfxer 3; \
|
||||
mfctr 4; \
|
||||
mflr 5; \
|
||||
andi. 5,5,0xff00; \
|
||||
stw 3,FRAME_XER+8(1); \
|
||||
stw 4,FRAME_CTR+8(1); \
|
||||
stw 5,FRAME_EXC+8(1); \
|
||||
stw 28,FRAME_DAR+8(1); \
|
||||
stw 29,FRAME_DSISR+8(1); \
|
||||
stw 30,FRAME_SRR0+8(1); \
|
||||
stw 31,FRAME_SRR1+8(1)
|
||||
|
||||
#define FRAME_LEAVE(savearea) \
|
||||
/* Now restore regs: */ \
|
||||
lwz 2,FRAME_SRR0+8(1); \
|
||||
lwz 3,FRAME_SRR1+8(1); \
|
||||
lwz 4,FRAME_CTR+8(1); \
|
||||
lwz 5,FRAME_XER+8(1); \
|
||||
lwz 6,FRAME_LR+8(1); \
|
||||
lwz 7,FRAME_CR+8(1); \
|
||||
stw 2,savearea(0); \
|
||||
stw 3,savearea+4(0); \
|
||||
mtctr 4; \
|
||||
mtxer 5; \
|
||||
mtlr 6; \
|
||||
mtsprg 1,7; /* save cr */ \
|
||||
lmw 2,FRAME_2+8(1); \
|
||||
lwz 0,FRAME_0+8(1); \
|
||||
lwz 1,FRAME_1+8(1); \
|
||||
mtsprg 2,2; /* save r2 & r3 */ \
|
||||
mtsprg 3,3; \
|
||||
/* Disable translation, machine check and recoverability: */ \
|
||||
mfmsr 2; \
|
||||
andi. 2,2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
|
||||
mtmsr 2; \
|
||||
isync; \
|
||||
/* Decide whether we return to user mode: */ \
|
||||
lwz 3,savearea+4(0); \
|
||||
mtcr 3; \
|
||||
bc 4,17,1f; /* branch if PSL_PR is false */ \
|
||||
/* Restore user & kernel access SR: */ \
|
||||
lis 2,_C_LABEL(curpm)@ha; /* get real address of pmap */ \
|
||||
lwz 2,_C_LABEL(curpm)@l(2); \
|
||||
lwz 3,PM_USRSR(2); \
|
||||
mtsr USER_SR,3; \
|
||||
lwz 3,PM_KERNELSR(2); \
|
||||
mtsr KERNEL_SR,3; \
|
||||
1: mfsprg 2,1; /* restore cr */ \
|
||||
mtcr 2; \
|
||||
lwz 2,savearea(0); \
|
||||
lwz 3,savearea+4(0); \
|
||||
mtsrr0 2; \
|
||||
mtsrr1 3; \
|
||||
mfsprg 2,2; /* restore r2 & r3 */ \
|
||||
mfsprg 3,3
|
||||
|
||||
/*
|
||||
* Preamble code for DSI/ISI traps
|
||||
*/
|
||||
disitrap:
|
||||
lmw 30,disisave(0)
|
||||
stmw 30,tempsave(0)
|
||||
lmw 30,disisave+8(0)
|
||||
stmw 30,tempsave+8(0)
|
||||
mfdar 30
|
||||
mfdsisr 31
|
||||
stmw 30,tempsave+16(0)
|
||||
realtrap:
|
||||
/* Test whether we already had PR set */
|
||||
mfsrr1 1
|
||||
mtcr 1
|
||||
mfsprg 1,1 /* restore SP (might have been
|
||||
overwritten) */
|
||||
bc 4,17,s_trap /* branch if PSL_PR is false */
|
||||
lis 1,_C_LABEL(curpcb)@ha
|
||||
lwz 1,_C_LABEL(curpcb)@l(1)
|
||||
addi 1,1,USPACE /* stack is top of user struct */
|
||||
|
||||
/*
|
||||
* Now the common trap catching code.
|
||||
*/
|
||||
s_trap:
|
||||
/* First have to enable KERNEL mapping */
|
||||
lis 31,KERNEL_SEGMENT@h
|
||||
ori 31,31,KERNEL_SEGMENT@l
|
||||
mtsr KERNEL_SR,31
|
||||
FRAME_SETUP(tempsave)
|
||||
/* Now we can recover interrupts again: */
|
||||
mfmsr 7
|
||||
ori 7,7,(PSL_EE|PSL_ME|PSL_RI)@l
|
||||
mtmsr 7
|
||||
isync
|
||||
/* Call C trap code: */
|
||||
trapagain:
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(trap)
|
||||
trapexit:
|
||||
/* Disable interrupts: */
|
||||
mfmsr 3
|
||||
andi. 3,3,~PSL_EE@l
|
||||
mtmsr 3
|
||||
/* Test AST pending: */
|
||||
lwz 5,FRAME_SRR1+8(1)
|
||||
mtcr 5
|
||||
bc 4,17,1f /* branch if PSL_PR is false */
|
||||
lis 3,_C_LABEL(astpending)@ha
|
||||
lwz 4,_C_LABEL(astpending)@l(3)
|
||||
andi. 4,4,1
|
||||
beq 1f
|
||||
li 6,EXC_AST
|
||||
stw 6,FRAME_EXC+8(1)
|
||||
b trapagain
|
||||
1:
|
||||
FRAME_LEAVE(tempsave)
|
||||
rfi
|
||||
|
||||
/*
|
||||
* Child comes here at the end of a fork.
|
||||
* Mostly similar to the above.
|
||||
|
|
@ -1044,367 +477,10 @@ _C_LABEL(fork_trampoline):
|
|||
b trapexit
|
||||
|
||||
/*
|
||||
* DSI second stage fault handler
|
||||
* Pull in common trap vector code.
|
||||
*/
|
||||
s_dsitrap:
|
||||
mfdsisr 31 /* test whether this may be a
|
||||
spill fault */
|
||||
mtcr 31
|
||||
mtsprg 1,1 /* save SP */
|
||||
bc 4,1,disitrap /* branch if table miss is false */
|
||||
lis 1,spillstk+SPILLSTK@ha
|
||||
addi 1,1,spillstk+SPILLSTK@l /* get spill stack */
|
||||
stwu 1,-52(1)
|
||||
stw 0,48(1) /* save non-volatile registers */
|
||||
stw 3,44(1)
|
||||
stw 4,40(1)
|
||||
stw 5,36(1)
|
||||
stw 6,32(1)
|
||||
stw 7,28(1)
|
||||
stw 8,24(1)
|
||||
stw 9,20(1)
|
||||
stw 10,16(1)
|
||||
stw 11,12(1)
|
||||
stw 12,8(1)
|
||||
mflr 30 /* save trap type */
|
||||
mfctr 31 /* & CTR */
|
||||
mfdar 3
|
||||
s_pte_spill:
|
||||
bl _C_LABEL(pte_spill) /* try a spill */
|
||||
or. 3,3,3
|
||||
mtctr 31 /* restore CTR */
|
||||
mtlr 30 /* and trap type */
|
||||
mfsprg 31,2 /* get saved XER */
|
||||
mtxer 31 /* restore XER */
|
||||
lwz 12,8(1) /* restore non-volatile registers */
|
||||
lwz 11,12(1)
|
||||
lwz 10,16(1)
|
||||
lwz 9,20(1)
|
||||
lwz 8,24(1)
|
||||
lwz 7,28(1)
|
||||
lwz 6,32(1)
|
||||
lwz 5,36(1)
|
||||
lwz 4,40(1)
|
||||
lwz 3,44(1)
|
||||
lwz 0,48(1)
|
||||
beq disitrap
|
||||
mfsprg 1,1 /* restore SP */
|
||||
mtcr 29 /* restore CR */
|
||||
mtlr 28 /* restore LR */
|
||||
lmw 28,disisave(0) /* restore r28-r31 */
|
||||
rfi /* return to trapped code */
|
||||
#include <powerpc/powerpc/trap_subr.S>
|
||||
|
||||
/*
|
||||
* ISI second stage fault handler
|
||||
*/
|
||||
s_isitrap:
|
||||
mfsrr1 31 /* test whether this may be a
|
||||
spill fault */
|
||||
mtcr 31
|
||||
mtsprg 1,1 /* save SP */
|
||||
bc 4,1,disitrap /* branch if table miss is false */
|
||||
lis 1,spillstk+SPILLSTK@ha
|
||||
addi 1,1,spillstk+SPILLSTK@l /* get spill stack */
|
||||
stwu 1,-52(1)
|
||||
stw 0,48(1) /* save non-volatile registers */
|
||||
stw 3,44(1)
|
||||
stw 4,40(1)
|
||||
stw 5,36(1)
|
||||
stw 6,32(1)
|
||||
stw 7,28(1)
|
||||
stw 8,24(1)
|
||||
stw 9,20(1)
|
||||
stw 10,16(1)
|
||||
stw 11,12(1)
|
||||
stw 12,8(1)
|
||||
mfxer 30 /* save XER */
|
||||
mtsprg 2,30
|
||||
mflr 30 /* save trap type */
|
||||
mfctr 31 /* & ctr */
|
||||
mfsrr0 3
|
||||
b s_pte_spill /* above */
|
||||
|
||||
/*
|
||||
* External interrupt second level handler
|
||||
*/
|
||||
#define INTRENTER \
|
||||
/* Save non-volatile registers: */ \
|
||||
stwu 1,-88(1); /* temporarily */ \
|
||||
stw 0,84(1); \
|
||||
mfsprg 0,1; /* get original SP */ \
|
||||
stw 0,0(1); /* and store it */ \
|
||||
stw 3,80(1); \
|
||||
stw 4,76(1); \
|
||||
stw 5,72(1); \
|
||||
stw 6,68(1); \
|
||||
stw 7,64(1); \
|
||||
stw 8,60(1); \
|
||||
stw 9,56(1); \
|
||||
stw 10,52(1); \
|
||||
stw 11,48(1); \
|
||||
stw 12,44(1); \
|
||||
stw 28,40(1); /* saved LR */ \
|
||||
stw 29,36(1); /* saved CR */ \
|
||||
stw 30,32(1); /* saved XER */ \
|
||||
lmw 28,tempsave(0); /* restore r28-r31 */ \
|
||||
mfctr 6; \
|
||||
lis 5,_C_LABEL(intr_depth)@ha; \
|
||||
lwz 5,_C_LABEL(intr_depth)@l(5); \
|
||||
mfsrr0 4; \
|
||||
mfsrr1 3; \
|
||||
stw 6,28(1); \
|
||||
stw 5,20(1); \
|
||||
stw 4,12(1); \
|
||||
stw 3,8(1); \
|
||||
/* interrupts are recoverable here, and enable translation */ \
|
||||
lis 3,(KERNEL_SEGMENT|SR_SUKEY|SR_PRKEY)@h; \
|
||||
ori 3,3,(KERNEL_SEGMENT|SR_SUKEY|SR_PRKEY)@l; \
|
||||
mtsr KERNEL_SR,3; \
|
||||
mfmsr 5; \
|
||||
ori 5,5,(PSL_IR|PSL_DR|PSL_RI); \
|
||||
mtmsr 5; \
|
||||
isync
|
||||
|
||||
.globl _C_LABEL(extint_call)
|
||||
extintr:
|
||||
INTRENTER
|
||||
_C_LABEL(extint_call):
|
||||
bl _C_LABEL(extint_call) /* to be filled in later */
|
||||
|
||||
intr_exit:
|
||||
/* Disable interrupts (should already be disabled) and MMU here: */
|
||||
mfmsr 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME|PSL_RI|PSL_DR|PSL_IR)@l
|
||||
mtmsr 3
|
||||
isync
|
||||
/* restore possibly overwritten registers: */
|
||||
lwz 12,44(1)
|
||||
lwz 11,48(1)
|
||||
lwz 10,52(1)
|
||||
lwz 9,56(1)
|
||||
lwz 8,60(1)
|
||||
lwz 7,64(1)
|
||||
lwz 6,8(1)
|
||||
lwz 5,12(1)
|
||||
lwz 4,28(1)
|
||||
lwz 3,32(1)
|
||||
mtsrr1 6
|
||||
mtsrr0 5
|
||||
mtctr 4
|
||||
mtxer 3
|
||||
/* Returning to user mode? */
|
||||
mtcr 6 /* saved SRR1 */
|
||||
bc 4,17,1f /* branch if PSL_PR is false */
|
||||
lis 3,_C_LABEL(curpm)@ha /* get current pmap real address */
|
||||
lwz 3,_C_LABEL(curpm)@l(3)
|
||||
lwz 3,PM_KERNELSR(3)
|
||||
mtsr KERNEL_SR,3 /* Restore kernel SR */
|
||||
lis 3,_C_LABEL(astpending)@ha /* Test AST pending */
|
||||
lwz 4,_C_LABEL(astpending)@l(3)
|
||||
andi. 4,4,1
|
||||
beq 1f
|
||||
/* Setup for entry to realtrap: */
|
||||
lwz 3,0(1) /* get saved SP */
|
||||
mtsprg 1,3
|
||||
li 6,EXC_AST
|
||||
stmw 28,tempsave(0) /* establish tempsave again */
|
||||
mtlr 6
|
||||
lwz 28,40(1) /* saved LR */
|
||||
lwz 29,36(1) /* saved CR */
|
||||
lwz 6,68(1)
|
||||
lwz 5,72(1)
|
||||
lwz 4,76(1)
|
||||
lwz 3,80(1)
|
||||
lwz 0,84(1)
|
||||
lis 30,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
|
||||
lwz 31,_C_LABEL(intr_depth)@l(30)
|
||||
addi 31,31,-1
|
||||
stw 31,_C_LABEL(intr_depth)@l(30)
|
||||
b realtrap
|
||||
1:
|
||||
/* Here is the normal exit of extintr: */
|
||||
lwz 5,36(1)
|
||||
lwz 6,40(1)
|
||||
mtcr 5
|
||||
mtlr 6
|
||||
lwz 6,68(1)
|
||||
lwz 5,72(1)
|
||||
lis 3,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
|
||||
lwz 4,_C_LABEL(intr_depth)@l(3)
|
||||
addi 4,4,-1
|
||||
stw 4,_C_LABEL(intr_depth)@l(3)
|
||||
lwz 4,76(1)
|
||||
lwz 3,80(1)
|
||||
lwz 0,84(1)
|
||||
lwz 1,0(1)
|
||||
rfi
|
||||
|
||||
/*
|
||||
* Decrementer interrupt second level handler
|
||||
*/
|
||||
decrintr:
|
||||
INTRENTER
|
||||
addi 3,1,8 /* intr frame */
|
||||
bl _C_LABEL(decr_intr)
|
||||
b intr_exit
|
||||
|
||||
#ifdef DDB
|
||||
/*
|
||||
* Deliberate entry to ddbtrap
|
||||
*/
|
||||
.globl _C_LABEL(ddb_trap)
|
||||
_C_LABEL(ddb_trap):
|
||||
mtsprg 1,1
|
||||
mfmsr 3
|
||||
mtsrr1 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME)@l
|
||||
mtmsr 3 /* disable interrupts */
|
||||
isync
|
||||
stmw 28,ddbsave(0)
|
||||
mflr 28
|
||||
li 29,EXC_BPT
|
||||
mtlr 29
|
||||
mfcr 29
|
||||
mtsrr0 28
|
||||
|
||||
/*
|
||||
* Now the ddb trap catching code.
|
||||
*/
|
||||
ddbtrap:
|
||||
FRAME_SETUP(ddbsave)
|
||||
/* Call C trap code: */
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(ddb_trap_glue)
|
||||
or. 3,3,3
|
||||
bne ddbleave
|
||||
/* This wasn't for DDB, so switch to real trap: */
|
||||
lwz 3,FRAME_EXC+8(1) /* save exception */
|
||||
stw 3,ddbsave+8(0)
|
||||
FRAME_LEAVE(ddbsave)
|
||||
mtsprg 1,1 /* prepare for entrance to realtrap */
|
||||
stmw 28,tempsave(0)
|
||||
mflr 28
|
||||
mfcr 29
|
||||
lwz 31,ddbsave+8(0)
|
||||
mtlr 31
|
||||
b realtrap
|
||||
ddbleave:
|
||||
FRAME_LEAVE(ddbsave)
|
||||
rfi
|
||||
#endif /* DDB */
|
||||
|
||||
#ifdef IPKDB
|
||||
/*
|
||||
* Deliberate entry to ipkdbtrap
|
||||
*/
|
||||
.globl _C_LABEL(ipkdb_trap)
|
||||
_C_LABEL(ipkdb_trap):
|
||||
mtsprg 1,1
|
||||
mfmsr 3
|
||||
mtsrr1 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME)@l
|
||||
mtmsr 3 /* disable interrupts */
|
||||
isync
|
||||
stmw 28,ipkdbsave(0)
|
||||
mflr 28
|
||||
li 29,EXC_BPT
|
||||
mtlr 29
|
||||
mfcr 29
|
||||
mtsrr0 28
|
||||
|
||||
/*
|
||||
* Now the ipkdb trap catching code.
|
||||
*/
|
||||
ipkdbtrap:
|
||||
FRAME_SETUP(ipkdbsave)
|
||||
/* Call C trap code: */
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(ipkdb_trap_glue)
|
||||
or. 3,3,3
|
||||
bne ipkdbleave
|
||||
/* This wasn't for IPKDB, so switch to real trap: */
|
||||
lwz 3,FRAME_EXC+8(1) /* save exception */
|
||||
stw 3,ipkdbsave+8(0)
|
||||
FRAME_LEAVE(ipkdbsave)
|
||||
mtsprg 1,1 /* prepare for entrance to realtrap */
|
||||
stmw 28,tempsave(0)
|
||||
mflr 28
|
||||
mfcr 29
|
||||
lwz 31,ipkdbsave+8(0)
|
||||
mtlr 31
|
||||
b realtrap
|
||||
ipkdbleave:
|
||||
FRAME_LEAVE(ipkdbsave)
|
||||
rfi
|
||||
|
||||
ipkdbfault:
|
||||
ba _ipkdbfault
|
||||
_ipkdbfault:
|
||||
mfsrr0 3
|
||||
addi 3,3,4
|
||||
mtsrr0 3
|
||||
li 3,-1
|
||||
rfi
|
||||
|
||||
/*
|
||||
* int ipkdbfbyte(unsigned char *p)
|
||||
*/
|
||||
.globl _C_LABEL(ipkdbfbyte)
|
||||
_C_LABEL(ipkdbfbyte):
|
||||
li 9,EXC_DSI /* establish new fault routine */
|
||||
lwz 5,0(9)
|
||||
lis 6,ipkdbfault@ha
|
||||
lwz 6,ipkdbfault@l(6)
|
||||
stw 6,0(9)
|
||||
#ifdef IPKDBUSERHACK
|
||||
lis 8,_C_LABEL(ipkdbsr)@ha
|
||||
lwz 8,_C_LABEL(ipkdbsr)@l(8)
|
||||
mtsr USER_SR,8
|
||||
isync
|
||||
#endif
|
||||
dcbst 0,9 /* flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
lbz 3,0(3) /* fetch data */
|
||||
stw 5,0(9) /* restore previous fault handler */
|
||||
dcbst 0,9 /* and flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
blr
|
||||
|
||||
/*
|
||||
* int ipkdbsbyte(unsigned char *p, int c)
|
||||
*/
|
||||
.globl _C_LABEL(ipkdbsbyte)
|
||||
_C_LABEL(ipkdbsbyte):
|
||||
li 9,EXC_DSI /* establish new fault routine */
|
||||
lwz 5,0(9)
|
||||
lis 6,ipkdbfault@ha
|
||||
lwz 6,ipkdbfault@l(6)
|
||||
stw 6,0(9)
|
||||
#ifdef IPKDBUSERHACK
|
||||
lis 8,_C_LABEL(ipkdbsr)@ha
|
||||
lwz 8,_C_LABEL(ipkdbsr)@l(8)
|
||||
mtsr USER_SR,8
|
||||
isync
|
||||
#endif
|
||||
dcbst 0,9 /* flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
mr 6,3
|
||||
xor 3,3,3
|
||||
stb 4,0(6)
|
||||
dcbst 0,6 /* Now do appropriate flushes
|
||||
to data... */
|
||||
sync
|
||||
icbi 0,6 /* and instruction caches */
|
||||
stw 5,0(9) /* restore previous fault handler */
|
||||
dcbst 0,9 /* and flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
blr
|
||||
#endif /* IPKDB */
|
||||
|
||||
/*
|
||||
* int setfault()
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: locore.s,v 1.7 2000/08/21 18:46:04 tsubai Exp $ */
|
||||
/* $NetBSD: locore.s,v 1.8 2000/11/16 05:38:33 thorpej Exp $ */
|
||||
/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -406,575 +406,9 @@ switch_return:
|
|||
mtlr 0
|
||||
blr
|
||||
|
||||
/*
|
||||
* Data used during primary/secondary traps/interrupts
|
||||
*/
|
||||
#define tempsave 0x2e0 /* primary save area for trap handling */
|
||||
#define disisave 0x3e0 /* primary save area for dsi/isi traps */
|
||||
|
||||
#define INTSTK (8*1024) /* 8K interrupt stack */
|
||||
.data
|
||||
.align 4
|
||||
intstk:
|
||||
.space INTSTK /* interrupt stack */
|
||||
|
||||
GLOBAL(intr_depth)
|
||||
.long -1 /* in-use marker */
|
||||
|
||||
#define SPILLSTK 1024 /* 1K spill stack */
|
||||
|
||||
.comm spillstk,SPILLSTK,8
|
||||
|
||||
/*
|
||||
* This code gets copied to all the trap vectors
|
||||
* (except ISI/DSI, ALI, the interrupts, and possibly the debugging
|
||||
* traps when using IPKDB).
|
||||
*/
|
||||
.text
|
||||
.globl _C_LABEL(trapcode),_C_LABEL(trapsize)
|
||||
_C_LABEL(trapcode):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
/* Test whether we already had PR set */
|
||||
mfsrr1 31
|
||||
mtcr 31
|
||||
bc 4,17,1f /* branch if PSL_PR is clear */
|
||||
lis 1,_C_LABEL(curpcb)@ha
|
||||
lwz 1,_C_LABEL(curpcb)@l(1)
|
||||
addi 1,1,USPACE /* stack is top of user struct */
|
||||
1:
|
||||
bla s_trap
|
||||
_C_LABEL(trapsize) = .-_C_LABEL(trapcode)
|
||||
|
||||
/*
|
||||
* For ALI: has to save DSISR and DAR
|
||||
*/
|
||||
.globl _C_LABEL(alitrap),_C_LABEL(alisize)
|
||||
_C_LABEL(alitrap):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mfdar 30
|
||||
mfdsisr 31
|
||||
stmw 30,tempsave+16(0)
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
/* Test whether we already had PR set */
|
||||
mfsrr1 31
|
||||
mtcr 31
|
||||
bc 4,17,1f /* branch if PSL_PR is clear */
|
||||
lis 1,_C_LABEL(curpcb)@ha
|
||||
lwz 1,_C_LABEL(curpcb)@l(1)
|
||||
addi 1,1,USPACE /* stack is top of user struct */
|
||||
1:
|
||||
bla s_trap
|
||||
_C_LABEL(alisize) = .-_C_LABEL(alitrap)
|
||||
|
||||
/*
|
||||
* Similar to the above for DSI
|
||||
* Has to handle BAT spills
|
||||
* and standard pagetable spills
|
||||
*/
|
||||
.globl _C_LABEL(dsitrap),_C_LABEL(dsisize)
|
||||
_C_LABEL(dsitrap):
|
||||
stmw 28,disisave(0) /* free r28-r31 */
|
||||
mfcr 29 /* save CR */
|
||||
mfxer 30 /* save XER */
|
||||
mtsprg 2,30 /* in SPRG2 */
|
||||
mfsrr1 31 /* test kernel mode */
|
||||
mtcr 31
|
||||
bc 12,17,1f /* branch if PSL_PR is set */
|
||||
mfdar 31 /* get fault address */
|
||||
rlwinm 31,31,7,25,28 /* get segment * 8 */
|
||||
|
||||
/* get batu */
|
||||
addis 31,31,_C_LABEL(battable)@ha
|
||||
lwz 30,_C_LABEL(battable)@l(31)
|
||||
mtcr 30
|
||||
bc 4,30,1f /* branch if supervisor valid is
|
||||
false */
|
||||
/* get batl */
|
||||
lwz 31,_C_LABEL(battable)+4@l(31)
|
||||
/* We randomly use the highest two bat registers here */
|
||||
mftb 28
|
||||
andi. 28,28,1
|
||||
bne 2f
|
||||
mtdbatu 2,30
|
||||
mtdbatl 2,31
|
||||
b 3f
|
||||
2:
|
||||
mtdbatu 3,30
|
||||
mtdbatl 3,31
|
||||
3:
|
||||
mfsprg 30,2 /* restore XER */
|
||||
mtxer 30
|
||||
mtcr 29 /* restore CR */
|
||||
lmw 28,disisave(0) /* restore r28-r31 */
|
||||
rfi /* return to trapped code */
|
||||
1:
|
||||
mflr 28 /* save LR */
|
||||
bla s_dsitrap
|
||||
_C_LABEL(dsisize) = .-_C_LABEL(dsitrap)
|
||||
|
||||
/*
|
||||
* Similar to the above for ISI
|
||||
*/
|
||||
.globl _C_LABEL(isitrap),_C_LABEL(isisize)
|
||||
_C_LABEL(isitrap):
|
||||
stmw 28,disisave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
mfsrr1 31 /* test kernel mode */
|
||||
mtcr 31
|
||||
bc 12,17,1f /* branch if PSL_PR is set */
|
||||
mfsrr0 31 /* get fault address */
|
||||
rlwinm 31,31,7,25,28 /* get segment * 8 */
|
||||
|
||||
/* get batu */
|
||||
addis 31,31,_C_LABEL(battable)@ha
|
||||
lwz 30,_C_LABEL(battable)@l(31)
|
||||
mtcr 30
|
||||
bc 4,30,1f /* branch if supervisor valid is
|
||||
false */
|
||||
mtibatu 3,30
|
||||
|
||||
/* get batl */
|
||||
lwz 30,_C_LABEL(battable)+4@l(31)
|
||||
mtibatl 3,30
|
||||
|
||||
mtcr 29 /* restore CR */
|
||||
lmw 28,disisave(0) /* restore r28-r31 */
|
||||
rfi /* return to trapped code */
|
||||
1:
|
||||
bla s_isitrap
|
||||
_C_LABEL(isisize)= .-_C_LABEL(isitrap)
|
||||
|
||||
/*
|
||||
* This one for the external interrupt handler.
|
||||
*/
|
||||
.globl _C_LABEL(extint),_C_LABEL(extsize)
|
||||
_C_LABEL(extint):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
mfxer 30 /* save XER */
|
||||
lis 1,intstk+INTSTK@ha /* get interrupt stack */
|
||||
addi 1,1,intstk+INTSTK@l
|
||||
lwz 31,0(1) /* were we already running on intstk? */
|
||||
addic. 31,31,1
|
||||
stw 31,0(1)
|
||||
beq 1f
|
||||
mfsprg 1,1 /* yes, get old SP */
|
||||
1:
|
||||
ba extintr
|
||||
_C_LABEL(extsize) = .-_C_LABEL(extint)
|
||||
|
||||
/*
|
||||
* And this one for the decrementer interrupt handler.
|
||||
*/
|
||||
.globl _C_LABEL(decrint),_C_LABEL(decrsize)
|
||||
_C_LABEL(decrint):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,tempsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
mfxer 30 /* save XER */
|
||||
lis 1,intstk+INTSTK@ha /* get interrupt stack */
|
||||
addi 1,1,intstk+INTSTK@l
|
||||
lwz 31,0(1) /* were we already running on intstk? */
|
||||
addic. 31,31,1
|
||||
stw 31,0(1)
|
||||
beq 1f
|
||||
mfsprg 1,1 /* yes, get old SP */
|
||||
1:
|
||||
ba decrintr
|
||||
_C_LABEL(decrsize) = .-_C_LABEL(decrint)
|
||||
|
||||
/*
|
||||
* Now the tlb software load for 603 processors:
|
||||
* (Code essentially from the 603e User Manual, Chapter 5, but
|
||||
* corrected a lot.)
|
||||
*/
|
||||
#define DMISS 976
|
||||
#define DCMP 977
|
||||
#define HASH1 978
|
||||
#define HASH2 979
|
||||
#define IMISS 980
|
||||
#define ICMP 981
|
||||
#define RPA 982
|
||||
|
||||
.globl _C_LABEL(tlbimiss),_C_LABEL(tlbimsize)
|
||||
_C_LABEL(tlbimiss):
|
||||
mfspr 2,HASH1 /* get first pointer */
|
||||
li 1,8
|
||||
mfctr 0 /* save counter */
|
||||
mfspr 3,ICMP /* get first compare value */
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
1:
|
||||
mtctr 1 /* load counter */
|
||||
2:
|
||||
lwzu 1,8(2) /* get next pte */
|
||||
cmpl 0,1,3 /* see if found pte */
|
||||
bdneq 2b /* loop if not eq */
|
||||
bne 3f /* not found */
|
||||
lwz 1,4(2) /* load tlb entry lower word */
|
||||
andi. 3,1,8 /* check G-bit */
|
||||
bne 4f /* if guarded, take ISI */
|
||||
mtctr 0 /* restore counter */
|
||||
mfspr 0,IMISS /* get the miss address for the tlbli */
|
||||
mfsrr1 3 /* get the saved cr0 bits */
|
||||
mtcrf 0x80,3 /* and restore */
|
||||
ori 1,1,0x100 /* set the reference bit */
|
||||
mtspr RPA,1 /* set the pte */
|
||||
srwi 1,1,8 /* get byte 7 of pte */
|
||||
tlbli 0 /* load the itlb */
|
||||
stb 1,6(2) /* update page table */
|
||||
rfi
|
||||
|
||||
3: /* not found in pteg */
|
||||
andi. 1,3,0x40 /* have we already done second hash? */
|
||||
bne 5f
|
||||
mfspr 2,HASH2 /* get the second pointer */
|
||||
ori 3,3,0x40 /* change the compare value */
|
||||
li 1,8
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
b 1b
|
||||
4: /* guarded */
|
||||
mfsrr1 3
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
oris 2,2,0x8000000@h /* set srr<4> to flag prot violation */
|
||||
b 6f
|
||||
5: /* not found anywhere */
|
||||
mfsrr1 3
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
oris 2,2,0x40000000@h /* set srr1<1> to flag pte not found */
|
||||
6:
|
||||
mtctr 0 /* restore counter */
|
||||
mtsrr1 2
|
||||
mfmsr 0
|
||||
xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
|
||||
mtcrf 0x80,3 /* restore cr0 */
|
||||
mtmsr 0 /* now with native gprs */
|
||||
isync
|
||||
ba EXC_ISI
|
||||
_C_LABEL(tlbimsize) = .-_C_LABEL(tlbimiss)
|
||||
|
||||
.globl _C_LABEL(tlbdlmiss),_C_LABEL(tlbdlmsize)
|
||||
_C_LABEL(tlbdlmiss):
|
||||
mfspr 2,HASH1 /* get first pointer */
|
||||
li 1,8
|
||||
mfctr 0 /* save counter */
|
||||
mfspr 3,DCMP /* get first compare value */
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
1:
|
||||
mtctr 1 /* load counter */
|
||||
2:
|
||||
lwzu 1,8(2) /* get next pte */
|
||||
cmpl 0,1,3 /* see if found pte */
|
||||
bdneq 2b /* loop if not eq */
|
||||
bne 3f /* not found */
|
||||
lwz 1,4(2) /* load tlb entry lower word */
|
||||
mtctr 0 /* restore counter */
|
||||
mfspr 0,DMISS /* get the miss address for the tlbld */
|
||||
mfsrr1 3 /* get the saved cr0 bits */
|
||||
mtcrf 0x80,3 /* and restore */
|
||||
ori 1,1,0x100 /* set the reference bit */
|
||||
mtspr RPA,1 /* set the pte */
|
||||
srwi 1,1,8 /* get byte 7 of pte */
|
||||
tlbld 0 /* load the dtlb */
|
||||
stb 1,6(2) /* update page table */
|
||||
rfi
|
||||
|
||||
3: /* not found in pteg */
|
||||
andi. 1,3,0x40 /* have we already done second hash? */
|
||||
bne 5f
|
||||
mfspr 2,HASH2 /* get the second pointer */
|
||||
ori 3,3,0x40 /* change the compare value */
|
||||
li 1,8
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
b 1b
|
||||
5: /* not found anywhere */
|
||||
mfsrr1 3
|
||||
lis 1,0x40000000@h /* set dsisr<1> to flag pte not found */
|
||||
mtctr 0 /* restore counter */
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
mtsrr1 2
|
||||
mtdsisr 1 /* load the dsisr */
|
||||
mfspr 1,DMISS /* get the miss address */
|
||||
mtdar 1 /* put in dar */
|
||||
mfmsr 0
|
||||
xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
|
||||
mtcrf 0x80,3 /* restore cr0 */
|
||||
mtmsr 0 /* now with native gprs */
|
||||
isync
|
||||
ba EXC_DSI
|
||||
_C_LABEL(tlbdlmsize) = .-_C_LABEL(tlbdlmiss)
|
||||
|
||||
.globl _C_LABEL(tlbdsmiss),_C_LABEL(tlbdsmsize)
|
||||
_C_LABEL(tlbdsmiss):
|
||||
mfspr 2,HASH1 /* get first pointer */
|
||||
li 1,8
|
||||
mfctr 0 /* save counter */
|
||||
mfspr 3,DCMP /* get first compare value */
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
1:
|
||||
mtctr 1 /* load counter */
|
||||
2:
|
||||
lwzu 1,8(2) /* get next pte */
|
||||
cmpl 0,1,3 /* see if found pte */
|
||||
bdneq 2b /* loop if not eq */
|
||||
bne 3f /* not found */
|
||||
lwz 1,4(2) /* load tlb entry lower word */
|
||||
andi. 3,1,0x80 /* check the C-bit */
|
||||
beq 4f
|
||||
5:
|
||||
mtctr 0 /* restore counter */
|
||||
mfspr 0,DMISS /* get the miss address for the tlbld */
|
||||
mfsrr1 3 /* get the saved cr0 bits */
|
||||
mtcrf 0x80,3 /* and restore */
|
||||
mtspr RPA,1 /* set the pte */
|
||||
tlbld 0 /* load the dtlb */
|
||||
rfi
|
||||
|
||||
3: /* not found in pteg */
|
||||
andi. 1,3,0x40 /* have we already done second hash? */
|
||||
bne 5f
|
||||
mfspr 2,HASH2 /* get the second pointer */
|
||||
ori 3,3,0x40 /* change the compare value */
|
||||
li 1,8
|
||||
addi 2,2,-8 /* predec pointer */
|
||||
b 1b
|
||||
4: /* found, but C-bit = 0 */
|
||||
rlwinm. 3,1,30,0,1 /* test PP */
|
||||
bge- 7f
|
||||
andi. 3,1,1
|
||||
beq+ 8f
|
||||
9: /* found, but protection violation (PP==00)*/
|
||||
mfsrr1 3
|
||||
lis 1,0xa000000@h /* indicate protection violation
|
||||
on store */
|
||||
b 1f
|
||||
7: /* found, PP=1x */
|
||||
mfspr 3,DMISS /* get the miss address */
|
||||
mfsrin 1,3 /* get the segment register */
|
||||
mfsrr1 3
|
||||
rlwinm 3,3,18,31,31 /* get PR-bit */
|
||||
rlwnm. 2,2,3,1,1 /* get the key */
|
||||
bne- 9b /* protection violation */
|
||||
8: /* found, set reference/change bits */
|
||||
lwz 1,4(2) /* reload tlb entry */
|
||||
ori 1,1,0x180
|
||||
sth 1,6(2)
|
||||
b 5b
|
||||
5: /* not found anywhere */
|
||||
mfsrr1 3
|
||||
lis 1,0x42000000@h /* set dsisr<1> to flag pte not found */
|
||||
/* dsisr<6> to flag store */
|
||||
1:
|
||||
mtctr 0 /* restore counter */
|
||||
andi. 2,3,0xffff /* clean upper srr1 */
|
||||
mtsrr1 2
|
||||
mtdsisr 1 /* load the dsisr */
|
||||
mfspr 1,DMISS /* get the miss address */
|
||||
mtdar 1 /* put in dar */
|
||||
mfmsr 0
|
||||
xoris 0,0,0x20000@h /* flip the msr<tgpr> bit */
|
||||
mtcrf 0x80,3 /* restore cr0 */
|
||||
mtmsr 0 /* now with native gprs */
|
||||
isync
|
||||
ba EXC_DSI
|
||||
_C_LABEL(tlbdsmsize) = .-_C_LABEL(tlbdsmiss)
|
||||
|
||||
#ifdef DDB
|
||||
#define ddbsave 0xde0 /* primary save area for DDB */
|
||||
/*
|
||||
* In case of DDB we want a separate trap catcher for it
|
||||
*/
|
||||
.local ddbstk
|
||||
.comm ddbstk,INTSTK,8 /* ddb stack */
|
||||
|
||||
.globl _C_LABEL(ddblow),_C_LABEL(ddbsize)
|
||||
_C_LABEL(ddblow):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,ddbsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
lis 1,ddbstk+INTSTK@ha /* get new SP */
|
||||
addi 1,1,ddbstk+INTSTK@l
|
||||
bla ddbtrap
|
||||
_C_LABEL(ddbsize) = .-_C_LABEL(ddblow)
|
||||
#endif /* DDB */
|
||||
|
||||
#ifdef IPKDB
|
||||
#define ipkdbsave 0xde0 /* primary save area for IPKDB */
|
||||
/*
|
||||
* In case of IPKDB we want a separate trap catcher for it
|
||||
*/
|
||||
|
||||
.local ipkdbstk
|
||||
.comm ipkdbstk,INTSTK,8 /* ipkdb stack */
|
||||
|
||||
.globl _C_LABEL(ipkdblow),_C_LABEL(ipkdbsize)
|
||||
_C_LABEL(ipkdblow):
|
||||
mtsprg 1,1 /* save SP */
|
||||
stmw 28,ipkdbsave(0) /* free r28-r31 */
|
||||
mflr 28 /* save LR */
|
||||
mfcr 29 /* save CR */
|
||||
lis 1,ipkdbstk+INTSTK@ha /* get new SP */
|
||||
addi 1,1,ipkdbstk+INTSTK@l
|
||||
bla ipkdbtrap
|
||||
_C_LABEL(ipkdbsize) = .-_C_LABEL(ipkdblow)
|
||||
#endif /* IPKDB */
|
||||
|
||||
/*
|
||||
* FRAME_SETUP assumes:
|
||||
* SPRG1 SP (1)
|
||||
* savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
|
||||
* 28 LR
|
||||
* 29 CR
|
||||
* 1 kernel stack
|
||||
* LR trap type
|
||||
* SRR0/1 as at start of trap
|
||||
*/
|
||||
#define FRAME_SETUP(savearea) \
|
||||
/* Have to enable translation to allow access of kernel stack: */ \
|
||||
mfsrr0 30; \
|
||||
mfsrr1 31; \
|
||||
stmw 30,savearea+24(0); \
|
||||
mfmsr 30; \
|
||||
ori 30,30,(PSL_DR|PSL_IR); \
|
||||
mtmsr 30; \
|
||||
isync; \
|
||||
mfsprg 31,1; \
|
||||
stwu 31,-FRAMELEN(1); \
|
||||
stw 0,FRAME_0+8(1); \
|
||||
stw 31,FRAME_1+8(1); \
|
||||
stw 28,FRAME_LR+8(1); \
|
||||
stw 29,FRAME_CR+8(1); \
|
||||
lmw 28,savearea(0); \
|
||||
stmw 2,FRAME_2+8(1); \
|
||||
lmw 28,savearea+16(0); \
|
||||
mfxer 3; \
|
||||
mfctr 4; \
|
||||
mflr 5; \
|
||||
andi. 5,5,0xff00; \
|
||||
stw 3,FRAME_XER+8(1); \
|
||||
stw 4,FRAME_CTR+8(1); \
|
||||
stw 5,FRAME_EXC+8(1); \
|
||||
stw 28,FRAME_DAR+8(1); \
|
||||
stw 29,FRAME_DSISR+8(1); \
|
||||
stw 30,FRAME_SRR0+8(1); \
|
||||
stw 31,FRAME_SRR1+8(1)
|
||||
|
||||
#define FRAME_LEAVE(savearea) \
|
||||
/* Now restore regs: */ \
|
||||
lwz 2,FRAME_SRR0+8(1); \
|
||||
lwz 3,FRAME_SRR1+8(1); \
|
||||
lwz 4,FRAME_CTR+8(1); \
|
||||
lwz 5,FRAME_XER+8(1); \
|
||||
lwz 6,FRAME_LR+8(1); \
|
||||
lwz 7,FRAME_CR+8(1); \
|
||||
stw 2,savearea(0); \
|
||||
stw 3,savearea+4(0); \
|
||||
mtctr 4; \
|
||||
mtxer 5; \
|
||||
mtlr 6; \
|
||||
mtsprg 1,7; /* save cr */ \
|
||||
lmw 2,FRAME_2+8(1); \
|
||||
lwz 0,FRAME_0+8(1); \
|
||||
lwz 1,FRAME_1+8(1); \
|
||||
mtsprg 2,2; /* save r2 & r3 */ \
|
||||
mtsprg 3,3; \
|
||||
/* Disable translation, machine check and recoverability: */ \
|
||||
mfmsr 2; \
|
||||
andi. 2,2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
|
||||
mtmsr 2; \
|
||||
isync; \
|
||||
/* Decide whether we return to user mode: */ \
|
||||
lwz 3,savearea+4(0); \
|
||||
mtcr 3; \
|
||||
bc 4,17,1f; /* branch if PSL_PR is false */ \
|
||||
/* Restore user & kernel access SR: */ \
|
||||
lis 2,_C_LABEL(curpm)@ha; /* get real address of pmap */ \
|
||||
lwz 2,_C_LABEL(curpm)@l(2); \
|
||||
lwz 3,PM_USRSR(2); \
|
||||
mtsr USER_SR,3; \
|
||||
lwz 3,PM_KERNELSR(2); \
|
||||
mtsr KERNEL_SR,3; \
|
||||
1: mfsprg 2,1; /* restore cr */ \
|
||||
mtcr 2; \
|
||||
lwz 2,savearea(0); \
|
||||
lwz 3,savearea+4(0); \
|
||||
mtsrr0 2; \
|
||||
mtsrr1 3; \
|
||||
mfsprg 2,2; /* restore r2 & r3 */ \
|
||||
mfsprg 3,3
|
||||
|
||||
/*
|
||||
* Preamble code for DSI/ISI traps
|
||||
*/
|
||||
disitrap:
|
||||
lmw 30,disisave(0)
|
||||
stmw 30,tempsave(0)
|
||||
lmw 30,disisave+8(0)
|
||||
stmw 30,tempsave+8(0)
|
||||
mfdar 30
|
||||
mfdsisr 31
|
||||
stmw 30,tempsave+16(0)
|
||||
realtrap:
|
||||
/* Test whether we already had PR set */
|
||||
mfsrr1 1
|
||||
mtcr 1
|
||||
mfsprg 1,1 /* restore SP (might have been
|
||||
overwritten) */
|
||||
bc 4,17,s_trap /* branch if PSL_PR is false */
|
||||
lis 1,_C_LABEL(curpcb)@ha
|
||||
lwz 1,_C_LABEL(curpcb)@l(1)
|
||||
addi 1,1,USPACE /* stack is top of user struct */
|
||||
|
||||
/*
|
||||
* Now the common trap catching code.
|
||||
*/
|
||||
s_trap:
|
||||
/* First have to enable KERNEL mapping */
|
||||
lis 31,KERNEL_SEGMENT@h
|
||||
ori 31,31,KERNEL_SEGMENT@l
|
||||
mtsr KERNEL_SR,31
|
||||
FRAME_SETUP(tempsave)
|
||||
/* Now we can recover interrupts again: */
|
||||
mfmsr 7
|
||||
ori 7,7,(PSL_EE|PSL_ME|PSL_RI)@l
|
||||
mtmsr 7
|
||||
isync
|
||||
/* Call C trap code: */
|
||||
trapagain:
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(trap)
|
||||
trapexit:
|
||||
/* Disable interrupts: */
|
||||
mfmsr 3
|
||||
andi. 3,3,~PSL_EE@l
|
||||
mtmsr 3
|
||||
/* Test AST pending: */
|
||||
lwz 5,FRAME_SRR1+8(1)
|
||||
mtcr 5
|
||||
bc 4,17,1f /* branch if PSL_PR is false */
|
||||
lis 3,_C_LABEL(astpending)@ha
|
||||
lwz 4,_C_LABEL(astpending)@l(3)
|
||||
andi. 4,4,1
|
||||
beq 1f
|
||||
li 6,EXC_AST
|
||||
stw 6,FRAME_EXC+8(1)
|
||||
b trapagain
|
||||
1:
|
||||
FRAME_LEAVE(tempsave)
|
||||
rfi
|
||||
|
||||
/*
|
||||
* Child comes here at the end of a fork.
|
||||
* Mostly similar to the above.
|
||||
* Return to userspace via the trap return path.
|
||||
*/
|
||||
.globl _C_LABEL(fork_trampoline)
|
||||
_C_LABEL(fork_trampoline):
|
||||
|
|
@ -986,367 +420,10 @@ _C_LABEL(fork_trampoline):
|
|||
b trapexit
|
||||
|
||||
/*
|
||||
* DSI second stage fault handler
|
||||
* Pull in common trap vector code.
|
||||
*/
|
||||
s_dsitrap:
|
||||
mfdsisr 31 /* test whether this may be a
|
||||
spill fault */
|
||||
mtcr 31
|
||||
mtsprg 1,1 /* save SP */
|
||||
bc 4,1,disitrap /* branch if table miss is false */
|
||||
lis 1,spillstk+SPILLSTK@ha
|
||||
addi 1,1,spillstk+SPILLSTK@l /* get spill stack */
|
||||
stwu 1,-52(1)
|
||||
stw 0,48(1) /* save non-volatile registers */
|
||||
stw 3,44(1)
|
||||
stw 4,40(1)
|
||||
stw 5,36(1)
|
||||
stw 6,32(1)
|
||||
stw 7,28(1)
|
||||
stw 8,24(1)
|
||||
stw 9,20(1)
|
||||
stw 10,16(1)
|
||||
stw 11,12(1)
|
||||
stw 12,8(1)
|
||||
mflr 30 /* save trap type */
|
||||
mfctr 31 /* & CTR */
|
||||
mfdar 3
|
||||
s_pte_spill:
|
||||
bl _C_LABEL(pte_spill) /* try a spill */
|
||||
or. 3,3,3
|
||||
mtctr 31 /* restore CTR */
|
||||
mtlr 30 /* and trap type */
|
||||
mfsprg 31,2 /* get saved XER */
|
||||
mtxer 31 /* restore XER */
|
||||
lwz 12,8(1) /* restore non-volatile registers */
|
||||
lwz 11,12(1)
|
||||
lwz 10,16(1)
|
||||
lwz 9,20(1)
|
||||
lwz 8,24(1)
|
||||
lwz 7,28(1)
|
||||
lwz 6,32(1)
|
||||
lwz 5,36(1)
|
||||
lwz 4,40(1)
|
||||
lwz 3,44(1)
|
||||
lwz 0,48(1)
|
||||
beq disitrap
|
||||
mfsprg 1,1 /* restore SP */
|
||||
mtcr 29 /* restore CR */
|
||||
mtlr 28 /* restore LR */
|
||||
lmw 28,disisave(0) /* restore r28-r31 */
|
||||
rfi /* return to trapped code */
|
||||
#include <powerpc/powerpc/trap_subr.S>
|
||||
|
||||
/*
|
||||
* ISI second stage fault handler
|
||||
*/
|
||||
s_isitrap:
|
||||
mfsrr1 31 /* test whether this may be a
|
||||
spill fault */
|
||||
mtcr 31
|
||||
mtsprg 1,1 /* save SP */
|
||||
bc 4,1,disitrap /* branch if table miss is false */
|
||||
lis 1,spillstk+SPILLSTK@ha
|
||||
addi 1,1,spillstk+SPILLSTK@l /* get spill stack */
|
||||
stwu 1,-52(1)
|
||||
stw 0,48(1) /* save non-volatile registers */
|
||||
stw 3,44(1)
|
||||
stw 4,40(1)
|
||||
stw 5,36(1)
|
||||
stw 6,32(1)
|
||||
stw 7,28(1)
|
||||
stw 8,24(1)
|
||||
stw 9,20(1)
|
||||
stw 10,16(1)
|
||||
stw 11,12(1)
|
||||
stw 12,8(1)
|
||||
mfxer 30 /* save XER */
|
||||
mtsprg 2,30
|
||||
mflr 30 /* save trap type */
|
||||
mfctr 31 /* & ctr */
|
||||
mfsrr0 3
|
||||
b s_pte_spill /* above */
|
||||
|
||||
/*
|
||||
* External interrupt second level handler
|
||||
*/
|
||||
#define INTRENTER \
|
||||
/* Save non-volatile registers: */ \
|
||||
stwu 1,-88(1); /* temporarily */ \
|
||||
stw 0,84(1); \
|
||||
mfsprg 0,1; /* get original SP */ \
|
||||
stw 0,0(1); /* and store it */ \
|
||||
stw 3,80(1); \
|
||||
stw 4,76(1); \
|
||||
stw 5,72(1); \
|
||||
stw 6,68(1); \
|
||||
stw 7,64(1); \
|
||||
stw 8,60(1); \
|
||||
stw 9,56(1); \
|
||||
stw 10,52(1); \
|
||||
stw 11,48(1); \
|
||||
stw 12,44(1); \
|
||||
stw 28,40(1); /* saved LR */ \
|
||||
stw 29,36(1); /* saved CR */ \
|
||||
stw 30,32(1); /* saved XER */ \
|
||||
lmw 28,tempsave(0); /* restore r28-r31 */ \
|
||||
mfctr 6; \
|
||||
lis 5,_C_LABEL(intr_depth)@ha; \
|
||||
lwz 5,_C_LABEL(intr_depth)@l(5); \
|
||||
mfsrr0 4; \
|
||||
mfsrr1 3; \
|
||||
stw 6,28(1); \
|
||||
stw 5,20(1); \
|
||||
stw 4,12(1); \
|
||||
stw 3,8(1); \
|
||||
/* interrupts are recoverable here, and enable translation */ \
|
||||
lis 3,(KERNEL_SEGMENT|SR_SUKEY|SR_PRKEY)@h; \
|
||||
ori 3,3,(KERNEL_SEGMENT|SR_SUKEY|SR_PRKEY)@l; \
|
||||
mtsr KERNEL_SR,3; \
|
||||
mfmsr 5; \
|
||||
ori 5,5,(PSL_IR|PSL_DR|PSL_RI); \
|
||||
mtmsr 5; \
|
||||
isync
|
||||
|
||||
.globl _C_LABEL(extint_call)
|
||||
extintr:
|
||||
INTRENTER
|
||||
_C_LABEL(extint_call):
|
||||
bl _C_LABEL(extint_call) /* to be filled in later */
|
||||
|
||||
intr_exit:
|
||||
/* Disable interrupts (should already be disabled) and MMU here: */
|
||||
mfmsr 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME|PSL_RI|PSL_DR|PSL_IR)@l
|
||||
mtmsr 3
|
||||
isync
|
||||
/* restore possibly overwritten registers: */
|
||||
lwz 12,44(1)
|
||||
lwz 11,48(1)
|
||||
lwz 10,52(1)
|
||||
lwz 9,56(1)
|
||||
lwz 8,60(1)
|
||||
lwz 7,64(1)
|
||||
lwz 6,8(1)
|
||||
lwz 5,12(1)
|
||||
lwz 4,28(1)
|
||||
lwz 3,32(1)
|
||||
mtsrr1 6
|
||||
mtsrr0 5
|
||||
mtctr 4
|
||||
mtxer 3
|
||||
/* Returning to user mode? */
|
||||
mtcr 6 /* saved SRR1 */
|
||||
bc 4,17,1f /* branch if PSL_PR is false */
|
||||
lis 3,_C_LABEL(curpm)@ha /* get current pmap real address */
|
||||
lwz 3,_C_LABEL(curpm)@l(3)
|
||||
lwz 3,PM_KERNELSR(3)
|
||||
mtsr KERNEL_SR,3 /* Restore kernel SR */
|
||||
lis 3,_C_LABEL(astpending)@ha /* Test AST pending */
|
||||
lwz 4,_C_LABEL(astpending)@l(3)
|
||||
andi. 4,4,1
|
||||
beq 1f
|
||||
/* Setup for entry to realtrap: */
|
||||
lwz 3,0(1) /* get saved SP */
|
||||
mtsprg 1,3
|
||||
li 6,EXC_AST
|
||||
stmw 28,tempsave(0) /* establish tempsave again */
|
||||
mtlr 6
|
||||
lwz 28,40(1) /* saved LR */
|
||||
lwz 29,36(1) /* saved CR */
|
||||
lwz 6,68(1)
|
||||
lwz 5,72(1)
|
||||
lwz 4,76(1)
|
||||
lwz 3,80(1)
|
||||
lwz 0,84(1)
|
||||
lis 30,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
|
||||
lwz 31,_C_LABEL(intr_depth)@l(30)
|
||||
addi 31,31,-1
|
||||
stw 31,_C_LABEL(intr_depth)@l(30)
|
||||
b realtrap
|
||||
1:
|
||||
/* Here is the normal exit of extintr: */
|
||||
lwz 5,36(1)
|
||||
lwz 6,40(1)
|
||||
mtcr 5
|
||||
mtlr 6
|
||||
lwz 6,68(1)
|
||||
lwz 5,72(1)
|
||||
lis 3,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
|
||||
lwz 4,_C_LABEL(intr_depth)@l(3)
|
||||
addi 4,4,-1
|
||||
stw 4,_C_LABEL(intr_depth)@l(3)
|
||||
lwz 4,76(1)
|
||||
lwz 3,80(1)
|
||||
lwz 0,84(1)
|
||||
lwz 1,0(1)
|
||||
rfi
|
||||
|
||||
/*
|
||||
* Decrementer interrupt second level handler
|
||||
*/
|
||||
decrintr:
|
||||
INTRENTER
|
||||
addi 3,1,8 /* intr frame */
|
||||
bl _C_LABEL(decr_intr)
|
||||
b intr_exit
|
||||
|
||||
#ifdef DDB
|
||||
/*
|
||||
* Deliberate entry to ddbtrap
|
||||
*/
|
||||
.globl _C_LABEL(ddb_trap)
|
||||
_C_LABEL(ddb_trap):
|
||||
mtsprg 1,1
|
||||
mfmsr 3
|
||||
mtsrr1 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME)@l
|
||||
mtmsr 3 /* disable interrupts */
|
||||
isync
|
||||
stmw 28,ddbsave(0)
|
||||
mflr 28
|
||||
li 29,EXC_BPT
|
||||
mtlr 29
|
||||
mfcr 29
|
||||
mtsrr0 28
|
||||
|
||||
/*
|
||||
* Now the ddb trap catching code.
|
||||
*/
|
||||
ddbtrap:
|
||||
FRAME_SETUP(ddbsave)
|
||||
/* Call C trap code: */
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(ddb_trap_glue)
|
||||
or. 3,3,3
|
||||
bne ddbleave
|
||||
/* This wasn't for DDB, so switch to real trap: */
|
||||
lwz 3,FRAME_EXC+8(1) /* save exception */
|
||||
stw 3,ddbsave+8(0)
|
||||
FRAME_LEAVE(ddbsave)
|
||||
mtsprg 1,1 /* prepare for entrance to realtrap */
|
||||
stmw 28,tempsave(0)
|
||||
mflr 28
|
||||
mfcr 29
|
||||
lwz 31,ddbsave+8(0)
|
||||
mtlr 31
|
||||
b realtrap
|
||||
ddbleave:
|
||||
FRAME_LEAVE(ddbsave)
|
||||
rfi
|
||||
#endif /* DDB */
|
||||
|
||||
#ifdef IPKDB
|
||||
/*
|
||||
* Deliberate entry to ipkdbtrap
|
||||
*/
|
||||
.globl _C_LABEL(ipkdb_trap)
|
||||
_C_LABEL(ipkdb_trap):
|
||||
mtsprg 1,1
|
||||
mfmsr 3
|
||||
mtsrr1 3
|
||||
andi. 3,3,~(PSL_EE|PSL_ME)@l
|
||||
mtmsr 3 /* disable interrupts */
|
||||
isync
|
||||
stmw 28,ipkdbsave(0)
|
||||
mflr 28
|
||||
li 29,EXC_BPT
|
||||
mtlr 29
|
||||
mfcr 29
|
||||
mtsrr0 28
|
||||
|
||||
/*
|
||||
* Now the ipkdb trap catching code.
|
||||
*/
|
||||
ipkdbtrap:
|
||||
FRAME_SETUP(ipkdbsave)
|
||||
/* Call C trap code: */
|
||||
addi 3,1,8
|
||||
bl _C_LABEL(ipkdb_trap_glue)
|
||||
or. 3,3,3
|
||||
bne ipkdbleave
|
||||
/* This wasn't for IPKDB, so switch to real trap: */
|
||||
lwz 3,FRAME_EXC+8(1) /* save exception */
|
||||
stw 3,ipkdbsave+8(0)
|
||||
FRAME_LEAVE(ipkdbsave)
|
||||
mtsprg 1,1 /* prepare for entrance to realtrap */
|
||||
stmw 28,tempsave(0)
|
||||
mflr 28
|
||||
mfcr 29
|
||||
lwz 31,ipkdbsave+8(0)
|
||||
mtlr 31
|
||||
b realtrap
|
||||
ipkdbleave:
|
||||
FRAME_LEAVE(ipkdbsave)
|
||||
rfi
|
||||
|
||||
ipkdbfault:
|
||||
ba _ipkdbfault
|
||||
_ipkdbfault:
|
||||
mfsrr0 3
|
||||
addi 3,3,4
|
||||
mtsrr0 3
|
||||
li 3,-1
|
||||
rfi
|
||||
|
||||
/*
|
||||
* int ipkdbfbyte(unsigned char *p)
|
||||
*/
|
||||
.globl _C_LABEL(ipkdbfbyte)
|
||||
_C_LABEL(ipkdbfbyte):
|
||||
li 9,EXC_DSI /* establish new fault routine */
|
||||
lwz 5,0(9)
|
||||
lis 6,ipkdbfault@ha
|
||||
lwz 6,ipkdbfault@l(6)
|
||||
stw 6,0(9)
|
||||
#ifdef IPKDBUSERHACK
|
||||
lis 8,_C_LABEL(ipkdbsr)@ha
|
||||
lwz 8,_C_LABEL(ipkdbsr)@l(8)
|
||||
mtsr USER_SR,8
|
||||
isync
|
||||
#endif
|
||||
dcbst 0,9 /* flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
lbz 3,0(3) /* fetch data */
|
||||
stw 5,0(9) /* restore previous fault handler */
|
||||
dcbst 0,9 /* and flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
blr
|
||||
|
||||
/*
|
||||
* int ipkdbsbyte(unsigned char *p, int c)
|
||||
*/
|
||||
.globl _C_LABEL(ipkdbsbyte)
|
||||
_C_LABEL(ipkdbsbyte):
|
||||
li 9,EXC_DSI /* establish new fault routine */
|
||||
lwz 5,0(9)
|
||||
lis 6,ipkdbfault@ha
|
||||
lwz 6,ipkdbfault@l(6)
|
||||
stw 6,0(9)
|
||||
#ifdef IPKDBUSERHACK
|
||||
lis 8,_C_LABEL(ipkdbsr)@ha
|
||||
lwz 8,_C_LABEL(ipkdbsr)@l(8)
|
||||
mtsr USER_SR,8
|
||||
isync
|
||||
#endif
|
||||
dcbst 0,9 /* flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
mr 6,3
|
||||
xor 3,3,3
|
||||
stb 4,0(6)
|
||||
dcbst 0,6 /* Now do appropriate flushes
|
||||
to data... */
|
||||
sync
|
||||
icbi 0,6 /* and instruction caches */
|
||||
stw 5,0(9) /* restore previous fault handler */
|
||||
dcbst 0,9 /* and flush data... */
|
||||
sync
|
||||
icbi 0,9 /* and instruction caches */
|
||||
blr
|
||||
#endif /* IPKDB */
|
||||
|
||||
/*
|
||||
* int setfault()
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue