According to diffs from Waldi Raven:
Make speed/clock-source selection smarter. This makes the baudrates more accurate and allows speeds upto 115k baud.
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leo
parent
27a11d1735
commit
d8cb2b8dfa
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@ -1,4 +1,4 @@
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/* $NetBSD: zs.c,v 1.5 1995/05/14 15:55:51 leo Exp $ */
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/* $NetBSD: zs.c,v 1.6 1995/05/28 19:50:26 leo Exp $ */
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/*
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* Copyright (c) 1995 L. Weppelman (Atari modifications)
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@ -94,7 +94,7 @@ struct zs_softc {
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/*
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* Define the registers for a closed port
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*/
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u_char zs_init_regs[16] = {
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static u_char zs_init_regs[16] = {
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/* 0 */ 0,
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/* 1 */ 0,
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/* 2 */ 0x60,
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@ -113,6 +113,58 @@ u_char zs_init_regs[16] = {
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/* 15 */ 0
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};
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/*
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* Define the machine dependant clock frequencies
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* If BRgen feeds sender/receiver we always use a
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* divisor 16, therefor the division by 16 can as
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* well be done here.
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*/
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static u_long zs_freqs_tt[] = {
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/*
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* Atari TT, RTxCB is generated by TT-MFP timer C,
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* which is set to 307.2KHz during initialisation
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* and never changed afterwards.
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*/
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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229500, /* BRgen, RTxCA, divisor 16 */
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3672000, /* RTxCA, from PCLK4 */
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0, /* TRxCA, external */
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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19200, /* BRgen, RTxCB, divisor 16 */
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307200, /* RTxCB, from TT-MFP TCO */
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2457600 /* TRxCB, from BCLK */
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};
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static u_long zs_freqs_falcon[] = {
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/*
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* Atari Falcon, XXX no specs available, this might be wrong
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*/
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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229500, /* BRgen, RTxCA, divisor 16 */
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3672000, /* RTxCA, ??? */
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0, /* TRxCA, external */
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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229500, /* BRgen, RTxCB, divisor 16 */
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3672000, /* RTxCB, ??? */
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2457600 /* TRxCB, ??? */
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};
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static u_long zs_freqs_generic[] = {
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/*
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* other machines, assume only PCLK is available
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*/
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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0, /* BRgen, RTxCA, divisor 16 */
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0, /* RTxCA, unknown */
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0, /* TRxCA, unknown */
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PCLK/16, /* BRgen, PCLK, divisor 16 */
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0, /* BRgen, RTxCB, divisor 16 */
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0, /* RTxCB, unknown */
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0 /* TRxCB, unknown */
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};
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static u_long *zs_frequencies;
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/* Definition of the driver for autoconfig. */
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static int zsmatch __P((struct device *, struct cfdata *, void *));
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static void zsattach __P((struct device *, struct device *, void *));
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@ -127,19 +179,20 @@ static int zsrint __P((struct zs_chanstate *, volatile struct zschan *));
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static int zsxint __P((struct zs_chanstate *, volatile struct zschan *));
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static int zssint __P((struct zs_chanstate *, volatile struct zschan *));
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struct zs_chanstate *zslist;
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static struct zs_chanstate *zslist;
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/* Routines called from other code. */
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static void zsstart __P((struct tty *));
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void zsstop __P((struct tty *, int));
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static int zsparam __P((struct tty *, struct termios *));
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static int zsbaudrate __P((int, int, int *, int *, int *, int *));
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/* Routines purely local to this driver. */
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static void zs_reset __P((volatile struct zschan *, int, int));
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static int zs_modem __P((struct zs_chanstate *, int, int));
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static void zs_loadchannelregs __P((volatile struct zschan *, u_char *));
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int zsshortcuts; /* number of "shortcut" software interrupts */
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static int zsshortcuts; /* number of "shortcut" software interrupts */
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static int
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zsmatch(pdp, cfp, auxp)
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@ -194,10 +247,27 @@ void *aux;
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zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs);
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if(machineid & ATARI_TT) {
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/*
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* ininitialise TT-MFP timer C: 307200Hz
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* timer C and D share one control register:
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* bits 0-2 control timer D
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* bits 4-6 control timer C
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*/
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int cr = MFP2->mf_tcdcr & 7;
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MFP2->mf_tcdcr = cr; /* stop timer C */
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MFP2->mf_tcdr = 1; /* counter 1 */
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cr |= T_Q004 << 4; /* divisor 4 */
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MFP2->mf_tcdcr = cr; /* start timer C */
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/*
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* enable scc related interrupts
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*/
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SCU->sys_mask |= SCU_SCC;
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zs_frequencies = zs_freqs_tt;
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} else if (machineid & ATARI_FALCON) {
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zs_frequencies = zs_freqs_falcon;
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} else {
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zs_frequencies = zs_freqs_generic;
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}
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/* link into interrupt list with order (A,B) (B=A+1) */
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@ -881,32 +951,33 @@ register struct termios *t;
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int unit = ZS_UNIT(tp->t_dev);
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struct zs_softc *zi = zscd.cd_devs[unit >> 1];
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register struct zs_chanstate *cs = &zi->zi_cs[unit & 1];
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int cdiv, clkm, brgm, tcon;
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register int tmp, tmp5, cflag, s;
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tmp = t->c_ospeed;
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if(tmp < 0 || (t->c_ispeed && t->c_ispeed != tmp))
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tmp = t->c_ospeed;
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tmp5 = t->c_ispeed;
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if(tmp < 0 || (tmp5 && tmp5 != tmp))
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return(EINVAL);
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if(tmp == 0) {
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/* stty 0 => drop DTR and RTS */
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zs_modem(cs, 0, DMSET);
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return(0);
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}
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tmp = BPS_TO_TCONST(PCLK / 16, tmp);
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if(tmp < 2)
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tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon);
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if (tmp < 0)
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return(EINVAL);
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tp->t_ispeed = tp->t_ospeed = tmp;
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cflag = t->c_cflag;
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tp->t_ispeed = tp->t_ospeed = TCONST_TO_BPS(PCLK / 16, tmp);
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tp->t_cflag = cflag;
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cflag = tp->t_cflag = t->c_cflag;
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if (cflag & CSTOPB)
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cdiv |= ZSWR4_TWOSB;
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else
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cdiv |= ZSWR4_ONESB;
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if (!(cflag & PARODD))
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cdiv |= ZSWR4_EVENP;
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if (cflag & PARENB)
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cdiv |= ZSWR4_PARENB;
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/*
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* Block interrupts so that state will not
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* be altered until we are done setting it up.
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*/
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s = splzs();
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cs->cs_preg[12] = tmp;
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cs->cs_preg[13] = tmp >> 8;
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cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE;
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switch(cflag & CSIZE) {
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case CS5:
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tmp = ZSWR3_RX_5;
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@ -926,6 +997,23 @@ register struct termios *t;
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tmp5 = ZSWR5_TX_8;
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break;
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}
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tmp |= ZSWR3_RX_ENABLE;
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tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS;
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/*
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* Block interrupts so that state will not
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* be altered until we are done setting it up.
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*/
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s = splzs();
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cs->cs_preg[4] = cdiv;
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cs->cs_preg[11] = clkm;
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cs->cs_preg[12] = tcon;
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cs->cs_preg[13] = tcon >> 8;
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cs->cs_preg[14] = brgm;
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cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE;
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cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT;
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cs->cs_preg[10] = ZSWR10_NRZ;
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cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE;
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/*
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* Output hardware flow control on the chip is horrendous: if
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@ -933,22 +1021,9 @@ register struct termios *t;
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* can only do this when the carrier is on.
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*/
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if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD)
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tmp |= ZSWR3_HFC | ZSWR3_RX_ENABLE;
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else tmp |= ZSWR3_RX_ENABLE;
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tmp |= ZSWR3_HFC;
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cs->cs_preg[3] = tmp;
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cs->cs_preg[5] = tmp5 | ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS;
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tmp = ZSWR4_CLK_X16 | (cflag & CSTOPB ? ZSWR4_TWOSB : ZSWR4_ONESB);
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if((cflag & PARODD) == 0)
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tmp |= ZSWR4_EVENP;
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if (cflag & PARENB)
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tmp |= ZSWR4_PARENB;
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cs->cs_preg[4] = tmp;
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cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT;
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cs->cs_preg[10] = ZSWR10_NRZ;
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cs->cs_preg[11] = ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD;
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cs->cs_preg[14] = ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA;
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cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE;
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cs->cs_preg[5] = tmp5;
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/*
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* If nothing is being transmitted, set up new current values,
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@ -959,8 +1034,7 @@ register struct termios *t;
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cs->cs_heldtbc = cs->cs_tbc;
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cs->cs_tbc = 0;
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cs->cs_heldchange = 1;
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}
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else {
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} else {
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bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16);
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zs_loadchannelregs(cs->cs_zc, cs->cs_creg);
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}
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@ -969,6 +1043,81 @@ register struct termios *t;
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return (0);
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}
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/*
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* search for the best matching baudrate
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*/
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static int
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zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst)
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int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst;
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{
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int bestdiff, bestbps, source;
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unit = (unit & 1) << 2;
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for (source = 0; source < 4; ++source) {
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long freq = zs_frequencies[unit + source];
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int diff, bps, div, clkm, brgm, tcon;
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switch (source) {
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case 0: /* BRgen, PCLK */
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brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK;
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break;
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case 1: /* BRgen, RTxC */
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brgm = ZSWR14_BAUD_ENA;
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break;
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case 2: /* RTxC */
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clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC;
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break;
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case 3: /* TRxC */
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clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC;
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break;
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}
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switch (source) {
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case 0:
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case 1:
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div = ZSWR4_CLK_X16;
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clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD;
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tcon = BPS_TO_TCONST(freq, wanted);
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if (tcon < 0)
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tcon = 0;
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bps = TCONST_TO_BPS(freq, tcon);
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break;
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case 2:
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case 3:
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{ int b1 = freq / 16, d1 = abs(b1 - wanted);
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int b2 = freq / 32, d2 = abs(b2 - wanted);
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int b3 = freq / 64, d3 = abs(b3 - wanted);
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if (d1 < d2 && d1 < d3) {
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div = ZSWR4_CLK_X16;
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bps = b1;
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} else if (d2 < d3 && d2 < d1) {
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div = ZSWR4_CLK_X32;
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bps = b2;
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} else {
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div = ZSWR4_CLK_X64;
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bps = b3;
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}
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brgm = tcon = 0;
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break;
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}
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}
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diff = abs(bps - wanted);
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if (!source || diff < bestdiff) {
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*divisor = div;
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*clockmode = clkm;
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*brgenmode = brgm;
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*timeconst = tcon;
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bestbps = bps;
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bestdiff = diff;
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if (diff == 0)
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break;
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}
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}
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/* Allow deviations upto 5% */
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if (20 * bestdiff > wanted)
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return -1;
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return bestbps;
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}
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/*
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* Raise or lower modem control (DTR/RTS) signals. If a character is
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* in transmission, the change is deferred.
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