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Set DCR_TFT[01] and DCR_RFT[01] bits of DCR register for TX/RX thresholds 

in each MD attachment since optimized values could be machine dependent.
This commit is contained in:
tsutsui 2007-06-08 17:08:46 +00:00
parent 7df023a2e5
commit d851aeff1e
2 changed files with 12 additions and 10 deletions
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11
sys/arch/arc/jazz/if_sn_jazzio.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_sn_jazzio.c,v 1.7 2005/12/11 12:16:39 christos Exp $ */
/* $NetBSD: if_sn_jazzio.c,v 1.8 2007/06/08 17:08:46 tsutsui Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_sn_jazzio.c,v 1.7 2005/12/11 12:16:39 christos Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_sn_jazzio.c,v 1.8 2007/06/08 17:08:46 tsutsui Exp $");
#include "bpfilter.h"
@ -125,8 +125,13 @@ sonic_jazzio_attach(struct device *parent, struct device *self, void *aux)
* - Latched bug retry
* - Synchronous bus (memory cycle 2 clocks)
* - 0 wait states added (WC0,WC1 == 0,0)
* - 4 byte Rx DMA threshold (RFT0,RFT1 == 0,0)
* - 28 byte Tx DMA threshold (TFT0,TFT1 == 1,1)
* XXX There was a comment
* "XXX RFT & TFT according to MIPS manual"
* in old MD sys/arch/arc/dev/if_sn.c in Attic.
*/
sc->sc_dcr = DCR_LBR | DCR_SBUS;
sc->sc_dcr = DCR_LBR | DCR_SBUS | DCR_TFT0 | DCR_TFT1;
sc->sc_dcr2 = 0;
/* Hook up our interrupt handler. */

11
sys/dev/ic/dp83932.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dp83932.c,v 1.16 2007/06/02 10:48:24 tsutsui Exp $ */
/* $NetBSD: dp83932.c,v 1.17 2007/06/08 17:08:46 tsutsui Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: dp83932.c,v 1.16 2007/06/02 10:48:24 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: dp83932.c,v 1.17 2007/06/08 17:08:46 tsutsui Exp $");
#include "bpfilter.h"
@ -910,12 +910,9 @@ sonic_init(struct ifnet *ifp)
* Bring the SONIC into reset state, and program the DCR.
*
* Note: We don't bother optimizing the transmit and receive
* thresholds, here. We just use the most conservative values:
*
* - Rx: 4 bytes (RFT0,RFT0 == 0,0)
* - Tx: 28 bytes (TFT0,TFT1 == 1,1)
* thresholds, here. TFT/RFT values should be set in MD attachments.
*/
reg = sc->sc_dcr | DCR_TFT0 | DCR_TFT1;
reg = sc->sc_dcr;
if (sc->sc_32bit)
reg |= DCR_DW;
CSR_WRITE(sc, SONIC_CR, CR_RST);