diff --git a/sys/arch/evbppc/walnut/machdep.c b/sys/arch/evbppc/walnut/machdep.c
index 433b67265fff..e982dd22cb7f 100644
--- a/sys/arch/evbppc/walnut/machdep.c
+++ b/sys/arch/evbppc/walnut/machdep.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.29 2006/07/13 07:36:04 simonb Exp $	*/
+/*	$NetBSD: machdep.c,v 1.30 2006/10/16 18:14:37 kiyohara Exp $	*/
 
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -67,7 +67,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.29 2006/07/13 07:36:04 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.30 2006/10/16 18:14:37 kiyohara Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_ddb.h"
@@ -115,6 +115,9 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.29 2006/07/13 07:36:04 simonb Exp $");
 #include <ddb/db_extern.h>
 #endif
 
+
+#define TLB_PG_SIZE 	(16*1024*1024)
+
 /*
  * Global variables used here and there
  */
@@ -171,6 +174,7 @@ initppc(u_int startkernel, u_int endkernel, char *args, void *info_block)
 #ifdef IPKDB
 	extern int ipkdblow, ipkdbsize;
 #endif
+	vaddr_t va;
 	int exc, dbcr0;
 	struct cpu_info * const ci = curcpu();
 
@@ -191,6 +195,13 @@ initppc(u_int startkernel, u_int endkernel, char *args, void *info_block)
 	availmemr[0].start = startkernel; 
 	availmemr[0].size = board_data.mem_size - availmemr[0].start;
 
+	/* Linear map whole physmem */
+	for (va = 0; va < board_data.mem_size; va += TLB_PG_SIZE)
+		ppc4xx_tlb_reserve(va, va, TLB_PG_SIZE, TLB_EX);
+
+	/* Map console just after RAM */
+	ppc4xx_tlb_reserve(0xef000000, va, TLB_PG_SIZE, TLB_I | TLB_G);
+
 	/*
 	 * Initialize lwp0 and current pcb and pmap pointers.
 	 */
diff --git a/sys/arch/evbppc/walnut/walnut_start.S b/sys/arch/evbppc/walnut/walnut_start.S
index 14201a814fc9..bba1724588be 100644
--- a/sys/arch/evbppc/walnut/walnut_start.S
+++ b/sys/arch/evbppc/walnut/walnut_start.S
@@ -1,4 +1,4 @@
-/*	$NetBSD: walnut_start.S,v 1.13 2006/06/30 17:54:51 freza Exp $	*/
+/*	$NetBSD: walnut_start.S,v 1.14 2006/10/16 18:14:37 kiyohara Exp $	*/
 /*	$OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $	*/
 
 /*
@@ -192,59 +192,11 @@ __start_cpu0:
 	stw	%r8,0(%r7)
 #endif
 
-	/*
-	 * Set up TLB entry to cover kernel addresses.
-	 *
-	 * XXX: Skip TLB 0 for now, due to unresolved TLB 0 replacement
-	 *	and hard hangs
-	 */
-	li	%r0,1
+	/* Set kernel MMU context. */
+	li	%r0,KERNEL_PID
 	mtpid	%r0
 	sync
 
-	li	%r0,0
-#ifdef PPC_4XX_NOCACHE
-	li	%r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
-#else
-	li	%r4,TLB_EX|TLB_WR /* |TLB_W */
-#endif
-        li	%r3,TLB_VALID|TLB_PG_16M
-        tlbwe	%r4,%r0,1		/* Load the data(Low) portion of the entry */
-        tlbwe	%r3,%r0,0		/* Load the tag(High) portion of the entry */
-
-#if 1
-	/* Damn. Have to be able to access all real memory.... Hardcode for 32M for now. */
-	li	%r0,1
-	lis	%r4,0x01000000@h
-	ori	%r3,%r4,0
-#ifdef PPC_4XX_NOCACHE
-	addi	%r4,%r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
-#else
-	addi	%r4,%r4,TLB_EX|TLB_WR /* |TLB_W */
-#endif
-	addi	%r3,%r3,TLB_VALID|TLB_PG_16M
-	tlbwe	%r4,%r0,1		/* Load the data(Low) portion of the entry */
-	tlbwe	%r3,%r0,0		/* Load the tag(High) portion of the entry */
-#endif
-
-	/* set up a TLB mapping to cover uart0 */
-	lis	%r3,0xef000000@h	/* Load the virtual address */
-	ori	%r4,%r3,0		/* Load the physical address */
-
-	clrrwi	%r4,%r4,10		/* Mask off the real page number */
-	/* write, execute, cache inhibit, guarded */
-	ori	%r4,%r4,(TLB_WR|TLB_EX|TLB_I|TLB_G)
-
-	clrrwi	%r3,%r3,10		/* Mask off the effective page number */
-	ori	%r3,%r3,(TLB_VALID|TLB_PG_16M)
-
-	li	%r0,2
-
-	tlbwe	%r4,%r0,1		/* Load the data portion of the entry */
-	tlbwe	%r3,%r0,0		/* Load the tag portion of the entry */
-
-	/* END of TLB setup */
-
 	INIT_CPUINFO(8,1,9,0)
 	mr	%r4,%r8
 
diff --git a/sys/arch/powerpc/ibm4xx/openbios/locore.S b/sys/arch/powerpc/ibm4xx/openbios/locore.S
index a51c7a9a6c2f..1d27c8bdf253 100644
--- a/sys/arch/powerpc/ibm4xx/openbios/locore.S
+++ b/sys/arch/powerpc/ibm4xx/openbios/locore.S
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.S,v 1.2 2005/12/11 12:18:43 christos Exp $	*/
+/*	$NetBSD: locore.S,v 1.3 2006/10/16 18:14:37 kiyohara Exp $	*/
 /*	$OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $	*/
 
 /*
@@ -210,59 +210,11 @@ __start_cpu0:
 	stw	%r8,0(%r7)
 #endif
 
-	/*
-	 * Set up TLB entry to cover kernel addresses.
-	 *
-	 * XXX: Skip TLB 0 for now, due to unresolved TLB 0 replacement
-	 *	and hard hangs
-	 */
-	li	%r0,1
+	/* Set kernel MMU context. */
+	li	%r0,KERNEL_PID
 	mtpid	%r0
 	sync
 
-	li	%r0,0
-#ifdef PPC_4XX_NOCACHE
-	li	%r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
-#else
-	li	%r4,TLB_EX|TLB_WR /* |TLB_W */
-#endif
-        li	%r3,TLB_VALID|TLB_PG_16M
-        tlbwe	%r4,%r0,1		/* Load the data(Low) portion of the entry */
-        tlbwe	%r3,%r0,0		/* Load the tag(High) portion of the entry */
-
-#if 1
-	/* Damn. Have to be able to access all real memory.... Hardcode for 32M for now. */
-	li	%r0,1
-	lis	%r4,0x01000000@h
-	ori	%r3,%r4,0
-#ifdef PPC_4XX_NOCACHE
-	addi	%r4,%r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
-#else
-	addi	%r4,%r4,TLB_EX|TLB_WR /* |TLB_W */
-#endif
-	addi	%r3,%r3,TLB_VALID|TLB_PG_16M
-	tlbwe	%r4,%r0,1		/* Load the data(Low) portion of the entry */
-	tlbwe	%r3,%r0,0		/* Load the tag(High) portion of the entry */
-#endif
-
-	/* set up a TLB mapping to cover uart0 */
-	lis	%r3,0xef000000@h	/* Load the virtual address */
-	ori	%r4,%r3,0		/* Load the physical address */
-
-	clrrwi	%r4,%r4,10		/* Mask off the real page number */
-	/* write, execute, cache inhibit, guarded */
-	ori	%r4,%r4,(TLB_WR|TLB_EX|TLB_I|TLB_G)
-
-	clrrwi	%r3,%r3,10		/* Mask off the effective page number */
-	ori	%r3,%r3,(TLB_VALID|TLB_PG_16M)
-
-	li	%r0,2
-
-	tlbwe	%r4,%r0,1		/* Load the data portion of the entry */
-	tlbwe	%r3,%r0,0		/* Load the tag portion of the entry */
-
-	/* END of TLB setup */
-
 	INIT_CPUINFO(8,1,9,0)
 	mr	%r4,%r8