Map the recursive slot and page table pages as non-executable on Xen. Same
as normal x86.
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parent
bbe119dec3
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d7d5f3349a
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@ -1,4 +1,4 @@
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/* $NetBSD: x86_xpmap.c,v 1.57 2016/08/02 14:21:53 maxv Exp $ */
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/* $NetBSD: x86_xpmap.c,v 1.58 2016/08/03 11:51:18 maxv Exp $ */
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/*
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* Copyright (c) 2006 Mathieu Ropert <mro@adviseo.fr>
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@ -69,7 +69,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.57 2016/08/02 14:21:53 maxv Exp $");
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__KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.58 2016/08/03 11:51:18 maxv Exp $");
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#include "opt_xen.h"
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#include "opt_ddb.h"
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@ -918,7 +918,7 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd,
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pte[pl1_pi(page)] |= PG_k | PG_V;
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if (page < (vaddr_t)&__rodata_start) {
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/* Map kernel text RX. */
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/* Map the kernel text RX. */
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pte[pl1_pi(page)] |= PG_RO;
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} else if (page >= (vaddr_t)&__rodata_start &&
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page < (vaddr_t)&__data_start) {
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@ -930,12 +930,12 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd,
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pte[pl1_pi(page)] |= PG_RW | pg_nx;
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} else if (page >= old_pgd &&
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page < old_pgd + (old_count * PAGE_SIZE)) {
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/* map old page tables RO */
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pte[pl1_pi(page)] |= PG_RO;
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/* Map the old page tables R. */
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pte[pl1_pi(page)] |= PG_RO | pg_nx;
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} else if (page >= new_pgd &&
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page < new_pgd + ((new_count + l2_4_count) * PAGE_SIZE)) {
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/* map new page tables RO */
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pte[pl1_pi(page)] |= PG_RO;
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/* Map the new page tables R. */
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pte[pl1_pi(page)] |= PG_RO | pg_nx;
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#ifdef i386
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} else if (page == (vaddr_t)tmpgdt) {
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/*
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@ -1028,15 +1028,19 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd,
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xpq_queue_pin_l2_table(xpmap_ptom_masked(addr));
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#endif
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#else /* PAE */
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/* recursive entry in higher-level per-cpu PD and pmap_kernel() */
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bt_pgd[PDIR_SLOT_PTE] = xpmap_ptom_masked((paddr_t)bt_pgd - KERNBASE) | PG_k | PG_V;
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/* Recursive entry in pmap_kernel(). */
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bt_pgd[PDIR_SLOT_PTE] = xpmap_ptom_masked((paddr_t)bt_pgd - KERNBASE)
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| PG_k | PG_RO | PG_V | pg_nx;
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#ifdef __x86_64__
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bt_cpu_pgd[PDIR_SLOT_PTE] =
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xpmap_ptom_masked((paddr_t)bt_cpu_pgd - KERNBASE) | PG_k | PG_V;
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#endif /* __x86_64__ */
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/* Recursive entry in higher-level per-cpu PD. */
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bt_cpu_pgd[PDIR_SLOT_PTE] = xpmap_ptom_masked((paddr_t)bt_cpu_pgd - KERNBASE)
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| PG_k | PG_RO | PG_V | pg_nx;
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#endif
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__PRINTK(("bt_pgd[PDIR_SLOT_PTE] va %#" PRIxVADDR " pa %#" PRIxPADDR
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" entry %#" PRIxPADDR "\n", new_pgd, (paddr_t)new_pgd - KERNBASE,
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bt_pgd[PDIR_SLOT_PTE]));
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/* Mark tables RO */
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xen_bt_set_readonly((vaddr_t) pde);
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#endif
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@ -1046,6 +1050,7 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd,
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#if PTP_LEVELS > 3
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xen_bt_set_readonly(new_pgd);
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#endif
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/* Pin the PGD */
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__PRINTK(("pin PGD: %"PRIxVADDR"\n", new_pgd - KERNBASE));
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#ifdef __x86_64__
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