Cleanup rambling codes.
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6944e3acfe
commit
d782dfb5f7
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3100.c,v 1.17 1999/11/25 01:40:22 simonb Exp $ */
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/* $NetBSD: dec_3100.c,v 1.18 1999/12/03 03:06:11 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -132,8 +132,7 @@ dec_3100_init()
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splvec.splstatclock = MIPS_SPL_0_1_2_3;
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/* calibrate cpu_mhz value */
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mc_cpuspeed(
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(void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_3);
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mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_3);
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sprintf(cpu_model, "DECstation %d100 (PMAX)", cpu_mhz < 15 ? 3 : 2);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3max.c,v 1.17 1999/11/25 01:40:22 simonb Exp $ */
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/* $NetBSD: dec_3max.c,v 1.18 1999/12/03 03:06:11 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.17 1999/11/25 01:40:22 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.18 1999/12/03 03:06:11 nisimura Exp $");
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#include <sys/types.h>
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#include <sys/systm.h>
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@ -138,8 +138,7 @@ dec_3max_init()
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splvec.splstatclock = MIPS_SPL_0_1;
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/* calibrate cpu_mhz value */
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mc_cpuspeed(
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(void *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK), MIPS_INT_MASK_1);
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mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK), MIPS_INT_MASK_1);
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/*
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* Enable ECC memory correction, turn off LEDs, and
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3maxplus.c,v 1.29 1999/11/25 01:40:22 simonb Exp $ */
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/* $NetBSD: dec_3maxplus.c,v 1.30 1999/12/03 03:06:11 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.29 1999/11/25 01:40:22 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.30 1999/12/03 03:06:11 nisimura Exp $");
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#include <sys/types.h>
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#include <sys/systm.h>
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@ -157,7 +157,7 @@ dec_3maxplus_init()
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splvec.splstatclock = MIPS_SPL_0_1;
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/* calibrate cpu_mhz value */
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mc_cpuspeed((void *)(ioasic_base+IOASIC_SLOT_8_START), MIPS_INT_MASK_1);
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mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1);
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*(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
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*(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3min.c,v 1.28 1999/12/01 08:35:27 nisimura Exp $ */
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/* $NetBSD: dec_3min.c,v 1.29 1999/12/03 03:06:11 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.28 1999/12/01 08:35:27 nisimura Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.29 1999/12/03 03:06:11 nisimura Exp $");
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#include <sys/types.h>
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@ -166,7 +166,7 @@ dec_3min_init()
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/* enable posting of MIPS_INT_MASK_3 to CAUSE register */
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*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK;
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/* calibrate cpu_mhz value */
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mc_cpuspeed((void *)(ioasic_base+IOASIC_SLOT_8_START), MIPS_INT_MASK_3);
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mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3);
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*(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
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*(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_5100.c,v 1.13 1999/11/25 01:40:22 simonb Exp $ */
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/* $NetBSD: dec_5100.c,v 1.14 1999/12/03 03:06:11 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -103,8 +103,7 @@ dec_5100_init()
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splvec.splstatclock = MIPS_SPL_0_1_2;
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/* calibrate cpu_mhz value */
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mc_cpuspeed(
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(void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_2);
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mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_2);
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sprintf(cpu_model, "DECsystem 5100 (MIPSMATE)");
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_maxine.c,v 1.20 1999/11/28 08:29:00 simonb Exp $ */
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/* $NetBSD: dec_maxine.c,v 1.21 1999/12/03 03:06:11 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.20 1999/11/28 08:29:00 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.21 1999/12/03 03:06:11 nisimura Exp $");
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#include <sys/types.h>
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#include <sys/systm.h>
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@ -154,7 +154,7 @@ dec_maxine_init()
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splvec.splstatclock = MIPS_SPL_0_1_3;
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/* calibrate cpu_mhz value */
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mc_cpuspeed((void *)(ioasic_base+IOASIC_SLOT_8_START), MIPS_INT_MASK_1);
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mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1);
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*(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
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*(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
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