From d6d9fbe24018cdfba824e5011d0c23a6b7654bbb Mon Sep 17 00:00:00 2001 From: thorpej Date: Wed, 17 Nov 1999 01:21:20 +0000 Subject: [PATCH] Interrupt router drivers from UCHIYAMA Yasushi's PCI BIOS patches, cleaned up and reworked a bit be me. --- sys/arch/i386/pci/opti82c558.c | 248 +++++++++++++++++++++++++ sys/arch/i386/pci/opti82c558reg.h | 65 +++++++ sys/arch/i386/pci/opti82c700.c | 290 ++++++++++++++++++++++++++++++ sys/arch/i386/pci/opti82c700reg.h | 71 ++++++++ sys/arch/i386/pci/piix.c | 237 ++++++++++++++++++++++++ sys/arch/i386/pci/piixreg.h | 55 ++++++ sys/arch/i386/pci/piixvar.h | 77 ++++++++ sys/arch/i386/pci/sis85c503.c | 180 +++++++++++++++++++ sys/arch/i386/pci/sis85c503reg.h | 52 ++++++ sys/arch/i386/pci/via82c586.c | 270 ++++++++++++++++++++++++++++ sys/arch/i386/pci/via82c586reg.h | 62 +++++++ 11 files changed, 1607 insertions(+) create mode 100644 sys/arch/i386/pci/opti82c558.c create mode 100644 sys/arch/i386/pci/opti82c558reg.h create mode 100644 sys/arch/i386/pci/opti82c700.c create mode 100644 sys/arch/i386/pci/opti82c700reg.h create mode 100644 sys/arch/i386/pci/piix.c create mode 100644 sys/arch/i386/pci/piixreg.h create mode 100644 sys/arch/i386/pci/piixvar.h create mode 100644 sys/arch/i386/pci/sis85c503.c create mode 100644 sys/arch/i386/pci/sis85c503reg.h create mode 100644 sys/arch/i386/pci/via82c586.c create mode 100644 sys/arch/i386/pci/via82c586reg.h diff --git a/sys/arch/i386/pci/opti82c558.c b/sys/arch/i386/pci/opti82c558.c new file mode 100644 index 000000000000..45a4050177c1 --- /dev/null +++ b/sys/arch/i386/pci/opti82c558.c @@ -0,0 +1,248 @@ +/* $NetBSD: opti82c558.c,v 1.1 1999/11/17 01:21:20 thorpej Exp $ */ + +/*- + * Copyright (c) 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Support for the Opti 82c558 PCI-ISA bridge interrupt controller. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include + +int opti82c558_getclink __P((pciintr_icu_handle_t, int, int *)); +int opti82c558_get_intr __P((pciintr_icu_handle_t, int, int *)); +int opti82c558_set_intr __P((pciintr_icu_handle_t, int, int)); +int opti82c558_get_trigger __P((pciintr_icu_handle_t, int, int *)); +int opti82c558_set_trigger __P((pciintr_icu_handle_t, int, int)); + +const struct pciintr_icu opti82c558_pci_icu = { + opti82c558_getclink, + opti82c558_get_intr, + opti82c558_set_intr, + opti82c558_get_trigger, + opti82c558_set_trigger, +}; + +struct opti82c558_handle { + pci_chipset_tag_t ph_pc; + pcitag_t ph_tag; +}; + +static const int viper_pirq_decode[] = { + -1, 5, 9, 10, 11, 12, 14, 15 +}; + +static const int viper_pirq_encode[] = { + -1, /* 0 */ + -1, /* 1 */ + -1, /* 2 */ + -1, /* 3 */ + -1, /* 4 */ + VIPER_PIRQ_5, /* 5 */ + -1, /* 6 */ + -1, /* 7 */ + -1, /* 8 */ + VIPER_PIRQ_9, /* 9 */ + VIPER_PIRQ_10, /* 10 */ + VIPER_PIRQ_11, /* 11 */ + VIPER_PIRQ_12, /* 12 */ + -1, /* 13 */ + VIPER_PIRQ_14, /* 14 */ + VIPER_PIRQ_15, /* 15 */ +}; + +int +opti82c558_init(pc, iot, tag, ptagp, phandp) + pci_chipset_tag_t pc; + bus_space_tag_t iot; + pcitag_t tag; + pciintr_icu_tag_t *ptagp; + pciintr_icu_handle_t *phandp; +{ + struct opti82c558_handle *ph; + + ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); + if (ph == NULL) + return (1); + + ph->ph_pc = pc; + ph->ph_tag = tag; + + *ptagp = &opti82c558_pci_icu; + *phandp = ph; + return (0); +} + +int +opti82c558_getclink(v, link, clinkp) + pciintr_icu_handle_t v; + int link, *clinkp; +{ + + if (VIPER_LEGAL_LINK(link - 1)) { + *clinkp = link - 1; + return (0); + } + + return (1); +} + +int +opti82c558_get_intr(v, clink, irqp) + pciintr_icu_handle_t v; + int clink, *irqp; +{ + struct opti82c558_handle *ph = v; + pcireg_t reg; + int val; + + if (VIPER_LEGAL_LINK(clink) == 0) + return (1); + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); + val = VIPER_PIRQ(reg, clink); + *irqp = (val == VIPER_PIRQ_NONE) ? 0xff : viper_pirq_decode[val]; + + return (0); +} + +int +opti82c558_set_intr(v, clink, irq) + pciintr_icu_handle_t v; + int clink, irq; +{ + struct opti82c558_handle *ph = v; + int shift; + pcireg_t reg; + + if (VIPER_LEGAL_LINK(clink) == 0 || VIPER_LEGAL_IRQ(irq) == 0) + return (1); + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); + shift = VIPER_PIRQ_SELECT_SHIFT * clink; + reg &= ~(VIPER_PIRQ_SELECT_MASK << shift); + reg |= (viper_pirq_encode[irq] << shift); + pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg); + + return (0); +} + +int +opti82c558_get_trigger(v, irq, triggerp) + pciintr_icu_handle_t v; + int irq, *triggerp; +{ + struct opti82c558_handle *ph = v; + pcireg_t reg; + + if (VIPER_LEGAL_IRQ(irq) == 0) { + /* ISA IRQ? */ + *triggerp = IST_EDGE; + return (0); + } + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); + if ((reg >> (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq])) & 1) + *triggerp = IST_LEVEL; + else + *triggerp = IST_EDGE; + + return (0); +} + +int +opti82c558_set_trigger(v, irq, trigger) + pciintr_icu_handle_t v; + int irq, trigger; +{ + struct opti82c558_handle *ph = v; + int shift; + pcireg_t reg; + + if (VIPER_LEGAL_IRQ(irq) == 0) { + /* ISA IRQ? */ + return ((trigger != IST_LEVEL) ? 0 : 1); + } + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); + shift = (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq]); + if (trigger == IST_LEVEL) + reg |= (1 << shift); + else + reg &= ~(1 << shift); + pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg); + + return (0); +} diff --git a/sys/arch/i386/pci/opti82c558reg.h b/sys/arch/i386/pci/opti82c558reg.h new file mode 100644 index 000000000000..990a1b064edd --- /dev/null +++ b/sys/arch/i386/pci/opti82c558reg.h @@ -0,0 +1,65 @@ +/* $NetBSD: opti82c558reg.h,v 1.1 1999/11/17 01:21:20 thorpej Exp $ */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Register definitions for the Opti 82c558 PCI-ISA bridge interrupt + * controller. + */ + +/* + * PCI IRQ Select Register + */ + +#define VIPER_CFG_PIRQ 0x40 /* PCI configuration space */ + +/* + * Trigger setting: + * + * [1:7]=>5,9,10,11,12,14,15 Edge = 0 Level = 1 + */ +#define VIPER_CFG_TRIGGER_SHIFT 16 + +#define VIPER_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3) + +#define VIPER_PIRQ_MASK 0xde20 +#define VIPER_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \ + ((1 << (irq)) & VIPER_PIRQ_MASK) != 0) + +#define VIPER_PIRQ_NONE 0 +#define VIPER_PIRQ_5 1 +#define VIPER_PIRQ_9 2 +#define VIPER_PIRQ_10 3 +#define VIPER_PIRQ_11 4 +#define VIPER_PIRQ_12 5 +#define VIPER_PIRQ_14 6 +#define VIPER_PIRQ_15 7 + +#define VIPER_PIRQ_SELECT_MASK 0x07 +#define VIPER_PIRQ_SELECT_SHIFT 3 + +#define VIPER_PIRQ(reg, x) (((reg) >> ((x) * VIPER_PIRQ_SELECT_SHIFT)) \ + & VIPER_PIRQ_SELECT_MASK) diff --git a/sys/arch/i386/pci/opti82c700.c b/sys/arch/i386/pci/opti82c700.c new file mode 100644 index 000000000000..176f48bd299a --- /dev/null +++ b/sys/arch/i386/pci/opti82c700.c @@ -0,0 +1,290 @@ +/* $NetBSD: opti82c700.c,v 1.1 1999/11/17 01:21:20 thorpej Exp $ */ + +/*- + * Copyright (c) 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Support for the Opti 82c700 PCI-ISA bridge interrupt controller. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include + +int opti82c700_getclink __P((pciintr_icu_handle_t, int, int *)); +int opti82c700_get_intr __P((pciintr_icu_handle_t, int, int *)); +int opti82c700_set_intr __P((pciintr_icu_handle_t, int, int)); +int opti82c700_get_trigger __P((pciintr_icu_handle_t, int, int *)); +int opti82c700_set_trigger __P((pciintr_icu_handle_t, int, int)); + +const struct pciintr_icu opti82c700_pci_icu = { + opti82c700_getclink, + opti82c700_get_intr, + opti82c700_set_intr, + opti82c700_get_trigger, + opti82c700_set_trigger, +}; + +struct opti82c700_handle { + pci_chipset_tag_t ph_pc; + pcitag_t ph_tag; +}; + +int opti82c700_addr __P((int, int *, int *)); + +int +opti82c700_init(pc, iot, tag, ptagp, phandp) + pci_chipset_tag_t pc; + bus_space_tag_t iot; + pcitag_t tag; + pciintr_icu_tag_t *ptagp; + pciintr_icu_handle_t *phandp; +{ + struct opti82c700_handle *ph; + + ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); + if (ph == NULL) + return (1); + + ph->ph_pc = pc; + ph->ph_tag = tag; + + *ptagp = &opti82c700_pci_icu; + *phandp = ph; + return (0); +} + +int +opti82c700_addr(link, addrofs, ofs) + int link, *addrofs, *ofs; +{ + int regofs, src; + + regofs = FIRESTAR_PIR_REGOFS(link); + src = FIRESTAR_PIR_SELECTSRC(link); + + switch (src) { + case FIRESTAR_PIR_SELECT_NONE: + return (1); + + case FIRESTAR_PIR_SELECT_IRQ: + if (regofs < 0 || regofs > 7) + return (1); + *addrofs = FIRESTAR_CFG_INTR_IRQ + (regofs >> 2); + *ofs = (regofs & 3) << 3; + break; + + case FIRESTAR_PIR_SELECT_PIRQ: + case FIRESTAR_PIR_SELECT_BRIDGE: + if (regofs < 0 || regofs > 3) + return (1); + *addrofs = FIRESTAR_CFG_INTR_PIRQ; + *ofs = regofs << 2; + break; + + default: + return (1); + } + + return (0); +} + +int +opti82c700_getclink(v, link, clinkp) + pciintr_icu_handle_t v; + int link, *clinkp; +{ + + if (FIRESTAR_LEGAL_LINK(link)) { + *clinkp = link; + return (0); + } + + return (1); +} + +int +opti82c700_get_intr(v, clink, irqp) + pciintr_icu_handle_t v; + int clink, *irqp; +{ + struct opti82c700_handle *ph = v; + pcireg_t reg; + int val, addrofs, ofs; + + if (FIRESTAR_LEGAL_LINK(clink) == 0) + return (1); + + if (opti82c700_addr(clink, &addrofs, &ofs)) + return (1); + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs); + val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK; + *irqp = (val == FIRESTAR_PIRQ_NONE) ? 0xff : val; + + return (0); +} + +int +opti82c700_set_intr(v, clink, irq) + pciintr_icu_handle_t v; + int clink, irq; +{ + struct opti82c700_handle *ph = v; + int addrofs, ofs; + pcireg_t reg; + + if (FIRESTAR_LEGAL_LINK(clink) == 0 || FIRESTAR_LEGAL_IRQ(irq) == 0) + return (1); + + if (opti82c700_addr(clink, &addrofs, &ofs)) + return (1); + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs); + reg &= ~(FIRESTAR_CFG_PIRQ_MASK << ofs); + reg |= (irq << ofs); + pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg); + + return (0); +} + +int +opti82c700_get_trigger(v, irq, triggerp) + pciintr_icu_handle_t v; + int irq, *triggerp; +{ + struct opti82c700_handle *ph = v; + int i, val, addrofs, ofs; + pcireg_t reg; + + if (FIRESTAR_LEGAL_IRQ(irq) == 0) { + /* ISA IRQ? */ + *triggerp = IST_EDGE; + return (0); + } + + /* + * Search PCIDV1 registers. + */ + for (i = 0; i < 8; i++) { + opti82c700_addr(FIRESTAR_PIR_MAKELINK(FIRESTAR_PIR_SELECT_IRQ, + i), &addrofs, &ofs); + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs); + val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK; + if (val != irq) + continue; + val = ((reg >> ofs) >> FIRESTAR_TRIGGER_SHIFT) & + FIRESTAR_TRIGGER_MASK; + *triggerp = val ? IST_LEVEL : IST_EDGE; + return (0); + } + + return (1); +} + +int +opti82c700_set_trigger(v, irq, trigger) + pciintr_icu_handle_t v; + int irq, trigger; +{ + struct opti82c700_handle *ph = v; + int i, val, addrofs, ofs; + pcireg_t reg; + + if (FIRESTAR_LEGAL_IRQ(irq) == 0) { + /* ISA IRQ? */ + return ((trigger != IST_LEVEL) ? 0 : 1); + } + + /* + * Search PCIDV1 registers. + */ + for (i = 0; i < 8; i++) { + opti82c700_addr(FIRESTAR_PIR_MAKELINK(FIRESTAR_PIR_SELECT_IRQ, + i), &addrofs, &ofs); + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs); + val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK; + if (val != irq) + continue; + if (trigger == IST_LEVEL) + reg |= (FIRESTAR_TRIGGER_MASK << + (FIRESTAR_TRIGGER_SHIFT + ofs)); + else + reg &= ~(FIRESTAR_TRIGGER_MASK << + (FIRESTAR_TRIGGER_SHIFT + ofs)); + pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg); + return (0); + } + + return (1); +} diff --git a/sys/arch/i386/pci/opti82c700reg.h b/sys/arch/i386/pci/opti82c700reg.h new file mode 100644 index 000000000000..97edba7b3f87 --- /dev/null +++ b/sys/arch/i386/pci/opti82c700reg.h @@ -0,0 +1,71 @@ +/* $NetBSD: opti82c700reg.h,v 1.1 1999/11/17 01:21:20 thorpej Exp $ */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Register definitions for the Opti 82c700 PCI-ISA bridge interrupt + * controller. + */ + +#define FIRESTAR_CFG_INTR_IRQ 0xb0 /* PCI configuration space */ +#define FIRESTAR_CFG_INTR_PIRQ 0xb8 /* PCI configuration space */ + +#define FIRESTAR_PIRQ_NONE 0 +#define FIRESTAR_PIRQ_MIN FIRESTAR_CFG_INTR_IRQ +#define FIRESTAR_PIRQ_MAX (FIRESTAR_CFG_INTR_PIRQ + 1) +#define FIRESTAR_LEGAL_LINK(link) ((link) >= FIRESTAR_PIRQ_MIN && \ + (link) <= FIRESTAR_PIRQ_MAX) + +#define FIRESTAR_PIRQ_MASK 0xdffa +#define FIRESTAR_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \ + ((1 << (irq)) & FIRESTAR_PIRQ_MASK) != 0) + +#define FIRESTAR_CFG_PIRQ_MASK 0x0f + +#define FIRESTAR_TRIGGER_MASK 0x01 +#define FIRESTAR_TRIGGER_SHIFT 4 + +/* + * Opti's suggested Link values. + */ +#define FIRESTAR_PIR_REGOFS_MASK 0x07 +#define FIRESTAR_PIR_REGOFS_SHIFT 4 +#define FIRESTAR_PIR_REGOFS(link) \ + (((link) >> FIRESTAR_PIR_REGOFS_SHIFT) & FIRESTAR_PIR_REGOFS_MASK) + +#define FIRESTAR_PIR_SELECTSRC_MASK 0x07 +#define FIRESTAR_PIR_SELECTSRC_SHIFT 0 +#define FIRESTAR_PIR_SELECTSRC(link) \ + (((link) >> FIRESTAR_PIR_SELECTSRC_SHIFT) & FIRESTAR_PIR_SELECTSRC_MASK) + +#define FIRESTAR_PIR_SELECT_NONE 0 +#define FIRESTAR_PIR_SELECT_IRQ 1 +#define FIRESTAR_PIR_SELECT_PIRQ 2 +#define FIRESTAR_PIR_SELECT_BRIDGE 3 + +#define FIRESTAR_PIR_MAKELINK(src, ofs) \ + (((src) << FIRESTAR_PIR_SELECTSRC_SHIFT) | \ + ((ofs) << FIRESTAR_PIR_REGOFS_SHIFT)) diff --git a/sys/arch/i386/pci/piix.c b/sys/arch/i386/pci/piix.c new file mode 100644 index 000000000000..961a4580d0e9 --- /dev/null +++ b/sys/arch/i386/pci/piix.c @@ -0,0 +1,237 @@ +/* $NetBSD: piix.c,v 1.1 1999/11/17 01:21:20 thorpej Exp $ */ + +/*- + * Copyright (c) 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Support for the Intel PIIX PCI-ISA bridge interrupt controller. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +int piix_getclink __P((pciintr_icu_handle_t, int, int *)); +int piix_get_intr __P((pciintr_icu_handle_t, int, int *)); +int piix_set_intr __P((pciintr_icu_handle_t, int, int)); + +const struct pciintr_icu piix_pci_icu = { + piix_getclink, + piix_get_intr, + piix_set_intr, + piix_get_trigger, + piix_set_trigger, +}; + +int +piix_init(pc, iot, tag, ptagp, phandp) + pci_chipset_tag_t pc; + bus_space_tag_t iot; + pcitag_t tag; + pciintr_icu_tag_t *ptagp; + pciintr_icu_handle_t *phandp; +{ + struct piix_handle *ph; + + ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); + if (ph == NULL) + return (1); + + ph->ph_iot = iot; + ph->ph_pc = pc; + ph->ph_tag = tag; + + if (bus_space_map(iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, + &ph->ph_elcr_ioh) != 0) { + free(ph, M_DEVBUF); + return (1); + } + + *ptagp = &piix_pci_icu; + *phandp = ph; + return (0); +} + +int +piix_getclink(v, link, clinkp) + pciintr_icu_handle_t v; + int link, *clinkp; +{ + + /* Pattern 1: simple. */ + if (PIIX_LEGAL_LINK(link - 1)) { + *clinkp = link - 1; + return (0); + } + + /* Pattern 2: configuration register offset */ + if (link >= 0x60 && link <= 0x63) { + *clinkp = link - 0x60; + return (0); + } + + return (1); +} + +int +piix_get_intr(v, clink, irqp) + pciintr_icu_handle_t v; + int clink, *irqp; +{ + struct piix_handle *ph = v; + int shift; + pcireg_t reg; + + if (PIIX_LEGAL_LINK(clink) == 0) + return (1); + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ); + shift = clink << 3; + if ((reg >> shift) & PIIX_CFG_PIRQ_NONE) + *irqp = 0xff; + else + *irqp = PIIX_PIRQ(reg, clink); + + return (0); +} + +int +piix_set_intr(v, clink, irq) + pciintr_icu_handle_t v; + int clink, irq; +{ + struct piix_handle *ph = v; + int shift; + pcireg_t reg; + + if (PIIX_LEGAL_LINK(clink) == 0 || PIIX_LEGAL_IRQ(irq) == 0) + return (1); + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ); + shift = clink << 3; + reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift); + reg |= irq << shift; + pci_conf_write(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ, reg); + + return (0); +} + +int +piix_get_trigger(v, irq, triggerp) + pciintr_icu_handle_t v; + int irq, *triggerp; +{ + struct piix_handle *ph = v; + int off, bit; + u_int8_t elcr; + + if (PIIX_LEGAL_IRQ(irq) == 0) + return (1); + + off = (irq > 7) ? 1 : 0; + bit = irq & 7; + + elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); + if (elcr & (1 << bit)) + *triggerp = IST_LEVEL; + else + *triggerp = IST_EDGE; + + return (0); +} + +int +piix_set_trigger(v, irq, trigger) + pciintr_icu_handle_t v; + int irq, trigger; +{ + struct piix_handle *ph = v; + int off, bit; + u_int8_t elcr; + + if (PIIX_LEGAL_IRQ(irq) == 0) + return (1); + + off = (irq > 7) ? 1 : 0; + bit = irq & 7; + + elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); + if (trigger == IST_LEVEL) + elcr |= (1 << bit); + else + elcr &= ~(1 << bit); + bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr); + + return (0); +} diff --git a/sys/arch/i386/pci/piixreg.h b/sys/arch/i386/pci/piixreg.h new file mode 100644 index 000000000000..c558702ec261 --- /dev/null +++ b/sys/arch/i386/pci/piixreg.h @@ -0,0 +1,55 @@ +/* $NetBSD: piixreg.h,v 1.1 1999/11/17 01:21:21 thorpej Exp $ */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Register definitions for the Intel PIIX PCI-ISA bridge interrupt controller. + */ + +/* + * PIRQ[3:0]# - PIRQ ROUTE CONTROL REGISTERS + * + * PCI Configuration registers 0x60, 0x61, 0x62, 0x63 + */ + +#define PIIX_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3) + +#define PIIX_PIRQ_MASK 0xdef8 +#define PIIX_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \ + ((1 << (irq)) & PIIX_PIRQ_MASK) != 0) + +#define PIIX_CFG_PIRQ 0x60 /* PCI configuration space */ +#define PIIX_CFG_PIRQ_NONE 0x80 +#define PIIX_CFG_PIRQ_MASK 0x0f +#define PIIX_PIRQ(reg, x) (((reg) >> ((x) << 3)) & 0xff) + +/* + * ELCR - EDGE/LEVEL CONTROL REGISTER + * + * PCI I/O registers 0x4d0, 0x4d1 + */ +#define PIIX_REG_ELCR 0x4d0 +#define PIIX_REG_ELCR_SIZE 2 diff --git a/sys/arch/i386/pci/piixvar.h b/sys/arch/i386/pci/piixvar.h new file mode 100644 index 000000000000..f5e62463a111 --- /dev/null +++ b/sys/arch/i386/pci/piixvar.h @@ -0,0 +1,77 @@ +/* $NetBSD: piixvar.h,v 1.1 1999/11/17 01:21:21 thorpej Exp $ */ + +/*- + * Copyright (c) 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Support for the Intel PIIX PCI-ISA bridge interrupt controller. + */ + +int piix_get_trigger __P((pciintr_icu_handle_t, int, int *)); +int piix_set_trigger __P((pciintr_icu_handle_t, int, int)); + +struct piix_handle { + bus_space_tag_t ph_iot; + bus_space_handle_t ph_elcr_ioh; + pci_chipset_tag_t ph_pc; + pcitag_t ph_tag; +}; diff --git a/sys/arch/i386/pci/sis85c503.c b/sys/arch/i386/pci/sis85c503.c new file mode 100644 index 000000000000..69ee38b9b3e6 --- /dev/null +++ b/sys/arch/i386/pci/sis85c503.c @@ -0,0 +1,180 @@ +/* $NetBSD: sis85c503.c,v 1.1 1999/11/17 01:21:21 thorpej Exp $ */ + +/*- + * Copyright (c) 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Support for the SiS 85c503 PCI-ISA bridge interrupt controller. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +int sis85c503_getclink __P((pciintr_icu_handle_t, int, int *)); +int sis85c503_get_intr __P((pciintr_icu_handle_t, int, int *)); +int sis85c503_set_intr __P((pciintr_icu_handle_t, int, int)); + +const struct pciintr_icu sis85c503_pci_icu = { + sis85c503_getclink, + sis85c503_get_intr, + sis85c503_set_intr, + piix_get_trigger, + piix_set_trigger, +}; + +int +sis85c503_init(pc, iot, tag, ptagp, phandp) + pci_chipset_tag_t pc; + bus_space_tag_t iot; + pcitag_t tag; + pciintr_icu_tag_t *ptagp; + pciintr_icu_handle_t *phandp; +{ + + if (piix_init(pc, iot, tag, ptagp, phandp) == 0) { + *ptagp = &sis85c503_pci_icu; + return (0); + } + + return (1); +} + +int +sis85c503_getclink(v, link, clinkp) + pciintr_icu_handle_t v; + int link, *clinkp; +{ + + /* Pattern 1: simple. */ + if (link >= 1 && link <= 4) { + *clinkp = SIS85C503_CFG_PIRQ_REGSTART + link - 1; + return (0); + } + + /* Pattern 2: configuration register offset */ + if (link >= SIS85C503_CFG_PIRQ_REGSTART && + link <= SIS85C503_CFG_PIRQ_REGEND) { + *clinkp = link; + return (0); + } + + return (1); +} + +int +sis85c503_get_intr(v, clink, irqp) + pciintr_icu_handle_t v; + int clink, *irqp; +{ + struct piix_handle *ph = v; + pcireg_t reg; + + if (SIS85C503_LEGAL_LINK(clink) == 0) + return (1); + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, + SIS85C503_CFG_PIRQ_REGOFS(clink)); + reg = SIS85C503_CFG_PIRQ_REG(reg, clink); + + if (reg & SIS85C503_CFG_PIRQ_ROUTE_DISABLE) + *irqp = 0xff; + else + *irqp = reg & SIS85C503_CFG_PIRQ_INTR_MASK; + + return (0); +} + +int +sis85c503_set_intr(v, clink, irq) + pciintr_icu_handle_t v; + int clink, irq; +{ + struct piix_handle *ph = v; + int shift; + pcireg_t reg; + + if (SIS85C503_LEGAL_LINK(clink) == 0 || SIS85C503_LEGAL_IRQ(irq) == 0) + return (1); + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, + SIS85C503_CFG_PIRQ_REGOFS(clink)); + shift = SIS85C503_CFG_PIRQ_SHIFT(clink); + reg &= ~((SIS85C503_CFG_PIRQ_ROUTE_DISABLE | + SIS85C503_CFG_PIRQ_INTR_MASK) << shift); + reg |= (irq << shift); + pci_conf_write(ph->ph_pc, ph->ph_tag, SIS85C503_CFG_PIRQ_REGOFS(clink), + reg); + + return (0); +} diff --git a/sys/arch/i386/pci/sis85c503reg.h b/sys/arch/i386/pci/sis85c503reg.h new file mode 100644 index 000000000000..cef8141c944c --- /dev/null +++ b/sys/arch/i386/pci/sis85c503reg.h @@ -0,0 +1,52 @@ +/* $NetBSD: sis85c503reg.h,v 1.1 1999/11/17 01:21:21 thorpej Exp $ */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Register definitions for the SiS 85c503 PCI-ISA bridge interrupt controller. + */ + +#define SIS85C503_CFG_PIRQ_REGSTART 0x41 /* PCI configuration space */ +#define SIS85C503_CFG_PIRQ_REGEND 0x44 + +#define SIS85C503_LEGAL_LINK(link) ((link) >= SIS85C503_CFG_PIRQ_REGSTART && \ + (link) <= SIS85C503_CFG_PIRQ_REGEND) + +#define SIS85C503_CFG_PIRQ_REGOFS(regofs) (((regofs) >> 2) << 2) +#define SIS85C503_CFG_PIRQ_SHIFT(regofs) \ + (((regofs) - SIS85C503_CFG_PIRQ_REGOFS(regofs)) << 3) + +#define SIS85C503_CFG_PIRQ_MASK 0xff +#define SIS85C503_CFG_PIRQ_INTR_MASK 0x0f + +#define SIS85C503_CFG_PIRQ_REG(reg, regofs) \ + (((reg) >> SIS85C503_CFG_PIRQ_SHIFT(regofs)) & SIS85C503_CFG_PIRQ_MASK) + +#define SIS85C503_CFG_PIRQ_ROUTE_DISABLE 0x80 + +#define SIS85C503_PIRQ_MASK 0xdef8 +#define SIS85C503_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \ + ((1 << (irq)) & SIS85C503_PIRQ_MASK) != 0) diff --git a/sys/arch/i386/pci/via82c586.c b/sys/arch/i386/pci/via82c586.c new file mode 100644 index 000000000000..5f2470eff929 --- /dev/null +++ b/sys/arch/i386/pci/via82c586.c @@ -0,0 +1,270 @@ +/* $NetBSD: via82c586.c,v 1.1 1999/11/17 01:21:21 thorpej Exp $ */ + +/*- + * Copyright (c) 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Support for the VIA 82c586 PCI-ISA bridge interrupt controller. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +int via82c586_getclink __P((pciintr_icu_handle_t, int, int *)); +int via82c586_get_intr __P((pciintr_icu_handle_t, int, int *)); +int via82c586_set_intr __P((pciintr_icu_handle_t, int, int)); +int via82c586_get_trigger __P((pciintr_icu_handle_t, int, int *)); +int via82c586_set_trigger __P((pciintr_icu_handle_t, int, int)); + +const struct pciintr_icu via82c586_pci_icu = { + via82c586_getclink, + via82c586_get_intr, + via82c586_set_intr, + via82c586_get_trigger, + via82c586_set_trigger, +}; + +const int vp3_cfg_trigger_shift[] = { + VP3_CFG_TRIGGER_SHIFT_PIRQA, + VP3_CFG_TRIGGER_SHIFT_PIRQB, + VP3_CFG_TRIGGER_SHIFT_PIRQC, + VP3_CFG_TRIGGER_SHIFT_PIRQD, +}; + +#define VP3_TRIGGER(reg, pirq) (((reg) >> vp3_cfg_trigger_shift[(pirq)]) & \ + VP3_CFG_TRIGGER_MASK) + +const int vp3_cfg_intr_shift[] = { + VP3_CFG_INTR_SHIFT_PIRQA, + VP3_CFG_INTR_SHIFT_PIRQB, + VP3_CFG_INTR_SHIFT_PIRQC, + VP3_CFG_INTR_SHIFT_PIRQD, +}; + +#define VP3_PIRQ(req, pirq) (((reg) >> vp3_cfg_intr_shift[(pirq)]) & \ + VP3_CFG_INTR_MASK) + +int +via82c586_init(pc, iot, tag, ptagp, phandp) + pci_chipset_tag_t pc; + bus_space_tag_t iot; + pcitag_t tag; + pciintr_icu_tag_t *ptagp; + pciintr_icu_handle_t *phandp; +{ + pcireg_t reg; + + if (piix_init(pc, iot, tag, ptagp, phandp) == 0) { + *ptagp = &via82c586_pci_icu; + + /* + * Enable EISA ELCR. + */ + reg = pci_conf_read(pc, tag, VP3_CFG_KBDMISCCTRL12_REG); + reg |= VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE << + VP3_CFG_MISCCTRL2_SHIFT; + pci_conf_write(pc, tag, VP3_CFG_KBDMISCCTRL12_REG, reg); + + return (0); + } + + return (1); +} + +int +via82c586_getclink(v, link, clinkp) + pciintr_icu_handle_t v; + int link, *clinkp; +{ + + if (VP3_LEGAL_LINK(link - 1)) { + *clinkp = link - 1; + return (0); + } + + return (1); +} + +int +via82c586_get_intr(v, clink, irqp) + pciintr_icu_handle_t v; + int clink, *irqp; +{ + struct piix_handle *ph = v; + pcireg_t reg; + int val; + + if (VP3_LEGAL_LINK(clink) == 0) + return (1); + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG); + val = VP3_PIRQ(reg, clink); + *irqp = (val == VP3_PIRQ_NONE) ? 0xff : val; + + return (0); +} + +int +via82c586_set_intr(v, clink, irq) + pciintr_icu_handle_t v; + int clink, irq; +{ + struct piix_handle *ph = v; + int shift, val; + pcireg_t reg; + + if (VP3_LEGAL_LINK(clink) == 0 || VP3_LEGAL_IRQ(irq) == 0) + return (1); + + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG); + via82c586_get_intr(v, clink, &val); + shift = vp3_cfg_intr_shift[clink]; + reg &= ~(VP3_CFG_INTR_MASK << shift); + reg |= (irq << shift); + pci_conf_write(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG, reg); + if (via82c586_get_intr(v, clink, &val) != 0 || + val != irq) + return (1); + + return (0); +} + +int +via82c586_get_trigger(v, irq, triggerp) + pciintr_icu_handle_t v; + int irq, *triggerp; +{ + struct piix_handle *ph = v; + int i, error, check_consistency, pciirq, pcitrigger = IST_NONE; + pcireg_t reg; + + if (VP3_LEGAL_IRQ(irq) == 0) + return (1); + + check_consistency = 0; + for (i = 0; i <= 3; i++) { + via82c586_get_intr(v, i, &pciirq); + if (pciirq == irq) { + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, + VP3_CFG_PIRQ_REG); + if (VP3_TRIGGER(reg, i) == VP3_CFG_TRIGGER_EDGE) + pcitrigger = IST_EDGE; + else + pcitrigger = IST_LEVEL; + check_consistency = 1; + break; + } + } + + error = piix_get_trigger(v, irq, triggerp); + if (error == 0 && check_consistency && pcitrigger != *triggerp) + return (1); + return (error); +} + +int +via82c586_set_trigger(v, irq, trigger) + pciintr_icu_handle_t v; + int irq, trigger; +{ + struct piix_handle *ph = v; + int i, pciirq, shift, testtrig; + pcireg_t reg; + + if (VP3_LEGAL_IRQ(irq) == 0) + return (1); + + for (i = 0; i <= 3; i++) { + via82c586_get_intr(v, i, &pciirq); + if (pciirq == irq) { + reg = pci_conf_read(ph->ph_pc, ph->ph_tag, + VP3_CFG_PIRQ_REG); + shift = vp3_cfg_trigger_shift[i]; + if (trigger == IST_LEVEL) + reg &= ~(VP3_CFG_TRIGGER_MASK << shift); + else + reg |= (VP3_CFG_TRIGGER_EDGE << shift); + pci_conf_write(ph->ph_pc, ph->ph_tag, + VP3_CFG_PIRQ_REG, reg); + break; + } + } + + if (piix_set_trigger(v, irq, trigger) != 0 || + via82c586_get_trigger(v, irq, &testtrig) != 0 || + testtrig != trigger) + return (1); + + return (0); +} diff --git a/sys/arch/i386/pci/via82c586reg.h b/sys/arch/i386/pci/via82c586reg.h new file mode 100644 index 000000000000..4ed73521780e --- /dev/null +++ b/sys/arch/i386/pci/via82c586reg.h @@ -0,0 +1,62 @@ +/* $NetBSD: via82c586reg.h,v 1.1 1999/11/17 01:21:21 thorpej Exp $ */ + +/* + * Copyright (c) 1999, by UCHIYAMA Yasushi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Register definitions for the VIA 82c586 PCI-ISA bridge interrupt controller. + */ + +#define VP3_CFG_PIRQ_REG 0x54 /* PCI configuration space */ +#define VP3_CFG_KBDMISCCTRL12_REG 0x44 +#define VP3_CFG_IDEMISCCTRL3_REG 0x48 + +#define VP3_CFG_MISCCTRL2_SHIFT 24 +#define VP3_CFG_MISCCTRL2_MASK 0x0f +#define VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE 0x20 +#define VP3_CFG_MISCCTRL2_REG(reg) \ + (((reg) >> VP3_CFG_MISCCTRL2_SHIFT) & VP3_CFG_MISCCTRL2_MASK) + +#define VP3_CFG_TRIGGER_LEVEL 0 +#define VP3_CFG_TRIGGER_EDGE 1 + +#define VP3_CFG_TRIGGER_MASK 0x01 +#define VP3_CFG_TRIGGER_SHIFT_PIRQA 3 +#define VP3_CFG_TRIGGER_SHIFT_PIRQB 2 +#define VP3_CFG_TRIGGER_SHIFT_PIRQC 1 +#define VP3_CFG_TRIGGER_SHIFT_PIRQD 0 + +#define VP3_CFG_INTR_MASK 0x04 +#define VP3_PIRQ_MASK 0xdefa + +#define VP3_CFG_INTR_SHIFT_PIRQA 0x14 +#define VP3_CFG_INTR_SHIFT_PIRQB 0x10 +#define VP3_CFG_INTR_SHIFT_PIRQC 0x1c +#define VP3_CFG_INTR_SHIFT_PIRQD 0x0c + +#define VP3_PIRQ_NONE 0 +#define VP3_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3) +#define VP3_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \ + ((1 << (irq)) & VP3_PIRQ_MASK) != 0)