Pull up following revision(s) (requested by msaitoh in ticket #1539):
share/man/man4/man4.x86/amdsmn.4: revision 1.5 sys/arch/x86/pci/amdsmn.c: revision 1.14 sys/arch/x86/pci/amdzentemp.c: revision 1.12-1.15 amdzentemp(4): Add Zen 3 support. amdzentemp(4): Add support for per CCD temperature sensor from FreeBSD. Fix build failure on i386. amdsmn(4),amdzentemp(4): Add support for 17h/6xh and 19h/6xh. amdsmn.4: Now support AMD Family 19h processors.
This commit is contained in:
martin
parent
9a522ca6be
commit
d5badbfc7a
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@ -1,4 +1,4 @@
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.\" $NetBSD: amdsmn.4,v 1.3.8.1 2020/04/24 17:46:44 martin Exp $
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.\" $NetBSD: amdsmn.4,v 1.3.8.2 2022/10/11 18:16:20 martin Exp $
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.\"
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.\" Copyright (c) 2018 Ian Clark <mrrooster@gmail.com>
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.\" All rights reserved.
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@ -54,7 +54,7 @@
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.\"
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.\" $FreeBSD: head/share/man/man4/amdsmn.4 323184 2017-09-05 15:13:41Z cem $
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.\"
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.Dd April 20, 2020
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.Dd October 2, 2022
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.Dt AMDSMN 4 x86
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.Os
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.Sh NAME
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@ -66,7 +66,8 @@
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The
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.Nm
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driver provides support for resources on the System Management Network bus
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in AMD Family 17h processors and some later AMD Family 15h processors.
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in AMD Family 19h processors, 17h processors and some later
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AMD Family 15h processors.
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.Sh SEE ALSO
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.Xr amdzentemp 4
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.Sh HISTORY
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@ -1,4 +1,4 @@
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/* $NetBSD: amdsmn.c,v 1.5.2.2 2022/07/27 14:40:08 martin Exp $ */
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/* $NetBSD: amdsmn.c,v 1.5.2.3 2022/10/11 18:16:20 martin Exp $ */
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/*-
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* Copyright (c) 2017, 2019 Conrad Meyer <cem@FreeBSD.org>
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@ -29,7 +29,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.5.2.2 2022/07/27 14:40:08 martin Exp $ ");
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__KERNEL_RCSID(0, "$NetBSD: amdsmn.c,v 1.5.2.3 2022/10/11 18:16:20 martin Exp $ ");
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/*
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* Driver for the AMD Family 15h (model 60+) and 17h CPU
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@ -87,11 +87,21 @@ static const struct pciid {
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.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
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.amdsmn_data_reg = F17H_SMN_DATA_REG,
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},
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{
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.amdsmn_deviceid = PCI_PRODUCT_AMD_F17_6X_RC,
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.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
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.amdsmn_data_reg = F17H_SMN_DATA_REG,
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},
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{
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.amdsmn_deviceid = PCI_PRODUCT_AMD_F17_7X_RC,
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.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
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.amdsmn_data_reg = F17H_SMN_DATA_REG,
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},
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{
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.amdsmn_deviceid = PCI_PRODUCT_AMD_F19_6X_RC,
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.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
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.amdsmn_data_reg = F17H_SMN_DATA_REG,
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},
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};
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static int amdsmn_match(device_t, cfdata_t, void *);
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@ -1,4 +1,4 @@
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/* $NetBSD: amdzentemp.c,v 1.9.2.1 2020/04/24 17:46:44 martin Exp $ */
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/* $NetBSD: amdzentemp.c,v 1.9.2.2 2022/10/11 18:16:20 martin Exp $ */
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/* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */
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/*
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@ -53,7 +53,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.9.2.1 2020/04/24 17:46:44 martin Exp $ ");
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__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.9.2.2 2022/10/11 18:16:20 martin Exp $ ");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -76,6 +76,7 @@ __KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.9.2.1 2020/04/24 17:46:44 martin Ex
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#define AMD_CURTMP_RANGE_ADJUST 49000000 /* in microKelvins (ie, 49C) */
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#define AMD_CURTMP_RANGE_CHECK __BIT(19)
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#define F10_TEMP_CURTMP __BITS(31,21) /* XXX same as amdtemp.c */
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#define F10_TEMP_CURTMP_MASK 0x7ff
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#define F15M60_CURTMP_TJSEL __BITS(17,16)
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/*
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@ -96,13 +97,40 @@ __KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.9.2.1 2020/04/24 17:46:44 martin Ex
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*/
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#define AMD_17H_CUR_TMP 0x59800
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/*
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* The following register set was discovered experimentally by Ondrej Čerman
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* and collaborators, but is not (yet) documented in a PPR/OSRR (other than
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* the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
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* SMU::THM). It seems plausible and the Linux sensor folks have adopted it.
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*/
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#define AMD_17H_CCD_TMP_BASE 0x59954
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#define AMD_17H_CCD_TMP_VALID __BIT(11)
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struct amdzentemp_softc {
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device_t sc_dev;
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struct sysmon_envsys *sc_sme;
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device_t sc_smn;
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envsys_data_t *sc_sensor;
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size_t sc_sensor_len;
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size_t sc_numsensors;
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int32_t sc_offset;
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uint32_t sc_ccd_tmp_base;
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};
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enum {
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NOSENSOR = 0,
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CORE0_SENSOR0,
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CCD_BASE,
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CCD0 = CCD_BASE,
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CCD1,
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CCD2,
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CCD3,
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CCD4,
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CCD5,
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CCD6,
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CCD7,
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CCD_MAX,
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NUM_CCDS = CCD_MAX - CCD_BASE
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};
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@ -110,10 +138,12 @@ static int amdzentemp_match(device_t, cfdata_t, void *);
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static void amdzentemp_attach(device_t, device_t, void *);
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static int amdzentemp_detach(device_t, int);
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static void amdzentemp_init(struct amdzentemp_softc *);
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static void amdzentemp_setup_sensors(struct amdzentemp_softc *, int);
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static void amdzentemp_init(struct amdzentemp_softc *, int, int);
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static void amdzentemp_setup_sensors(struct amdzentemp_softc *);
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static void amdzentemp_family15_refresh(struct sysmon_envsys *, envsys_data_t *);
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static void amdzentemp_family17_refresh(struct sysmon_envsys *, envsys_data_t *);
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static int amdzentemp_probe_ccd_sensors(struct amdzentemp_softc *, int, int);
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static void amdzentemp_setup_ccd_sensors(struct amdzentemp_softc *);
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CFATTACH_DECL_NEW(amdzentemp, sizeof(struct amdzentemp_softc),
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amdzentemp_match, amdzentemp_attach, amdzentemp_detach, NULL);
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@ -124,9 +154,9 @@ amdzentemp_match(device_t parent, cfdata_t match, void *aux)
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struct pci_attach_args *pa __diagused = aux;
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KASSERT(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD);
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cfdata_t parent_cfdata = device_cfdata(parent);
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/* Got AMD family 17h system management network */
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return parent_cfdata->cf_name &&
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memcmp(parent_cfdata->cf_name, "amdsmn", 6) == 0;
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@ -137,18 +167,20 @@ amdzentemp_attach(device_t parent, device_t self, void *aux)
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{
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struct amdzentemp_softc *sc = device_private(self);
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struct cpu_info *ci = curcpu();
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int family;
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int family, model;
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int error;
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size_t i;
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sc->sc_dev = self;
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family = CPUID_TO_FAMILY(ci->ci_signature);
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model = CPUID_TO_MODEL(ci->ci_signature);
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aprint_naive("\n");
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aprint_normal(": AMD CPU Temperature Sensors (Family%xh)",
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family);
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aprint_normal(": AMD CPU Temperature Sensors (Family%xh)", family);
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sc->sc_smn = parent;
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amdzentemp_init(sc);
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amdzentemp_init(sc, family, model);
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aprint_normal("\n");
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@ -156,12 +188,14 @@ amdzentemp_attach(device_t parent, device_t self, void *aux)
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sc->sc_sensor_len = sizeof(envsys_data_t) * sc->sc_numsensors;
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sc->sc_sensor = kmem_zalloc(sc->sc_sensor_len, KM_SLEEP);
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amdzentemp_setup_sensors(sc, device_unit(self));
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amdzentemp_setup_sensors(sc);
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/*
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* Set properties in sensors.
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*/
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for (i = 0; i < sc->sc_numsensors; i++) {
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if (sc->sc_sensor[i].private == NOSENSOR)
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continue;
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if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[i]))
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goto bad;
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}
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@ -177,6 +211,7 @@ amdzentemp_attach(device_t parent, device_t self, void *aux)
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sc->sc_sme->sme_refresh = amdzentemp_family15_refresh;
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break;
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case 0x17:
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case 0x19:
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sc->sc_sme->sme_refresh = amdzentemp_family17_refresh;
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break;
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default:
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@ -222,10 +257,10 @@ amdzentemp_detach(device_t self, int flags)
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static void
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amdzentemp_init(struct amdzentemp_softc *sc)
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amdzentemp_init(struct amdzentemp_softc *sc, int family, int model)
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{
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sc->sc_numsensors = 1;
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sc->sc_numsensors = 1 + amdzentemp_probe_ccd_sensors(sc, family, model);
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sc->sc_offset = 0;
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if (strstr(cpu_brand_string, "AMD Ryzen 5 1600X")
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@ -240,24 +275,28 @@ amdzentemp_init(struct amdzentemp_softc *sc)
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}
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static void
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amdzentemp_setup_sensors(struct amdzentemp_softc *sc, int dv_unit)
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amdzentemp_setup_sensors(struct amdzentemp_softc *sc)
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{
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sc->sc_sensor[0].units = ENVSYS_STEMP;
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sc->sc_sensor[0].state = ENVSYS_SVALID;
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sc->sc_sensor[0].flags = ENVSYS_FHAS_ENTROPY;
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sc->sc_sensor[0].private = CORE0_SENSOR0;
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snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc),
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"cpu%u temperature", dv_unit);
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"cpu%u temperature", device_unit(sc->sc_dev));
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if (sc->sc_numsensors > 1)
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amdzentemp_setup_ccd_sensors(sc);
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}
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static void
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amdzentemp_family15_refresh(struct sysmon_envsys *sme,
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envsys_data_t *edata)
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envsys_data_t *edata)
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{
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struct amdzentemp_softc *sc = sme->sme_cookie;
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uint32_t val, temp;
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int error;
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error = amdsmn_read(sc->sc_smn, AMD_15H_M60H_REPTMP_CTRL, &val);
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if (error) {
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edata->state = ENVSYS_SINVALID;
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@ -285,26 +324,141 @@ amdzentemp_family15_refresh(struct sysmon_envsys *sme,
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}
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static void
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amdzentemp_family17_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
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amdzentemp_family17_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
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{
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struct amdzentemp_softc *sc = sme->sme_cookie;
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uint32_t temp;
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int error;
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error = amdsmn_read(sc->sc_smn, AMD_17H_CUR_TMP, &temp);
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if (error) {
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bool minus49;
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int i, error;
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switch (edata->private) {
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case CORE0_SENSOR0:
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/* Tctl */
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error = amdsmn_read(sc->sc_smn, AMD_17H_CUR_TMP, &temp);
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if (error) {
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edata->state = ENVSYS_SINVALID;
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return;
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}
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minus49 = (temp & AMD_CURTMP_RANGE_CHECK) ? true : false;
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temp = __SHIFTOUT(temp, F10_TEMP_CURTMP);
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break;
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case CCD_BASE ... (CCD_MAX - 1):
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/* Tccd */
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i = edata->private - CCD_BASE;
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error = amdsmn_read(sc->sc_smn,
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sc->sc_ccd_tmp_base + (i * sizeof(temp)), &temp);
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if (error || !ISSET(temp, AMD_17H_CCD_TMP_VALID)) {
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edata->state = ENVSYS_SINVALID;
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return;
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}
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minus49 = true;
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temp &= F10_TEMP_CURTMP_MASK;
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break;
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default:
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edata->state = ENVSYS_SINVALID;
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return;
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}
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edata->state = ENVSYS_SVALID;
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/* From C to uK. */
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edata->value_cur = ((temp >> 21) * 125000) + 273150000;
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/* From C to uK. */
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edata->value_cur = (temp * 125000) + 273150000;
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/* adjust for possible offset of 49K */
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if (temp & AMD_CURTMP_RANGE_CHECK)
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if (minus49)
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edata->value_cur -= AMD_CURTMP_RANGE_ADJUST;
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edata->value_cur += sc->sc_offset;
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}
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static int
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amdzentemp_probe_ccd_sensors17h(struct amdzentemp_softc *sc, int model)
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{
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int maxreg;
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switch (model) {
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case 0x00 ... 0x2f: /* Zen1, Zen+ */
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maxreg = 4;
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break;
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case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */
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case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */
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case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */
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maxreg = 8;
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break;
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default:
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aprint_error_dev(sc->sc_dev,
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"Unrecognized Family 17h Model: %02xh\n", model);
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return 0;
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}
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return maxreg;
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}
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static int
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amdzentemp_probe_ccd_sensors19h(struct amdzentemp_softc *sc, int model)
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{
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int maxreg;
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switch (model) {
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case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */
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case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */
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maxreg = 8;
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break;
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case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
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sc->sc_ccd_tmp_base = 0x59b08;
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maxreg = 8;
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break;
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default:
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aprint_error_dev(sc->sc_dev,
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"Unrecognized Family 19h Model: %02xh\n", model);
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return 0;
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}
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return maxreg;
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}
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static int
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amdzentemp_probe_ccd_sensors(struct amdzentemp_softc *sc, int family, int model)
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{
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int nccd;
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/* Set default CCD temp sensor base address. */
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sc->sc_ccd_tmp_base = 0x59954;
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switch (family) {
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case 0x17:
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nccd = amdzentemp_probe_ccd_sensors17h(sc, model);
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break;
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case 0x19:
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nccd = amdzentemp_probe_ccd_sensors19h(sc, model);
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break;
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default:
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return 0;
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}
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return nccd;
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}
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static void
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amdzentemp_setup_ccd_sensors(struct amdzentemp_softc *sc)
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{
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envsys_data_t *edata;
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size_t i;
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uint32_t temp;
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int error;
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for (i = 0; i < sc->sc_numsensors - 1; i++) {
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error = amdsmn_read(sc->sc_smn,
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sc->sc_ccd_tmp_base + (i * sizeof(temp)), &temp);
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if (error || !ISSET(temp, AMD_17H_CCD_TMP_VALID))
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continue;
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edata = &sc->sc_sensor[1 + i];
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edata->units = ENVSYS_STEMP;
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edata->state = ENVSYS_SVALID;
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edata->flags = ENVSYS_FHAS_ENTROPY;
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edata->private = CCD_BASE + i;
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snprintf(edata->desc, sizeof(edata->desc),
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"cpu%u ccd%zu temperature", device_unit(sc->sc_dev), i);
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}
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}
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MODULE(MODULE_CLASS_DRIVER, amdzentemp, "sysmon_envsys,amdsmn");
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#ifdef _MODULE
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