Un-__P.
This commit is contained in:
bjh21
parent
6c6b1ee9b1
commit
d4eec8400b
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.h,v 1.38 2007/01/06 00:50:54 christos Exp $ */
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/* $NetBSD: cpufunc.h,v 1.39 2007/03/04 13:42:51 bjh21 Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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@ -51,25 +51,25 @@ struct cpu_functions {
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/* CPU functions */
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u_int (*cf_id) __P((void));
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void (*cf_cpwait) __P((void));
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u_int (*cf_id) (void);
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void (*cf_cpwait) (void);
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/* MMU functions */
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u_int (*cf_control) __P((u_int, u_int));
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void (*cf_domains) __P((u_int));
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void (*cf_setttb) __P((u_int));
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u_int (*cf_faultstatus) __P((void));
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u_int (*cf_faultaddress) __P((void));
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u_int (*cf_control) (u_int, u_int);
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void (*cf_domains) (u_int);
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void (*cf_setttb) (u_int);
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u_int (*cf_faultstatus) (void);
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u_int (*cf_faultaddress) (void);
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/* TLB functions */
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void (*cf_tlb_flushID) __P((void));
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void (*cf_tlb_flushID_SE) __P((u_int));
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void (*cf_tlb_flushI) __P((void));
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void (*cf_tlb_flushI_SE) __P((u_int));
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void (*cf_tlb_flushD) __P((void));
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void (*cf_tlb_flushD_SE) __P((u_int));
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void (*cf_tlb_flushID) (void);
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void (*cf_tlb_flushID_SE) (u_int);
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void (*cf_tlb_flushI) (void);
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void (*cf_tlb_flushI_SE) (u_int);
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void (*cf_tlb_flushD) (void);
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void (*cf_tlb_flushD_SE) (u_int);
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/*
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* Cache operations:
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@ -121,34 +121,34 @@ struct cpu_functions {
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* Valid virtual addresses must be passed to each
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* cache operation.
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*/
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void (*cf_icache_sync_all) __P((void));
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void (*cf_icache_sync_range) __P((vaddr_t, vsize_t));
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void (*cf_icache_sync_all) (void);
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void (*cf_icache_sync_range) (vaddr_t, vsize_t);
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void (*cf_dcache_wbinv_all) __P((void));
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void (*cf_dcache_wbinv_range) __P((vaddr_t, vsize_t));
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void (*cf_dcache_inv_range) __P((vaddr_t, vsize_t));
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void (*cf_dcache_wb_range) __P((vaddr_t, vsize_t));
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void (*cf_dcache_wbinv_all) (void);
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void (*cf_dcache_wbinv_range)(vaddr_t, vsize_t);
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void (*cf_dcache_inv_range) (vaddr_t, vsize_t);
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void (*cf_dcache_wb_range) (vaddr_t, vsize_t);
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void (*cf_idcache_wbinv_all) __P((void));
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void (*cf_idcache_wbinv_range) __P((vaddr_t, vsize_t));
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void (*cf_idcache_wbinv_all) (void);
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void (*cf_idcache_wbinv_range)(vaddr_t, vsize_t);
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/* Other functions */
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void (*cf_flush_prefetchbuf) __P((void));
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void (*cf_drain_writebuf) __P((void));
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void (*cf_flush_brnchtgt_C) __P((void));
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void (*cf_flush_brnchtgt_E) __P((u_int));
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void (*cf_flush_prefetchbuf) (void);
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void (*cf_drain_writebuf) (void);
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void (*cf_flush_brnchtgt_C) (void);
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void (*cf_flush_brnchtgt_E) (u_int);
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void (*cf_sleep) __P((int mode));
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void (*cf_sleep) (int mode);
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/* Soft functions */
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int (*cf_dataabt_fixup) __P((void *));
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int (*cf_prefetchabt_fixup) __P((void *));
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int (*cf_dataabt_fixup) (void *);
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int (*cf_prefetchabt_fixup) (void *);
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void (*cf_context_switch) __P((void));
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void (*cf_context_switch) (void);
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void (*cf_setup) __P((char *));
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void (*cf_setup) (char *);
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};
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extern struct cpu_functions cpufuncs;
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@ -196,137 +196,137 @@ extern u_int cputype;
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#define cpu_setup(a) cpufuncs.cf_setup(a)
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int set_cpufuncs __P((void));
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int set_cpufuncs (void);
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#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
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#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
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void cpufunc_nullop __P((void));
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int cpufunc_null_fixup __P((void *));
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int early_abort_fixup __P((void *));
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int late_abort_fixup __P((void *));
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u_int cpufunc_id __P((void));
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u_int cpufunc_control __P((u_int, u_int));
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void cpufunc_domains __P((u_int));
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u_int cpufunc_faultstatus __P((void));
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u_int cpufunc_faultaddress __P((void));
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void cpufunc_nullop (void);
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int cpufunc_null_fixup (void *);
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int early_abort_fixup (void *);
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int late_abort_fixup (void *);
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u_int cpufunc_id (void);
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u_int cpufunc_control (u_int, u_int);
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void cpufunc_domains (u_int);
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u_int cpufunc_faultstatus (void);
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u_int cpufunc_faultaddress (void);
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#ifdef CPU_ARM3
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u_int arm3_control __P((u_int, u_int));
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void arm3_cache_flush __P((void));
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u_int arm3_control (u_int, u_int);
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void arm3_cache_flush (void);
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#endif /* CPU_ARM3 */
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#if defined(CPU_ARM6) || defined(CPU_ARM7)
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void arm67_setttb __P((u_int));
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void arm67_tlb_flush __P((void));
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void arm67_tlb_purge __P((u_int));
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void arm67_cache_flush __P((void));
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void arm67_context_switch __P((void));
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void arm67_setttb (u_int);
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void arm67_tlb_flush (void);
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void arm67_tlb_purge (u_int);
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void arm67_cache_flush (void);
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void arm67_context_switch (void);
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#endif /* CPU_ARM6 || CPU_ARM7 */
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#ifdef CPU_ARM6
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void arm6_setup __P((char *));
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void arm6_setup (char *);
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#endif /* CPU_ARM6 */
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#ifdef CPU_ARM7
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void arm7_setup __P((char *));
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void arm7_setup (char *);
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#endif /* CPU_ARM7 */
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#ifdef CPU_ARM7TDMI
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int arm7_dataabt_fixup __P((void *));
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void arm7tdmi_setup __P((char *));
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void arm7tdmi_setttb __P((u_int));
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void arm7tdmi_tlb_flushID __P((void));
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void arm7tdmi_tlb_flushID_SE __P((u_int));
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void arm7tdmi_cache_flushID __P((void));
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void arm7tdmi_context_switch __P((void));
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int arm7_dataabt_fixup (void *);
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void arm7tdmi_setup (char *);
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void arm7tdmi_setttb (u_int);
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void arm7tdmi_tlb_flushID (void);
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void arm7tdmi_tlb_flushID_SE (u_int);
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void arm7tdmi_cache_flushID (void);
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void arm7tdmi_context_switch (void);
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#endif /* CPU_ARM7TDMI */
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#ifdef CPU_ARM8
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void arm8_setttb __P((u_int));
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void arm8_tlb_flushID __P((void));
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void arm8_tlb_flushID_SE __P((u_int));
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void arm8_cache_flushID __P((void));
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void arm8_cache_flushID_E __P((u_int));
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void arm8_cache_cleanID __P((void));
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void arm8_cache_cleanID_E __P((u_int));
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void arm8_cache_purgeID __P((void));
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void arm8_cache_purgeID_E __P((u_int entry));
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void arm8_setttb (u_int);
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void arm8_tlb_flushID (void);
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void arm8_tlb_flushID_SE (u_int);
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void arm8_cache_flushID (void);
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void arm8_cache_flushID_E (u_int);
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void arm8_cache_cleanID (void);
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void arm8_cache_cleanID_E (u_int);
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void arm8_cache_purgeID (void);
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void arm8_cache_purgeID_E (u_int entry);
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void arm8_cache_syncI __P((void));
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void arm8_cache_cleanID_rng __P((vaddr_t, vsize_t));
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void arm8_cache_cleanD_rng __P((vaddr_t, vsize_t));
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void arm8_cache_purgeID_rng __P((vaddr_t, vsize_t));
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void arm8_cache_purgeD_rng __P((vaddr_t, vsize_t));
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void arm8_cache_syncI_rng __P((vaddr_t, vsize_t));
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void arm8_cache_syncI (void);
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void arm8_cache_cleanID_rng (vaddr_t, vsize_t);
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void arm8_cache_cleanD_rng (vaddr_t, vsize_t);
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void arm8_cache_purgeID_rng (vaddr_t, vsize_t);
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void arm8_cache_purgeD_rng (vaddr_t, vsize_t);
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void arm8_cache_syncI_rng (vaddr_t, vsize_t);
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void arm8_context_switch __P((void));
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void arm8_context_switch (void);
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void arm8_setup __P((char *));
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void arm8_setup (char *);
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u_int arm8_clock_config __P((u_int, u_int));
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u_int arm8_clock_config (u_int, u_int);
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#endif
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#ifdef CPU_SA110
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void sa110_setup __P((char *));
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void sa110_context_switch __P((void));
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void sa110_setup (char *);
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void sa110_context_switch (void);
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#endif /* CPU_SA110 */
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#if defined(CPU_SA1100) || defined(CPU_SA1110)
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void sa11x0_drain_readbuf __P((void));
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void sa11x0_drain_readbuf (void);
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void sa11x0_context_switch __P((void));
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void sa11x0_cpu_sleep __P((int));
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void sa11x0_context_switch (void);
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void sa11x0_cpu_sleep (int);
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void sa11x0_setup __P((char *));
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void sa11x0_setup (char *);
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#endif
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#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
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void sa1_setttb __P((u_int));
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void sa1_setttb (u_int);
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void sa1_tlb_flushID_SE __P((u_int));
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void sa1_tlb_flushID_SE (u_int);
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void sa1_cache_flushID __P((void));
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void sa1_cache_flushI __P((void));
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void sa1_cache_flushD __P((void));
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void sa1_cache_flushD_SE __P((u_int));
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void sa1_cache_flushID (void);
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void sa1_cache_flushI (void);
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void sa1_cache_flushD (void);
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void sa1_cache_flushD_SE (u_int);
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void sa1_cache_cleanID __P((void));
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void sa1_cache_cleanD __P((void));
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void sa1_cache_cleanD_E __P((u_int));
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void sa1_cache_cleanID (void);
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void sa1_cache_cleanD (void);
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void sa1_cache_cleanD_E (u_int);
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void sa1_cache_purgeID __P((void));
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void sa1_cache_purgeID_E __P((u_int));
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void sa1_cache_purgeD __P((void));
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void sa1_cache_purgeD_E __P((u_int));
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void sa1_cache_purgeID (void);
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void sa1_cache_purgeID_E (u_int);
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void sa1_cache_purgeD (void);
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void sa1_cache_purgeD_E (u_int);
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void sa1_cache_syncI __P((void));
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void sa1_cache_cleanID_rng __P((vaddr_t, vsize_t));
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void sa1_cache_cleanD_rng __P((vaddr_t, vsize_t));
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void sa1_cache_purgeID_rng __P((vaddr_t, vsize_t));
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void sa1_cache_purgeD_rng __P((vaddr_t, vsize_t));
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void sa1_cache_syncI_rng __P((vaddr_t, vsize_t));
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void sa1_cache_syncI (void);
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void sa1_cache_cleanID_rng (vaddr_t, vsize_t);
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void sa1_cache_cleanD_rng (vaddr_t, vsize_t);
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void sa1_cache_purgeID_rng (vaddr_t, vsize_t);
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void sa1_cache_purgeD_rng (vaddr_t, vsize_t);
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void sa1_cache_syncI_rng (vaddr_t, vsize_t);
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#endif
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#ifdef CPU_ARM9
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void arm9_setttb __P((u_int));
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void arm9_setttb (u_int);
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void arm9_tlb_flushID_SE __P((u_int));
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void arm9_tlb_flushID_SE (u_int);
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void arm9_icache_sync_all __P((void));
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void arm9_icache_sync_range __P((vaddr_t, vsize_t));
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void arm9_icache_sync_all (void);
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void arm9_icache_sync_range (vaddr_t, vsize_t);
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void arm9_dcache_wbinv_all __P((void));
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void arm9_dcache_wbinv_range __P((vaddr_t, vsize_t));
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void arm9_dcache_inv_range __P((vaddr_t, vsize_t));
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void arm9_dcache_wb_range __P((vaddr_t, vsize_t));
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void arm9_dcache_wbinv_all (void);
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void arm9_dcache_wbinv_range (vaddr_t, vsize_t);
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void arm9_dcache_inv_range (vaddr_t, vsize_t);
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void arm9_dcache_wb_range (vaddr_t, vsize_t);
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void arm9_idcache_wbinv_all __P((void));
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void arm9_idcache_wbinv_range __P((vaddr_t, vsize_t));
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void arm9_idcache_wbinv_all (void);
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void arm9_idcache_wbinv_range (vaddr_t, vsize_t);
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void arm9_context_switch __P((void));
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void arm9_context_switch (void);
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void arm9_setup __P((char *));
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void arm9_setup (char *);
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extern unsigned arm9_dcache_sets_max;
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extern unsigned arm9_dcache_sets_inc;
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@ -335,59 +335,59 @@ extern unsigned arm9_dcache_index_inc;
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#endif
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#if defined(CPU_ARM9E) || defined(CPU_ARM10)
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void arm10_tlb_flushID_SE __P((u_int));
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void arm10_tlb_flushI_SE __P((u_int));
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void arm10_tlb_flushID_SE (u_int);
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void arm10_tlb_flushI_SE (u_int);
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void arm10_context_switch __P((void));
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void arm10_context_switch (void);
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void arm10_setup __P((char *));
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void arm10_setup (char *);
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#endif
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#ifdef CPU_ARM11
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void arm11_setttb __P((u_int));
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void arm11_setttb (u_int);
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void arm11_tlb_flushID_SE __P((u_int));
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void arm11_tlb_flushI_SE __P((u_int));
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void arm11_tlb_flushID_SE (u_int);
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void arm11_tlb_flushI_SE (u_int);
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void arm11_context_switch __P((void));
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void arm11_context_switch (void);
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void arm11_setup __P((char *string));
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void arm11_tlb_flushID __P((void));
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void arm11_tlb_flushI __P((void));
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void arm11_tlb_flushD __P((void));
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void arm11_tlb_flushD_SE __P((u_int va));
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void arm11_setup (char *string);
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void arm11_tlb_flushID (void);
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void arm11_tlb_flushI (void);
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void arm11_tlb_flushD (void);
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void arm11_tlb_flushD_SE (u_int va);
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void arm11_drain_writebuf __P((void));
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void arm11_drain_writebuf (void);
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#endif
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#if defined(CPU_ARM9E) || defined (CPU_ARM10)
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void armv5_ec_setttb __P((u_int));
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void armv5_ec_setttb (u_int);
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void armv5_ec_icache_sync_all __P((void));
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void armv5_ec_icache_sync_range __P((vaddr_t, vsize_t));
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void armv5_ec_icache_sync_all (void);
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void armv5_ec_icache_sync_range (vaddr_t, vsize_t);
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void armv5_ec_dcache_wbinv_all __P((void));
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void armv5_ec_dcache_wbinv_range __P((vaddr_t, vsize_t));
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void armv5_ec_dcache_inv_range __P((vaddr_t, vsize_t));
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void armv5_ec_dcache_wb_range __P((vaddr_t, vsize_t));
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void armv5_ec_dcache_wbinv_all (void);
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void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t);
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void armv5_ec_dcache_inv_range (vaddr_t, vsize_t);
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void armv5_ec_dcache_wb_range (vaddr_t, vsize_t);
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void armv5_ec_idcache_wbinv_all __P((void));
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void armv5_ec_idcache_wbinv_range __P((vaddr_t, vsize_t));
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void armv5_ec_idcache_wbinv_all (void);
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void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t);
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#endif
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#if defined (CPU_ARM10) || defined (CPU_ARM11)
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void armv5_setttb __P((u_int));
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void armv5_setttb (u_int);
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void armv5_icache_sync_all __P((void));
|
||||
void armv5_icache_sync_range __P((vaddr_t, vsize_t));
|
||||
void armv5_icache_sync_all (void);
|
||||
void armv5_icache_sync_range (vaddr_t, vsize_t);
|
||||
|
||||
void armv5_dcache_wbinv_all __P((void));
|
||||
void armv5_dcache_wbinv_range __P((vaddr_t, vsize_t));
|
||||
void armv5_dcache_inv_range __P((vaddr_t, vsize_t));
|
||||
void armv5_dcache_wb_range __P((vaddr_t, vsize_t));
|
||||
void armv5_dcache_wbinv_all (void);
|
||||
void armv5_dcache_wbinv_range (vaddr_t, vsize_t);
|
||||
void armv5_dcache_inv_range (vaddr_t, vsize_t);
|
||||
void armv5_dcache_wb_range (vaddr_t, vsize_t);
|
||||
|
||||
void armv5_idcache_wbinv_all __P((void));
|
||||
void armv5_idcache_wbinv_range __P((vaddr_t, vsize_t));
|
||||
void armv5_idcache_wbinv_all (void);
|
||||
void armv5_idcache_wbinv_range (vaddr_t, vsize_t);
|
||||
|
||||
extern unsigned armv5_dcache_sets_max;
|
||||
extern unsigned armv5_dcache_sets_inc;
|
||||
|
|
@ -400,59 +400,59 @@ extern unsigned armv5_dcache_index_inc;
|
|||
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
|
||||
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
|
||||
|
||||
void armv4_tlb_flushID __P((void));
|
||||
void armv4_tlb_flushI __P((void));
|
||||
void armv4_tlb_flushD __P((void));
|
||||
void armv4_tlb_flushD_SE __P((u_int));
|
||||
void armv4_tlb_flushID (void);
|
||||
void armv4_tlb_flushI (void);
|
||||
void armv4_tlb_flushD (void);
|
||||
void armv4_tlb_flushD_SE (u_int);
|
||||
|
||||
void armv4_drain_writebuf __P((void));
|
||||
void armv4_drain_writebuf (void);
|
||||
#endif
|
||||
|
||||
#if defined(CPU_IXP12X0)
|
||||
void ixp12x0_drain_readbuf __P((void));
|
||||
void ixp12x0_context_switch __P((void));
|
||||
void ixp12x0_setup __P((char *));
|
||||
void ixp12x0_drain_readbuf (void);
|
||||
void ixp12x0_context_switch (void);
|
||||
void ixp12x0_setup (char *);
|
||||
#endif
|
||||
|
||||
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
|
||||
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
|
||||
void xscale_cpwait __P((void));
|
||||
void xscale_cpwait (void);
|
||||
|
||||
void xscale_cpu_sleep __P((int));
|
||||
void xscale_cpu_sleep (int);
|
||||
|
||||
u_int xscale_control __P((u_int, u_int));
|
||||
u_int xscale_control (u_int, u_int);
|
||||
|
||||
void xscale_setttb __P((u_int));
|
||||
void xscale_setttb (u_int);
|
||||
|
||||
void xscale_tlb_flushID_SE __P((u_int));
|
||||
void xscale_tlb_flushID_SE (u_int);
|
||||
|
||||
void xscale_cache_flushID __P((void));
|
||||
void xscale_cache_flushI __P((void));
|
||||
void xscale_cache_flushD __P((void));
|
||||
void xscale_cache_flushD_SE __P((u_int));
|
||||
void xscale_cache_flushID (void);
|
||||
void xscale_cache_flushI (void);
|
||||
void xscale_cache_flushD (void);
|
||||
void xscale_cache_flushD_SE (u_int);
|
||||
|
||||
void xscale_cache_cleanID __P((void));
|
||||
void xscale_cache_cleanD __P((void));
|
||||
void xscale_cache_cleanD_E __P((u_int));
|
||||
void xscale_cache_cleanID (void);
|
||||
void xscale_cache_cleanD (void);
|
||||
void xscale_cache_cleanD_E (u_int);
|
||||
|
||||
void xscale_cache_clean_minidata __P((void));
|
||||
void xscale_cache_clean_minidata (void);
|
||||
|
||||
void xscale_cache_purgeID __P((void));
|
||||
void xscale_cache_purgeID_E __P((u_int));
|
||||
void xscale_cache_purgeD __P((void));
|
||||
void xscale_cache_purgeD_E __P((u_int));
|
||||
void xscale_cache_purgeID (void);
|
||||
void xscale_cache_purgeID_E (u_int);
|
||||
void xscale_cache_purgeD (void);
|
||||
void xscale_cache_purgeD_E (u_int);
|
||||
|
||||
void xscale_cache_syncI __P((void));
|
||||
void xscale_cache_cleanID_rng __P((vaddr_t, vsize_t));
|
||||
void xscale_cache_cleanD_rng __P((vaddr_t, vsize_t));
|
||||
void xscale_cache_purgeID_rng __P((vaddr_t, vsize_t));
|
||||
void xscale_cache_purgeD_rng __P((vaddr_t, vsize_t));
|
||||
void xscale_cache_syncI_rng __P((vaddr_t, vsize_t));
|
||||
void xscale_cache_flushD_rng __P((vaddr_t, vsize_t));
|
||||
void xscale_cache_syncI (void);
|
||||
void xscale_cache_cleanID_rng (vaddr_t, vsize_t);
|
||||
void xscale_cache_cleanD_rng (vaddr_t, vsize_t);
|
||||
void xscale_cache_purgeID_rng (vaddr_t, vsize_t);
|
||||
void xscale_cache_purgeD_rng (vaddr_t, vsize_t);
|
||||
void xscale_cache_syncI_rng (vaddr_t, vsize_t);
|
||||
void xscale_cache_flushD_rng (vaddr_t, vsize_t);
|
||||
|
||||
void xscale_context_switch __P((void));
|
||||
void xscale_context_switch (void);
|
||||
|
||||
void xscale_setup __P((char *));
|
||||
void xscale_setup (char *);
|
||||
#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */
|
||||
|
||||
#define tlb_flush cpu_tlb_flushID
|
||||
|
|
@ -518,20 +518,20 @@ u_int get_r15(void);
|
|||
* (in arm/arm32/setstack.S)
|
||||
*/
|
||||
|
||||
void set_stackptr __P((u_int, u_int));
|
||||
u_int get_stackptr __P((u_int));
|
||||
void set_stackptr (u_int, u_int);
|
||||
u_int get_stackptr (u_int);
|
||||
|
||||
/*
|
||||
* Miscellany
|
||||
*/
|
||||
|
||||
int get_pc_str_offset __P((void));
|
||||
int get_pc_str_offset (void);
|
||||
|
||||
/*
|
||||
* CPU functions from locore.S
|
||||
*/
|
||||
|
||||
void cpu_reset __P((void)) __attribute__((__noreturn__));
|
||||
void cpu_reset (void) __attribute__((__noreturn__));
|
||||
|
||||
/*
|
||||
* Cache info variables.
|
||||
|
|
|
|||
Loading…
Reference in New Issue