LANCE register definitions, plus some utility macros for the machine-
independent driver.
This commit is contained in:
mycroft
parent
c9a66fce20
commit
d4b1924adb
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/* $NetBSD: am7990.h,v 1.1 1995/04/11 04:17:50 mycroft Exp $ */
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/*-
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* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)if_lereg.h 8.1 (Berkeley) 6/10/93
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*/
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#define LEBLEN 1536 /* ETHERMTU + header + CRC */
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#define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
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/*
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* Receive message descriptor
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*/
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struct lermd {
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u_int16_t rmd0;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t rmd1_bits;
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u_int8_t rmd1_hadr;
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#else
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u_int8_t rmd1_hadr;
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u_int8_t rmd1_bits;
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#endif
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int16_t rmd2;
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u_int16_t rmd3;
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};
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/*
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* Transmit message descriptor
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*/
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struct letmd {
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u_int16_t tmd0;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t tmd1_bits;
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u_int8_t tmd1_hadr;
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#else
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u_int8_t tmd1_hadr;
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u_int8_t tmd1_bits;
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#endif
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int16_t tmd2;
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u_int16_t tmd3;
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};
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/*
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* Initialization block
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*/
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struct leinit {
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u_int16_t init_mode; /* +0x0000 */
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u_int16_t init_padr[3]; /* +0x0002 */
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u_int16_t init_ladrf[4]; /* +0x0008 */
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u_int16_t init_rdra; /* +0x0010 */
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u_int16_t init_rlen; /* +0x0012 */
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u_int16_t init_tdra; /* +0x0014 */
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u_int16_t init_tlen; /* +0x0016 */
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int16_t pad0[4]; /* Pad to 16 shorts */
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};
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#define LE_INITADDR(sc) (sc->sc_initaddr)
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#define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
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#define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
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#define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix))
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#define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix))
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/* register addresses */
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#define LE_CSR0 0x0000 /* Control and status register */
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#define LE_CSR1 0x0001 /* low address of init block */
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#define LE_CSR2 0x0002 /* high address of init block */
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#define LE_CSR3 0x0003 /* Bus master and control */
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/* Control and status register 0 (csr0) */
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#define LE_C0_ERR 0x8000 /* error summary */
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#define LE_C0_BABL 0x4000 /* transmitter timeout error */
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#define LE_C0_CERR 0x2000 /* collision */
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#define LE_C0_MISS 0x1000 /* missed a packet */
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#define LE_C0_MERR 0x0800 /* memory error */
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#define LE_C0_RINT 0x0400 /* receiver interrupt */
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#define LE_C0_TINT 0x0200 /* transmitter interrupt */
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#define LE_C0_IDON 0x0100 /* initalization done */
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#define LE_C0_INTR 0x0080 /* interrupt condition */
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#define LE_C0_INEA 0x0040 /* interrupt enable */
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#define LE_C0_RXON 0x0020 /* receiver on */
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#define LE_C0_TXON 0x0010 /* transmitter on */
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#define LE_C0_TDMD 0x0008 /* transmit demand */
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#define LE_C0_STOP 0x0004 /* disable all external activity */
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#define LE_C0_STRT 0x0002 /* enable external activity */
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#define LE_C0_INIT 0x0001 /* begin initalization */
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#define LE_C0_BITS \
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"\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\
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\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
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/* Control and status register 3 (csr3) */
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#define LE_C3_BSWP 0x0004 /* byte swap */
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#define LE_C3_ACON 0x0002 /* ALE control, eh? */
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#define LE_C3_BCON 0x0001 /* byte control */
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/* Initialzation block (mode) */
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#define LE_MODE_PROM 0x8000 /* promiscuous mode */
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/* 0x7f80 reserved, must be zero */
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#define LE_MODE_INTL 0x0040 /* internal loopback */
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#define LE_MODE_DRTY 0x0020 /* disable retry */
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#define LE_MODE_COLL 0x0010 /* force a collision */
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#define LE_MODE_DTCR 0x0008 /* disable transmit CRC */
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#define LE_MODE_LOOP 0x0004 /* loopback mode */
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#define LE_MODE_DTX 0x0002 /* disable transmitter */
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#define LE_MODE_DRX 0x0001 /* disable receiver */
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#define LE_MODE_NORMAL 0 /* none of the above */
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/* Receive message descriptor 1 (rmd1_bits) */
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#define LE_R1_OWN 0x80 /* LANCE owns the packet */
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#define LE_R1_ERR 0x40 /* error summary */
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#define LE_R1_FRAM 0x20 /* framing error */
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#define LE_R1_OFLO 0x10 /* overflow error */
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#define LE_R1_CRC 0x08 /* CRC error */
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#define LE_R1_BUFF 0x04 /* buffer error */
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#define LE_R1_STP 0x02 /* start of packet */
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#define LE_R1_ENP 0x01 /* end of packet */
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#define LE_R1_BITS \
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"\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP"
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/* Transmit message descriptor 1 (tmd1_bits) */
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#define LE_T1_OWN 0x80 /* LANCE owns the packet */
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#define LE_T1_ERR 0x40 /* error summary */
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#define LE_T1_MORE 0x10 /* multiple collisions */
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#define LE_T1_ONE 0x08 /* single collision */
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#define LE_T1_DEF 0x04 /* defferred transmit */
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#define LE_T1_STP 0x02 /* start of packet */
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#define LE_T1_ENP 0x01 /* end of packet */
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#define LE_T1_BITS \
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"\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP"
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/* Transmit message descriptor 3 (tmd3) */
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#define LE_T3_BUFF 0x8000 /* buffer error */
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#define LE_T3_UFLO 0x4000 /* underflow error */
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#define LE_T3_LCOL 0x1000 /* late collision */
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#define LE_T3_LCAR 0x0800 /* loss of carrier */
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#define LE_T3_RTRY 0x0400 /* retry error */
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#define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */
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#define LE_XMD2_ONES 0xf000
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#define LE_T3_BITS \
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"\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY"
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@ -0,0 +1,178 @@
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/* $NetBSD: am7990reg.h,v 1.1 1995/04/11 04:17:50 mycroft Exp $ */
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/*-
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* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)if_lereg.h 8.1 (Berkeley) 6/10/93
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*/
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#define LEBLEN 1536 /* ETHERMTU + header + CRC */
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#define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
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/*
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* Receive message descriptor
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*/
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struct lermd {
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u_int16_t rmd0;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t rmd1_bits;
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u_int8_t rmd1_hadr;
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#else
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u_int8_t rmd1_hadr;
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u_int8_t rmd1_bits;
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#endif
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int16_t rmd2;
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u_int16_t rmd3;
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};
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/*
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* Transmit message descriptor
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*/
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struct letmd {
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u_int16_t tmd0;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t tmd1_bits;
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u_int8_t tmd1_hadr;
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#else
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u_int8_t tmd1_hadr;
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u_int8_t tmd1_bits;
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#endif
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int16_t tmd2;
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u_int16_t tmd3;
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};
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/*
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* Initialization block
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*/
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struct leinit {
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u_int16_t init_mode; /* +0x0000 */
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u_int16_t init_padr[3]; /* +0x0002 */
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u_int16_t init_ladrf[4]; /* +0x0008 */
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u_int16_t init_rdra; /* +0x0010 */
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u_int16_t init_rlen; /* +0x0012 */
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u_int16_t init_tdra; /* +0x0014 */
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u_int16_t init_tlen; /* +0x0016 */
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int16_t pad0[4]; /* Pad to 16 shorts */
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};
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#define LE_INITADDR(sc) (sc->sc_initaddr)
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#define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
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#define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
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#define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix))
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#define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix))
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/* register addresses */
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#define LE_CSR0 0x0000 /* Control and status register */
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#define LE_CSR1 0x0001 /* low address of init block */
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#define LE_CSR2 0x0002 /* high address of init block */
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#define LE_CSR3 0x0003 /* Bus master and control */
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/* Control and status register 0 (csr0) */
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#define LE_C0_ERR 0x8000 /* error summary */
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#define LE_C0_BABL 0x4000 /* transmitter timeout error */
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#define LE_C0_CERR 0x2000 /* collision */
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#define LE_C0_MISS 0x1000 /* missed a packet */
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#define LE_C0_MERR 0x0800 /* memory error */
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#define LE_C0_RINT 0x0400 /* receiver interrupt */
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#define LE_C0_TINT 0x0200 /* transmitter interrupt */
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#define LE_C0_IDON 0x0100 /* initalization done */
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#define LE_C0_INTR 0x0080 /* interrupt condition */
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#define LE_C0_INEA 0x0040 /* interrupt enable */
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#define LE_C0_RXON 0x0020 /* receiver on */
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#define LE_C0_TXON 0x0010 /* transmitter on */
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#define LE_C0_TDMD 0x0008 /* transmit demand */
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#define LE_C0_STOP 0x0004 /* disable all external activity */
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#define LE_C0_STRT 0x0002 /* enable external activity */
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#define LE_C0_INIT 0x0001 /* begin initalization */
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#define LE_C0_BITS \
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"\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\
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\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
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/* Control and status register 3 (csr3) */
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#define LE_C3_BSWP 0x0004 /* byte swap */
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#define LE_C3_ACON 0x0002 /* ALE control, eh? */
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#define LE_C3_BCON 0x0001 /* byte control */
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/* Initialzation block (mode) */
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#define LE_MODE_PROM 0x8000 /* promiscuous mode */
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/* 0x7f80 reserved, must be zero */
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#define LE_MODE_INTL 0x0040 /* internal loopback */
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#define LE_MODE_DRTY 0x0020 /* disable retry */
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#define LE_MODE_COLL 0x0010 /* force a collision */
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#define LE_MODE_DTCR 0x0008 /* disable transmit CRC */
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#define LE_MODE_LOOP 0x0004 /* loopback mode */
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#define LE_MODE_DTX 0x0002 /* disable transmitter */
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#define LE_MODE_DRX 0x0001 /* disable receiver */
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#define LE_MODE_NORMAL 0 /* none of the above */
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/* Receive message descriptor 1 (rmd1_bits) */
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#define LE_R1_OWN 0x80 /* LANCE owns the packet */
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#define LE_R1_ERR 0x40 /* error summary */
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#define LE_R1_FRAM 0x20 /* framing error */
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#define LE_R1_OFLO 0x10 /* overflow error */
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#define LE_R1_CRC 0x08 /* CRC error */
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#define LE_R1_BUFF 0x04 /* buffer error */
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#define LE_R1_STP 0x02 /* start of packet */
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#define LE_R1_ENP 0x01 /* end of packet */
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#define LE_R1_BITS \
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"\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP"
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/* Transmit message descriptor 1 (tmd1_bits) */
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#define LE_T1_OWN 0x80 /* LANCE owns the packet */
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#define LE_T1_ERR 0x40 /* error summary */
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#define LE_T1_MORE 0x10 /* multiple collisions */
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#define LE_T1_ONE 0x08 /* single collision */
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#define LE_T1_DEF 0x04 /* defferred transmit */
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#define LE_T1_STP 0x02 /* start of packet */
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#define LE_T1_ENP 0x01 /* end of packet */
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#define LE_T1_BITS \
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"\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP"
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/* Transmit message descriptor 3 (tmd3) */
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#define LE_T3_BUFF 0x8000 /* buffer error */
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#define LE_T3_UFLO 0x4000 /* underflow error */
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#define LE_T3_LCOL 0x1000 /* late collision */
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#define LE_T3_LCAR 0x0800 /* loss of carrier */
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#define LE_T3_RTRY 0x0400 /* retry error */
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#define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */
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#define LE_XMD2_ONES 0xf000
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#define LE_T3_BITS \
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"\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY"
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