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MIPS3_CONFIG_SC is an unreliable indicator for SC presence; r5k_enable_sdcache() 

will gracefully exit if there is no secondary cache.  Rework #ifdef'd out
r5k cache code to take this into account, and remove pointless r10k case.
This commit is contained in:
sekiya 2004-12-13 08:30:58 +00:00
parent 387711acf9
commit d45f3ffb2c
1 changed files with 16 additions and 26 deletions
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42
sys/arch/sgimips/sgimips/machdep.c
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@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.87 2004/10/02 03:19:00 sekiya Exp $ */
/* $NetBSD: machdep.c,v 1.88 2004/12/13 08:30:58 sekiya Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.87 2004/10/02 03:19:00 sekiya Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.88 2004/12/13 08:30:58 sekiya Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@ -146,11 +146,15 @@ extern void ip22_sdcache_disable(void);
extern void ip22_sdcache_enable(void);
#endif
#if defined(MIPS1)
extern void mips1_clock_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
extern unsigned long mips1_clkread(void);
#endif
#if defined(MIPS3)
extern void mips3_clock_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
extern unsigned long mips3_clkread(void);
#endif
void mach_init(int, char **, int, struct btinfo_common *);
@ -395,7 +399,7 @@ mach_init(int argc, char **argv, int magic, struct btinfo_common *btinfo)
#endif
switch (mach_type) {
#ifdef MIPS1
#if defined(MIPS1)
case MACH_SGI_IP12:
i = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd0000);
mach_boardrev = (i & 0x7000) >> 12;
@ -420,6 +424,7 @@ mach_init(int argc, char **argv, int magic, struct btinfo_common *btinfo)
platform.clkread = mips1_clkread;
break;
#endif /* MIPS1 */
#if defined(MIPS3) || defined(MIPS64)
case MACH_SGI_IP20:
i = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd0000);
@ -843,9 +848,6 @@ void ddb_trap_hook(int where)
void mips_machdep_cache_config(void)
{
#if defined(MIPS3) || defined(MIPS64)
volatile u_int32_t cpu_config;
arcbios_tree_walk(mips_machdep_find_l2cache, NULL);
switch (MIPS_PRID_IMPL(cpu_id)) {
@ -860,32 +862,20 @@ void mips_machdep_cache_config(void)
ip22_sdcache_disable();
break;
#endif
#ifndef ENABLE_MIPS_R3NKK
#if defined(MIPS3)
case MIPS_R5000:
#endif
case MIPS_RM5200:
cpu_config = mips3_cp0_config_read();
#ifdef notyet /* disable r5ksc for now */
if ((cpu_config & MIPS3_CONFIG_SC) == 0)
r5k_enable_sdcache();
else
#ifdef notyet
r5k_enable_sdcache();
#else
cpu_config &= ~MIPS3_CONFIG_SE;
mips3_cp0_config_write(cpu_config);
mips3_cp0_config_write( (mips3_cp0_config_read())
& ~MIPS3_CONFIG_SE);
mips_sdcache_size = 0;
mips_sdcache_line_size = 0;
#endif
{
mips_sdcache_size = 0;
mips_sdcache_line_size = 0;
}
break;
#ifdef ENABLE_MIPS4_CACHE_R10K
case MIPS_R10000:
cpu_config = mips3_cp0_config_read();
aprint_debug("\nr10k cpu config is %x\n", cpu_config);
break;
#endif /* ENABLE_MIPS4_CACHE_R10K */
#endif
}
#endif
}
void