Add five errata for AMD Family 17h (Ryzen etc), tested by Patrick Welche,
thanks. Also add two errata for Family 16h, not yet tested, so not yet enabled.
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maxv
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d40ccf42c1
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@ -1,4 +1,4 @@
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/* $NetBSD: specialreg.h,v 1.128 2018/07/13 09:37:32 maxv Exp $ */
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/* $NetBSD: specialreg.h,v 1.129 2018/08/07 10:50:12 maxv Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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@ -857,6 +857,9 @@
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#define NB_CFG_INITAPICCPUIDLO (1ULL << 54)
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#define MSR_LS_CFG 0xc0011020
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#define LS_CFG_ERRATA_1033 __BIT(4)
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#define LS_CFG_ERRATA_793 __BIT(15)
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#define LS_CFG_ERRATA_1095 __BIT(57)
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#define LS_CFG_DIS_LS2_SQUISH 0x02000000
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#define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL
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#define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL
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@ -865,6 +868,7 @@
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#define MSR_IC_CFG 0xc0011021
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#define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
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#define IC_CFG_DIS_IND 0x00004000
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#define IC_CFG_ERRATA_776 __BIT(26)
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#define MSR_DC_CFG 0xc0011022
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#define DC_CFG_DIS_CNV_WC_SSO 0x00000008
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@ -879,8 +883,15 @@
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#define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
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#define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
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#define MSR_FP_CFG 0xc0011028
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#define FP_CFG_ERRATA_1049 __BIT(4)
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#define MSR_DE_CFG 0xc0011029
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#define DE_CFG_ERRATA_721 0x00000001
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#define DE_CFG_ERRATA_1021 __BIT(13)
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#define MSR_LS_CFG2 0xc001102d
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#define LS_CFG2_ERRATA_1091 __BIT(34)
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/* AMD Family10h MSRs */
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#define MSR_OSVW_ID_LENGTH 0xc0010140
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@ -1,4 +1,4 @@
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/* $NetBSD: errata.c,v 1.23 2016/01/05 10:20:22 hannken Exp $ */
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/* $NetBSD: errata.c,v 1.24 2018/08/07 10:50:12 maxv Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -45,7 +45,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.23 2016/01/05 10:20:22 hannken Exp $");
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__KERNEL_RCSID(0, "$NetBSD: errata.c,v 1.24 2018/08/07 10:50:12 maxv Exp $");
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#include <sys/types.h>
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#include <sys/systm.h>
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@ -70,8 +70,8 @@ typedef enum cpurev {
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BH_E4, CH_CG, CH_D0, DH_CG, DH_D0, DH_E3, DH_E6, JH_E1,
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JH_E6, SH_B0, SH_B3, SH_C0, SH_CG, SH_D0, SH_E4, SH_E5,
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DR_BA, DR_B2, DR_B3, RB_C2, RB_C3, BL_C2, BL_C3, DA_C2,
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DA_C3, HY_D0, HY_D1, HY_D1_G34R1, PH_E0, LN_B0,
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OINK
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DA_C3, HY_D0, HY_D1, HY_D1_G34R1, PH_E0, LN_B0, KB_A1,
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ML_A1, ZP_B1, ZP_B2, PiR_B2, OINK
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} cpurev_t;
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static const u_int cpurevs[] = {
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@ -89,7 +89,9 @@ static const u_int cpurevs[] = {
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RB_C2, 0x0100f42, RB_C3, 0x0100f43, BL_C2, 0x0100f52,
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BL_C3, 0x0100f53, DA_C2, 0x0100f62, DA_C3, 0x0100f63,
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HY_D0, 0x0100f80, HY_D1, 0x0100f81, HY_D1_G34R1, 0x0100f91,
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PH_E0, 0x0100fa0, LN_B0, 0x0300f10,
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PH_E0, 0x0100fa0, LN_B0, 0x0300f10, KB_A1, 0x0700F01,
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ML_A1, 0x0730F01, ZP_B1, 0x0800F11, ZP_B2, 0x0800F12,
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PiR_B2, 0x0800F82,
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OINK
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};
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@ -142,6 +144,26 @@ static const uint8_t x86_errata_set11[] = {
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DA_C3, HY_D0, HY_D1, HY_D1_G34R1, PH_E0, LN_B0, OINK
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};
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#ifdef notyet_f16h
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static const uint8_t x86_errata_set12[] = {
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KB_A1, OINK
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};
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#endif
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static const uint8_t x86_errata_set13[] = {
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ZP_B1, ZP_B2, PiR_B2, OINK
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};
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static const uint8_t x86_errata_set14[] = {
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ZP_B1, OINK
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};
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#ifdef notyet_f16h
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static const uint8_t x86_errata_set15[] = {
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KB_A1, ML_A1, OINK
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};
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#endif
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static bool x86_errata_setmsr(struct cpu_info *, errata_t *);
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static bool x86_errata_testmsr(struct cpu_info *, errata_t *);
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@ -285,6 +307,62 @@ static errata_t errata[] = {
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721, FALSE, MSR_DE_CFG, x86_errata_set11,
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x86_errata_setmsr, DE_CFG_ERRATA_721
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},
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#ifdef notyet_f16h /* TODO: needs to be tested */
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/*
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* 776: Incorrect Processor Branch Prediction for Two Consecutive
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* Linear Pages
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*/
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{
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776, FALSE, MSR_IC_CFG, x86_errata_set12,
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x86_errata_setmsr, IC_CFG_ERRATA_776
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},
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/*
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* 793: Specific Combination of Writes to Write Combined Memory
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* Types and Locked Instructions May Cause Core Hang
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*/
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{
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793, FALSE, MSR_LS_CFG, x86_errata_set15,
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x86_errata_setmsr, LS_CFG_ERRATA_793
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},
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#endif
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/*
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* 1021: Load Operation May Receive Stale Data From Older Store
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* Operation
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*/
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{
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1021, FALSE, MSR_DE_CFG, x86_errata_set13,
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x86_errata_setmsr, DE_CFG_ERRATA_1021
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},
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/*
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* 1033: A Lock Operation May Cause the System to Hang
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*/
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{
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1033, FALSE, MSR_LS_CFG, x86_errata_set14,
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x86_errata_setmsr, LS_CFG_ERRATA_1033
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},
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/*
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* 1049: FCMOV Instruction May Not Execute Correctly
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*/
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{
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1049, FALSE, MSR_FP_CFG, x86_errata_set13,
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x86_errata_setmsr, FP_CFG_ERRATA_1049
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},
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/*
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* 1091: Address Boundary Crossing Load Operation May Receive
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* Stale Data
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*/
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{
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1091, FALSE, MSR_LS_CFG2, x86_errata_set13,
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x86_errata_setmsr, LS_CFG2_ERRATA_1091
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},
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/*
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* 1095: Potential Violation of Read Ordering In Lock Operation
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* In SMT (Simultaneous Multithreading) Mode
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*/
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{
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1095, FALSE, MSR_LS_CFG, x86_errata_set13,
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x86_errata_setmsr, LS_CFG_ERRATA_1095
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},
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};
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static bool
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