Tegra K1 Watchdog support.
This commit is contained in:
jmcneill
parent
eb69509472
commit
d33dbb1618
@ -1,4 +1,4 @@
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# $NetBSD: files.tegra,v 1.13 2015/05/18 20:36:42 jmcneill Exp $
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# $NetBSD: files.tegra,v 1.14 2015/05/30 13:25:55 jmcneill Exp $
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#
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# Configuration info for NVIDIA Tegra ARM Peripherals
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#
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@ -42,6 +42,11 @@ device tegragpio: gpiobus
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attach tegragpio at tegraio with tegra_gpio
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file arch/arm/nvidia/tegra_gpio.c tegra_gpio
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# Timers
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device tegratimer: sysmon_wdog
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attach tegratimer at tegraio with tegra_timer
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file arch/arm/nvidia/tegra_timer.c tegra_timer
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# MPIO / Pinmux
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device tegrampio
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attach tegrampio at tegraio with tegra_mpio
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_car.c,v 1.20 2015/05/30 11:10:24 jmcneill Exp $ */
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/* $NetBSD: tegra_car.c,v 1.21 2015/05/30 13:25:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -29,7 +29,7 @@
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#include "locators.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.20 2015/05/30 11:10:24 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.21 2015/05/30 13:25:55 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -792,3 +792,25 @@ tegra_car_host1x_enable(void)
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/* Leave reset */
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bus_space_write_4(bst, bsh, CAR_RST_DEV_L_CLR_REG, CAR_DEV_L_HOST1X);
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}
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void
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tegra_car_wdt_enable(u_int timer, bool enable)
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{
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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uint32_t enable_bits;
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KASSERT(timer == 1 || timer == 2);
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tegra_car_get_bs(&bst, &bsh);
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enable_bits = enable ?
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(CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN) : 0;
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tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG,
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__SHIFTIN(timer - 1, CAR_RST_SOURCE_WDT_SEL) |
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enable_bits,
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CAR_RST_SOURCE_WDT_SYS_RST_EN |
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CAR_RST_SOURCE_WDT_SEL |
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CAR_RST_SOURCE_WDT_EN);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_carreg.h,v 1.17 2015/05/30 11:10:24 jmcneill Exp $ */
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/* $NetBSD: tegra_carreg.h,v 1.18 2015/05/30 13:25:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -29,6 +29,13 @@
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#ifndef _ARM_TEGRA_CARREG_H
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#define _ARM_TEGRA_CARREG_H
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#define CAR_RST_SOURCE_REG 0x00
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#define CAR_RST_SOURCE_WDT_EN __BIT(5)
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#define CAR_RST_SOURCE_WDT_SEL __BIT(4)
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#define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2)
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#define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1)
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#define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0)
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#define CAR_CLK_OUT_ENB_L_REG 0x10
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#define CAR_CLK_OUT_ENB_H_REG 0x14
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#define CAR_CLK_OUT_ENB_U_REG 0x18
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_intr.h,v 1.5 2015/05/17 01:28:32 jmcneill Exp $ */
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/* $NetBSD: tegra_intr.h,v 1.6 2015/05/30 13:25:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -37,6 +37,8 @@
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#define TEGRA_INTR(x) ((x) + 32)
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#define TEGRA_INTR_TMR1 TEGRA_INTR(0)
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#define TEGRA_INTR_TMR2 TEGRA_INTR(1)
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#define TEGRA_INTR_SDMMC1 TEGRA_INTR(14)
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#define TEGRA_INTR_SDMMC2 TEGRA_INTR(15)
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#define TEGRA_INTR_SDMMC3 TEGRA_INTR(19)
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@ -47,6 +49,8 @@
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#define TEGRA_INTR_UARTA TEGRA_INTR(36)
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#define TEGRA_INTR_UARTB TEGRA_INTR(37)
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#define TEGRA_INTR_I2C1 TEGRA_INTR(38)
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#define TEGRA_INTR_TMR3 TEGRA_INTR(41)
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#define TEGRA_INTR_TMR4 TEGRA_INTR(42)
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#define TEGRA_INTR_UARTC TEGRA_INTR(46)
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#define TEGRA_INTR_I2C5 TEGRA_INTR(53)
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#define TEGRA_INTR_I2C6 TEGRA_INTR(63)
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@ -62,5 +66,12 @@
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#define TEGRA_INTR_PCIE_MSI TEGRA_INTR(99)
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#define TEGRA_INTR_PCIE_WAKE TEGRA_INTR(100)
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#define TEGRA_INTR_I2C4 TEGRA_INTR(120)
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#define TEGRA_INTR_TMR5 TEGRA_INTR(121)
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#define TEGRA_INTR_WDT_CPU TEGRA_INTR(123)
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#define TEGRA_INTR_WDT_AVP TEGRA_INTR(124)
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#define TEGRA_INTR_TMR6 TEGRA_INTR(152)
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#define TEGRA_INTR_TMR7 TEGRA_INTR(153)
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#define TEGRA_INTR_TMR8 TEGRA_INTR(154)
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#define TEGRA_INTR_TMR9 TEGRA_INTR(155)
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#define TEGRA_INTR_TMR0 TEGRA_INTR(156)
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#endif /* _ARM_TEGRA_INTR_H */
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_io.c,v 1.11 2015/05/18 20:36:42 jmcneill Exp $ */
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/* $NetBSD: tegra_io.c,v 1.12 2015/05/30 13:25:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -29,7 +29,7 @@
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#include "opt_tegra.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.11 2015/05/18 20:36:42 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.12 2015/05/30 13:25:55 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -66,6 +66,8 @@ static const struct tegra_locators tegra_ppsb_locators[] = {
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TEGRA_CAR_OFFSET, TEGRA_CAR_SIZE, NOPORT, NOINTR },
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{ "tegragpio",
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TEGRA_GPIO_OFFSET, TEGRA_GPIO_SIZE, NOPORT, NOINTR },
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{ "tegratimer",
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TEGRA_TIMER_OFFSET, TEGRA_TIMER_SIZE, NOPORT, NOINTR },
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};
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static const struct tegra_locators tegra_apb_locators[] = {
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_reg.h,v 1.11 2015/05/18 20:36:42 jmcneill Exp $ */
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/* $NetBSD: tegra_reg.h,v 1.12 2015/05/30 13:25:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -120,6 +120,8 @@
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#define TEGRA_XUSB_DEV_SIZE 0xa000
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/* PPSB */
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#define TEGRA_TIMER_OFFSET 0x00005000
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#define TEGRA_TIMER_SIZE 0x400
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#define TEGRA_CAR_OFFSET 0x00006000
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#define TEGRA_CAR_SIZE 0x1000
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#define TEGRA_GPIO_OFFSET 0x0000d000
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140
sys/arch/arm/nvidia/tegra_timer.c
Normal file
140
sys/arch/arm/nvidia/tegra_timer.c
Normal file
@ -0,0 +1,140 @@
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/* $NetBSD: tegra_timer.c,v 1.1 2015/05/30 13:25:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_timer.c,v 1.1 2015/05/30 13:25:55 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/wdog.h>
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#include <dev/sysmon/sysmonvar.h>
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#include <arm/nvidia/tegra_reg.h>
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#include <arm/nvidia/tegra_timerreg.h>
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#include <arm/nvidia/tegra_var.h>
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#define TEGRA_TIMER_WDOG_PERIOD_DEFAULT 10
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static int tegra_timer_match(device_t, cfdata_t, void *);
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static void tegra_timer_attach(device_t, device_t, void *);
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struct tegra_timer_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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struct sysmon_wdog sc_smw;
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};
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static int tegra_timer_wdt_setmode(struct sysmon_wdog *);
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static int tegra_timer_wdt_tickle(struct sysmon_wdog *);
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CFATTACH_DECL_NEW(tegra_timer, sizeof(struct tegra_timer_softc),
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tegra_timer_match, tegra_timer_attach, NULL, NULL);
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#define TIMER_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define TIMER_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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#define TIMER_SET_CLEAR(sc, reg, set, clr) \
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tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
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static int
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tegra_timer_match(device_t parent, cfdata_t cf, void *aux)
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{
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return 1;
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}
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static void
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tegra_timer_attach(device_t parent, device_t self, void *aux)
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{
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struct tegra_timer_softc * const sc = device_private(self);
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struct tegraio_attach_args * const tio = aux;
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const struct tegra_locators * const loc = &tio->tio_loc;
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sc->sc_dev = self;
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sc->sc_bst = tio->tio_bst;
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bus_space_subregion(tio->tio_bst, tio->tio_bsh,
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loc->loc_offset, loc->loc_size, &sc->sc_bsh);
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aprint_naive("\n");
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aprint_normal(": Timers\n");
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sc->sc_smw.smw_name = device_xname(self);
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sc->sc_smw.smw_cookie = sc;
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sc->sc_smw.smw_setmode = tegra_timer_wdt_setmode;
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sc->sc_smw.smw_tickle = tegra_timer_wdt_tickle;
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sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
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aprint_normal_dev(self, "default watchdog period is %u seconds\n",
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sc->sc_smw.smw_period);
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if (sysmon_wdog_register(&sc->sc_smw) != 0)
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aprint_error_dev(self, "couldn't register with sysmon\n");
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}
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static int
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tegra_timer_wdt_setmode(struct sysmon_wdog *smw)
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{
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struct tegra_timer_softc * const sc = smw->smw_cookie;
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if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
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TIMER_SET_CLEAR(sc, TMR1_PTV_REG, 0, TMR_PTV_EN);
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tegra_car_wdt_enable(1, false);
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} else {
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if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
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sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
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} else if (smw->smw_period == 0 || smw->smw_period > 1000) {
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return EINVAL;
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} else {
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sc->sc_smw.smw_period = smw->smw_period;
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}
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u_int tval = (sc->sc_smw.smw_period * 1000000) / 2;
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TIMER_WRITE(sc, TMR1_PTV_REG,
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TMR_PTV_EN | TMR_PTV_PER | __SHIFTIN(tval, TMR_PTV_VAL));
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TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR);
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tegra_car_wdt_enable(1, true);
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}
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return 0;
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}
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static int
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tegra_timer_wdt_tickle(struct sysmon_wdog *smw)
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{
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struct tegra_timer_softc * const sc = smw->smw_cookie;
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TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR);
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return 0;
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}
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81
sys/arch/arm/nvidia/tegra_timerreg.h
Normal file
81
sys/arch/arm/nvidia/tegra_timerreg.h
Normal file
@ -0,0 +1,81 @@
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/* $NetBSD: tegra_timerreg.h,v 1.1 2015/05/30 13:25:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
|
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*
|
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_TEGRA_TIMERREG_H
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#define _ARM_TEGRA_TIMERREG_H
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#define TMR1_PTV_REG 0x00
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#define TMR1_PCR_REG 0x04
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#define TMR2_PTV_REG 0x08
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#define TMR2_PCR_REG 0x0c
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#define TMR3_PTV_REG 0x50
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#define TMR3_PCR_REG 0x54
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#define TMR4_PTV_REG 0x58
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#define TMR4_PCR_REG 0x5c
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#define TMR5_PTV_REG 0x60
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#define TMR5_PCR_REG 0x64
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#define TMR6_PTV_REG 0x68
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#define TMR6_PCR_REG 0x6c
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#define TMR7_PTV_REG 0x70
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#define TMR7_PCR_REG 0x74
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#define TMR8_PTV_REG 0x78
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#define TMR8_PCR_REG 0x7c
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#define TMR9_PTV_REG 0x80
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#define TMR9_PCR_REG 0x84
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#define TMR0_PTV_REG 0x88
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#define TMR0_PCR_REG 0x8c
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#define TMR_PTV_EN __BIT(31)
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#define TMR_PTV_PER __BIT(30)
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#define TMR_PTV_VAL __BITS(28,0)
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#define TMR_PCR_INTR_CLR __BIT(30)
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#define TMR_PCR_VAL __BITS(28,0)
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#define WDT0_CONFIG_REG 0x100
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#define WDT0_STATUS_REG 0x104
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#define WDT0_COMMAND_REG 0x108
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#define WDT0_UNLOCK_PATTERN_REG 0x10c
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#define WDT1_CONFIG_REG 0x100
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#define WDT1_STATUS_REG 0x104
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#define WDT1_COMMAND_REG 0x108
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#define WDT1_UNLOCK_PATTERN_REG 0x10c
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#define WDT2_CONFIG_REG 0x100
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#define WDT2_STATUS_REG 0x104
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#define WDT2_COMMAND_REG 0x108
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#define WDT2_UNLOCK_PATTERN_REG 0x10c
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#define WDT3_CONFIG_REG 0x100
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#define WDT3_STATUS_REG 0x104
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#define WDT3_COMMAND_REG 0x108
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#define WDT3_UNLOCK_PATTERN_REG 0x10c
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#define WDT4_CONFIG_REG 0x100
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#define WDT4_STATUS_REG 0x104
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#define WDT4_COMMAND_REG 0x108
|
||||
#define WDT4_UNLOCK_PATTERN_REG 0x10c
|
||||
|
||||
#endif /* _ARM_TEGRA_TIMERREG_H */
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: tegra_var.h,v 1.19 2015/05/18 21:03:36 jmcneill Exp $ */
|
||||
/* $NetBSD: tegra_var.h,v 1.20 2015/05/30 13:25:55 jmcneill Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
|
||||
@ -106,6 +106,7 @@ void tegra_car_utmip_enable(u_int);
|
||||
void tegra_car_hdmi_enable(u_int);
|
||||
int tegra_car_dc_enable(u_int);
|
||||
void tegra_car_host1x_enable(void);
|
||||
void tegra_car_wdt_enable(u_int, bool);
|
||||
|
||||
struct tegra_gpio_pin;
|
||||
struct tegra_gpio_pin *tegra_gpio_acquire(const char *, u_int);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#
|
||||
# $NetBSD: JETSONTK1,v 1.23 2015/05/29 23:18:30 jmcneill Exp $
|
||||
# $NetBSD: JETSONTK1,v 1.24 2015/05/30 13:25:55 jmcneill Exp $
|
||||
#
|
||||
# NVIDIA Jetson TK1 - Tegra K1 development kit
|
||||
# https://developer.nvidia.com/jetson-tk1
|
||||
@ -51,6 +51,9 @@ tegragpio0 at tegraio? # GPIO
|
||||
gpio* at gpiobus?
|
||||
gpiorfkill0 at gpio23 offset 7 mask 1 # WF_EN
|
||||
|
||||
# Timers
|
||||
tegratimer0 at tegraio? # Timers
|
||||
|
||||
# MPIO / Pinmux
|
||||
tegrampio0 at tegraio? # MPIO
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user