From d322684f55e8174869b4fe98f264e8ee79c6df38 Mon Sep 17 00:00:00 2001 From: thorpej Date: Mon, 6 Oct 2003 16:06:05 +0000 Subject: [PATCH] Add support for the i80312 and i80321 I2C controllers. --- sys/arch/arm/xscale/files.i80312 | 10 +- sys/arch/arm/xscale/files.i80321 | 9 +- sys/arch/arm/xscale/i80312.c | 80 +++++++++- sys/arch/arm/xscale/i80312_i2c.c | 121 ++++++++++++++ sys/arch/arm/xscale/i80312var.h | 17 +- sys/arch/arm/xscale/i80321.c | 12 +- sys/arch/arm/xscale/i80321_gpio.c | 89 +++++++++++ sys/arch/arm/xscale/i80321_i2c.c | 126 +++++++++++++++ sys/arch/arm/xscale/i80321reg.h | 7 +- sys/arch/arm/xscale/i80321var.h | 8 +- sys/arch/arm/xscale/iopi2c.c | 257 ++++++++++++++++++++++++++++++ sys/arch/arm/xscale/iopi2creg.h | 77 +++++++++ sys/arch/arm/xscale/iopi2cvar.h | 55 +++++++ sys/arch/evbarm/conf/IQ31244 | 5 +- sys/arch/evbarm/conf/IQ80310 | 6 +- sys/arch/evbarm/conf/IQ80321 | 5 +- 16 files changed, 866 insertions(+), 18 deletions(-) create mode 100644 sys/arch/arm/xscale/i80312_i2c.c create mode 100644 sys/arch/arm/xscale/i80321_gpio.c create mode 100644 sys/arch/arm/xscale/i80321_i2c.c create mode 100644 sys/arch/arm/xscale/iopi2c.c create mode 100644 sys/arch/arm/xscale/iopi2creg.h create mode 100644 sys/arch/arm/xscale/iopi2cvar.h diff --git a/sys/arch/arm/xscale/files.i80312 b/sys/arch/arm/xscale/files.i80312 index 9317eca7cb92..30f6337bfe02 100644 --- a/sys/arch/arm/xscale/files.i80312 +++ b/sys/arch/arm/xscale/files.i80312 @@ -1,13 +1,19 @@ -# $NetBSD: files.i80312,v 1.6 2002/08/01 19:55:03 thorpej Exp $ +# $NetBSD: files.i80312,v 1.7 2003/10/06 16:06:05 thorpej Exp $ # # Configuration info for Intel i80312 Companion I/O support # file arch/arm/xscale/i80312_mem.c -device iopxs: pcibus, bus_space_generic +device iopxs {}: pcibus, bus_space_generic # Board-specific front-end provides attachment. file arch/arm/xscale/i80312.c iopxs file arch/arm/xscale/i80312_gpio.c iopxs file arch/arm/xscale/i80312_pci.c iopxs file arch/arm/xscale/i80312_space.c iopxs + +# I2C controller unit +device iopiic: i2cbus +attach iopiic at iopxs +file arch/arm/xscale/i80312_i2c.c iopiic +file arch/arm/xscale/iopi2c.c iopiic diff --git a/sys/arch/arm/xscale/files.i80321 b/sys/arch/arm/xscale/files.i80321 index d048f7d1e332..d66d462c811c 100644 --- a/sys/arch/arm/xscale/files.i80321 +++ b/sys/arch/arm/xscale/files.i80321 @@ -1,4 +1,4 @@ -# $NetBSD: files.i80321,v 1.11 2003/01/25 02:12:22 thorpej Exp $ +# $NetBSD: files.i80321,v 1.12 2003/10/06 16:06:05 thorpej Exp $ # # Configuration info for Intel i80321 XScale I/O Processor support # @@ -13,6 +13,7 @@ file arch/arm/xscale/xscale_pmc.c perfctrs device iopxs {}: pcibus, bus_space_generic # Board-specific front-end provides attachment. file arch/arm/xscale/i80321.c iopxs +file arch/arm/xscale/i80321_gpio.c iopxs file arch/arm/xscale/i80321_pci.c iopxs file arch/arm/xscale/i80321_space.c iopxs @@ -22,6 +23,12 @@ attach iopaau at iopxs file arch/arm/xscale/i80321_aau.c iopaau file arch/arm/xscale/iopaau.c iopaau +# I2C controller unit +device iopiic: i2cbus +attach iopiic at iopxs +file arch/arm/xscale/i80321_i2c.c iopiic +file arch/arm/xscale/iopi2c.c iopiic + # Watchdog timer device iopwdog: sysmon_wdog attach iopwdog at iopxs diff --git a/sys/arch/arm/xscale/i80312.c b/sys/arch/arm/xscale/i80312.c index a8c681f31a51..9be5f7064e43 100644 --- a/sys/arch/arm/xscale/i80312.c +++ b/sys/arch/arm/xscale/i80312.c @@ -1,4 +1,4 @@ -/* $NetBSD: i80312.c,v 1.15 2003/07/15 00:24:53 lukem Exp $ */ +/* $NetBSD: i80312.c,v 1.16 2003/10/06 16:06:05 thorpej Exp $ */ /* * Copyright (c) 2001, 2002 Wasabi Systems, Inc. @@ -40,7 +40,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: i80312.c,v 1.15 2003/07/15 00:24:53 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: i80312.c,v 1.16 2003/10/06 16:06:05 thorpej Exp $"); #include #include @@ -68,9 +68,25 @@ struct bus_space i80312_bs_tag; struct i80312_softc *i80312_softc; static void i80312_pci_dma_init(struct i80312_softc *); +static void i80312_local_dma_init(struct i80312_softc *); +static int i80312_iopxs_print(void *, const char *); static int i80312_pcibus_print(void *, const char *); +/* Built-in devices. */ +static const struct iopxs_device { + const char *id_name; + bus_addr_t id_offset; + bus_size_t id_size; +} iopxs_devices[] = { +/* { "iopaau", I80312_AAU_BASE, I80312_AAU_SIZE }, */ +/* { "iopdma", I80312_DMA_BASE0, I80312_DMA_SIZE }, */ +/* { "iopdma", I80312_DMA_BASE1, I80312_DMA_SIZE }, */ + { "iopiic", I80312_IIC_BASE, I80312_IIC_SIZE }, +/* { "iopmu", I80312_MSG_BASE, I80312_MU_SIZE }, */ + { NULL, 0, 0 } +}; + /* * i80312_attach: * @@ -80,6 +96,8 @@ void i80312_attach(struct i80312_softc *sc) { struct pcibus_attach_args pba; + const struct iopxs_device *id; + struct iopxs_attach_args ia; uint32_t atucr; pcireg_t preg; @@ -266,6 +284,21 @@ i80312_attach(struct i80312_softc *sc) /* Initialize the DMA tags. */ i80312_pci_dma_init(sc); + i80312_local_dma_init(sc); + + /* + * Attach all the IOP built-ins. + */ + for (id = iopxs_devices; id->id_name != NULL; id++) { + ia.ia_name = id->id_name; + ia.ia_st = sc->sc_st; + ia.ia_sh = sc->sc_sh; + ia.ia_dmat = &sc->sc_local_dmat; + ia.ia_offset = id->id_offset; + ia.ia_size = id->id_size; + + (void) config_found(&sc->sc_dev, &ia, i80312_iopxs_print); + } /* * Attach the PCI bus. @@ -291,6 +324,19 @@ i80312_attach(struct i80312_softc *sc) (void) config_found(&sc->sc_dev, &pba, i80312_pcibus_print); } +/* + * i80312_iopxs_print: + * + * Autoconfiguration cfprint routine when attaching + * to the "iopxs" device. + */ +static int +i80312_iopxs_print(void *aux, const char *pnp) +{ + + return (QUIET); +} + /* * i80312_pcibus_print: * @@ -344,3 +390,33 @@ i80312_pci_dma_init(struct i80312_softc *sc) dmat->_dmamem_unmap = _bus_dmamem_unmap; dmat->_dmamem_mmap = _bus_dmamem_mmap; } + +/* + * i80312_local_dma_init: + * + * Initialize the local DMA tag. + */ +static void +i80312_local_dma_init(struct i80312_softc *sc) +{ + bus_dma_tag_t dmat = &sc->sc_local_dmat; + + dmat->_ranges = NULL; + dmat->_nranges = 0; + + dmat->_dmamap_create = _bus_dmamap_create; + dmat->_dmamap_destroy = _bus_dmamap_destroy; + dmat->_dmamap_load = _bus_dmamap_load; + dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf; + dmat->_dmamap_load_uio = _bus_dmamap_load_uio; + dmat->_dmamap_load_raw = _bus_dmamap_load_raw; + dmat->_dmamap_unload = _bus_dmamap_unload; + dmat->_dmamap_sync_pre = _bus_dmamap_sync; + dmat->_dmamap_sync_post = NULL; + + dmat->_dmamem_alloc = _bus_dmamem_alloc; + dmat->_dmamem_free = _bus_dmamem_free; + dmat->_dmamem_map = _bus_dmamem_map; + dmat->_dmamem_unmap = _bus_dmamem_unmap; + dmat->_dmamem_mmap = _bus_dmamem_mmap; +} diff --git a/sys/arch/arm/xscale/i80312_i2c.c b/sys/arch/arm/xscale/i80312_i2c.c new file mode 100644 index 000000000000..beeaec910f74 --- /dev/null +++ b/sys/arch/arm/xscale/i80312_i2c.c @@ -0,0 +1,121 @@ +/* $NetBSD: i80312_i2c.c,v 1.1 2003/10/06 16:06:05 thorpej Exp $ */ + +/* + * Copyright (c) 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Intel i80321 I/O Processor I2C Controller Unit support. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD: i80312_i2c.c,v 1.1 2003/10/06 16:06:05 thorpej Exp $"); + +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include + +#include +#include + +static int +iic312_match(struct device *parent, struct cfdata *cf, void *aux) +{ + struct iopxs_attach_args *ia = aux; + + if (strcmp(cf->cf_name, ia->ia_name) == 0) + return (1); + + return (0); +} + +static void +iic312_attach(struct device *parent, struct device *self, void *aux) +{ + struct iopiic_softc *sc = (void *) self; + struct iopxs_attach_args *ia = aux; + int error; + + aprint_naive(": I2C controller\n"); + aprint_normal(": I2C controller\n"); + + sc->sc_st = ia->ia_st; + if ((error = bus_space_subregion(sc->sc_st, ia->ia_sh, + ia->ia_offset, ia->ia_size, + &sc->sc_sh)) != 0) { + aprint_error("%s: unable to subregion registers, error = %d\n", + sc->sc_dev.dv_xname, error); + return; + } + + /* XXX Reset the I2C unit? */ + + lockinit(&sc->sc_buslock, PRIBIO|PCATCH, "iopiiclk", 0, 0); + + /* XXX We don't currently use interrupts. Fix this some day. */ +#if 0 + sc->sc_ih = i80321_intr_establish(ICU_INT_I2C, IPL_BIO, + iopiic_intr, sc); + if (sc->sc_ih == NULL) { + aprint_error("%s: unable to establish interrupt handler\n", + sc->sc_dev.dv_xname); + return; + } +#endif + + /* + * Enable the I2C unit as a master running at 100.0 KHz (ICCR=0x1f4 + * per p.12-8 of the i80312 developer's manual). + * No, we do not support slave mode. + */ + sc->sc_icr = IIC_ICR_GCD | IIC_ICR_UE | IIC_ICR_SCLE; + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 0); + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICCR, 0x1f4); + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ISAR, 0); + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, sc->sc_icr); + + iopiic_attach(sc); +} + +CFATTACH_DECL(iopiic, sizeof(struct iopiic_softc), + iic312_match, iic312_attach, NULL, NULL); diff --git a/sys/arch/arm/xscale/i80312var.h b/sys/arch/arm/xscale/i80312var.h index 4818a937b0bb..19e4310a2fd6 100644 --- a/sys/arch/arm/xscale/i80312var.h +++ b/sys/arch/arm/xscale/i80312var.h @@ -1,4 +1,4 @@ -/* $NetBSD: i80312var.h,v 1.7 2002/08/01 19:55:03 thorpej Exp $ */ +/* $NetBSD: i80312var.h,v 1.8 2003/10/06 16:06:05 thorpej Exp $ */ /* * Copyright (c) 2001, 2002 Wasabi Systems, Inc. @@ -158,6 +158,21 @@ struct i80312_softc { /* GPIO state */ uint8_t sc_gpio_dir; /* GPIO pin direction (1 == output) */ uint8_t sc_gpio_val; /* GPIO output pin value */ + + /* DMA tag for local devices. */ + struct arm32_bus_dma_tag sc_local_dmat; +}; + +/* + * Arguments used to attach IOP built-ins. + */ +struct iopxs_attach_args { + const char *ia_name; /* name of device */ + bus_space_tag_t ia_st; /* space tag */ + bus_space_handle_t ia_sh;/* handle of IOP base */ + bus_dma_tag_t ia_dmat; /* DMA tag */ + bus_addr_t ia_offset; /* offset of device from IOP base */ + bus_size_t ia_size; /* size of sub-device */ }; extern struct bus_space i80312_bs_tag; diff --git a/sys/arch/arm/xscale/i80321.c b/sys/arch/arm/xscale/i80321.c index 3401de872ae4..7d3ee176cba0 100644 --- a/sys/arch/arm/xscale/i80321.c +++ b/sys/arch/arm/xscale/i80321.c @@ -1,4 +1,4 @@ -/* $NetBSD: i80321.c,v 1.14 2003/07/15 00:24:53 lukem Exp $ */ +/* $NetBSD: i80321.c,v 1.15 2003/10/06 16:06:05 thorpej Exp $ */ /* * Copyright (c) 2002 Wasabi Systems, Inc. @@ -40,7 +40,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: i80321.c,v 1.14 2003/07/15 00:24:53 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: i80321.c,v 1.15 2003/10/06 16:06:05 thorpej Exp $"); #include #include @@ -75,9 +75,11 @@ static const struct iopxs_device { bus_size_t id_size; } iopxs_devices[] = { { "iopaau", VERDE_AAU_BASE, VERDE_AAU_SIZE }, - { "iopdma", VERDE_DMA_BASE0, VERDE_DMA_CHSIZE }, - { "iopdma", VERDE_DMA_BASE1, VERDE_DMA_CHSIZE }, - { "iopssp", VERDE_SSP_BASE, VERDE_SSP_SIZE }, +/* { "iopdma", VERDE_DMA_BASE0, VERDE_DMA_CHSIZE }, */ +/* { "iopdma", VERDE_DMA_BASE1, VERDE_DMA_CHSIZE }, */ + { "iopiic", VERDE_I2C_BASE0, VERDE_I2C_CHSIZE }, + { "iopiic", VERDE_I2C_BASE1, VERDE_I2C_CHSIZE }, +/* { "iopssp", VERDE_SSP_BASE, VERDE_SSP_SIZE }, */ { "iopmu", VERDE_MU_BASE, VERDE_MU_SIZE }, { "iopwdog", 0, 0 }, { NULL, 0, 0 } diff --git a/sys/arch/arm/xscale/i80321_gpio.c b/sys/arch/arm/xscale/i80321_gpio.c new file mode 100644 index 000000000000..c79423c7d914 --- /dev/null +++ b/sys/arch/arm/xscale/i80321_gpio.c @@ -0,0 +1,89 @@ +/* $NetBSD: i80321_gpio.c,v 1.1 2003/10/06 16:06:05 thorpej Exp $ */ + +/* + * Copyright (c) 2001, 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Intel i80321 I/O Processor general purpose I/O support. + */ + +#include +#include + +#include + +#include +#include + +/* + * i80321_gpio_set_direction: + * + * Set the direction of the indicated GPIO pins (1 == output). + */ +void +i80321_gpio_set_direction(uint8_t which, uint8_t val) +{ + struct i80321_softc *sc = i80321_softc; + + sc->sc_gpio_dir = (sc->sc_gpio_dir & ~which) | val; + bus_space_write_1(sc->sc_st, sc->sc_sh, ICU_GPOE, ~sc->sc_gpio_dir); +} + +/* + * i80321_gpio_set_val: + * + * Set the value of the indicated GPIO pins. + */ +void +i80321_gpio_set_val(uint8_t which, uint8_t val) +{ + struct i80321_softc *sc = i80321_softc; + + sc->sc_gpio_val = (sc->sc_gpio_val & ~which) | val; + bus_space_write_1(sc->sc_st, sc->sc_sh, ICU_GPOD, sc->sc_gpio_val); +} + +/* + * i80321_gpio_get_val: + * + * Get the current state of the GPIO pins. + */ +uint8_t +i80321_gpio_get_val(void) +{ + struct i80321_softc *sc = i80321_softc; + + return (bus_space_read_1(sc->sc_st, sc->sc_sh, ICU_GPID)); +} diff --git a/sys/arch/arm/xscale/i80321_i2c.c b/sys/arch/arm/xscale/i80321_i2c.c new file mode 100644 index 000000000000..d285209425aa --- /dev/null +++ b/sys/arch/arm/xscale/i80321_i2c.c @@ -0,0 +1,126 @@ +/* $NetBSD: i80321_i2c.c,v 1.1 2003/10/06 16:06:05 thorpej Exp $ */ + +/* + * Copyright (c) 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Intel i80321 I/O Processor I2C Controller Unit support. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD: i80321_i2c.c,v 1.1 2003/10/06 16:06:05 thorpej Exp $"); + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include +#include + +static int +iic321_match(struct device *parent, struct cfdata *cf, void *aux) +{ + struct iopxs_attach_args *ia = aux; + + if (strcmp(cf->cf_name, ia->ia_name) == 0) + return (1); + + return (0); +} + +static void +iic321_attach(struct device *parent, struct device *self, void *aux) +{ + struct iopiic_softc *sc = (void *) self; + struct iopxs_attach_args *ia = aux; + int error; + uint8_t gpio_bits; + + aprint_naive(": I2C controller\n"); + aprint_normal(": I2C controller\n"); + + sc->sc_st = ia->ia_st; + if ((error = bus_space_subregion(sc->sc_st, ia->ia_sh, + ia->ia_offset, ia->ia_size, + &sc->sc_sh)) != 0) { + aprint_error("%s: unable to subregion registers, error = %d\n", + sc->sc_dev.dv_xname, error); + return; + } + + gpio_bits = (ia->ia_offset == VERDE_I2C_BASE0) ? + (1U << 7) | (1U << 6) : (1U << 5) | (1U << 4); + i80321_gpio_set_val(gpio_bits, 0); + i80321_gpio_set_direction(gpio_bits, 0); + + /* XXX Reset the I2C unit? */ + + lockinit(&sc->sc_buslock, PRIBIO|PCATCH, "iopiiclk", 0, 0); + + /* XXX We don't currently use interrupts. Fix this some day. */ +#if 0 + sc->sc_ih = i80321_intr_establish((ia->ia_offset == VERDE_I2C_BASE0) ? + ICU_INT_I2C0 : ICU_INT_I2C1, IPL_BIO, iopiic_intr, sc); + if (sc->sc_ih == NULL) { + aprint_error("%s: unable to establish interrupt handler\n", + sc->sc_dev.dv_xname); + return; + } +#endif + + /* + * Enable the I2C unit as a master. + * No, we do not support slave mode. + */ + sc->sc_icr = IIC_ICR_GCD | IIC_ICR_UE | IIC_ICR_SCLE; + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, 0); + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ISAR, 0); + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, sc->sc_icr); + + iopiic_attach(sc); +} + +CFATTACH_DECL(iopiic, sizeof(struct iopiic_softc), + iic321_match, iic321_attach, NULL, NULL); diff --git a/sys/arch/arm/xscale/i80321reg.h b/sys/arch/arm/xscale/i80321reg.h index f5c0b5e59f81..299069525007 100644 --- a/sys/arch/arm/xscale/i80321reg.h +++ b/sys/arch/arm/xscale/i80321reg.h @@ -1,4 +1,4 @@ -/* $NetBSD: i80321reg.h,v 1.11 2003/07/28 16:53:31 thorpej Exp $ */ +/* $NetBSD: i80321reg.h,v 1.12 2003/10/06 16:06:05 thorpej Exp $ */ /* * Copyright (c) 2002 Wasabi Systems, Inc. @@ -67,7 +67,7 @@ #define VERDE_EXTMEM_BASE 0x90020000UL #define VERDE_PMMR_BASE 0xffffe000UL -#define VERDE_PMMR_SIZE 0x00000900UL +#define VERDE_PMMR_SIZE 0x00001700UL /* * Peripheral Memory Mapped Registers. Defined as offsets @@ -98,7 +98,10 @@ #define VERDE_AAU_SIZE 0x0100 #define VERDE_I2C_BASE 0x1680 +#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) +#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20) #define VERDE_I2C_SIZE 0x0080 +#define VERDE_I2C_CHSIZE 0x0020 /* * Address Translation Unit diff --git a/sys/arch/arm/xscale/i80321var.h b/sys/arch/arm/xscale/i80321var.h index 4ce37b092ed2..edd6163b0366 100644 --- a/sys/arch/arm/xscale/i80321var.h +++ b/sys/arch/arm/xscale/i80321var.h @@ -1,7 +1,7 @@ -/* $NetBSD: i80321var.h,v 1.7 2003/02/06 03:16:49 briggs Exp $ */ +/* $NetBSD: i80321var.h,v 1.8 2003/10/06 16:06:06 thorpej Exp $ */ /* - * Copyright (c) 2002 Wasabi Systems, Inc. + * Copyright (c) 2002, 2003 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. @@ -167,6 +167,10 @@ void i80321_intr_init(void); void *i80321_intr_establish(int, int, int (*)(void *), void *); void i80321_intr_disestablish(void *); +void i80321_gpio_set_direction(uint8_t, uint8_t); +void i80321_gpio_set_val(uint8_t, uint8_t); +uint8_t i80321_gpio_get_val(void); + void i80321_bs_init(bus_space_tag_t, void *); void i80321_io_bs_init(bus_space_tag_t, void *); void i80321_mem_bs_init(bus_space_tag_t, void *); diff --git a/sys/arch/arm/xscale/iopi2c.c b/sys/arch/arm/xscale/iopi2c.c new file mode 100644 index 000000000000..9dcd24e56785 --- /dev/null +++ b/sys/arch/arm/xscale/iopi2c.c @@ -0,0 +1,257 @@ +/* $NetBSD: iopi2c.c,v 1.1 2003/10/06 16:06:06 thorpej Exp $ */ + +/* + * Copyright (c) 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Intel i80321 I/O Processor I2C Controller Unit support. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD: iopi2c.c,v 1.1 2003/10/06 16:06:06 thorpej Exp $"); + +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +static int iopiic_acquire_bus(void *, int); +static void iopiic_release_bus(void *, int); + +static int iopiic_send_start(void *, int); +static int iopiic_send_stop(void *, int); +static int iopiic_initiate_xfer(void *, uint16_t, int); +static int iopiic_read_byte(void *, uint8_t *, int); +static int iopiic_write_byte(void *, uint8_t, int); + +void +iopiic_attach(struct iopiic_softc *sc) +{ + struct i2cbus_attach_args iba; + + sc->sc_i2c.ic_cookie = sc; + sc->sc_i2c.ic_acquire_bus = iopiic_acquire_bus; + sc->sc_i2c.ic_release_bus = iopiic_release_bus; + sc->sc_i2c.ic_send_start = iopiic_send_start; + sc->sc_i2c.ic_send_stop = iopiic_send_stop; + sc->sc_i2c.ic_initiate_xfer = iopiic_initiate_xfer; + sc->sc_i2c.ic_read_byte = iopiic_read_byte; + sc->sc_i2c.ic_write_byte = iopiic_write_byte; + + iba.iba_name = "iic"; + iba.iba_tag = &sc->sc_i2c; + (void) config_found(&sc->sc_dev, &iba, iicbus_print); +} + +static int +iopiic_acquire_bus(void *cookie, int flags) +{ + struct iopiic_softc *sc = cookie; + + /* XXX What should we do for the polling case? */ + if (flags & I2C_F_POLL) + return (0); + + return (lockmgr(&sc->sc_buslock, LK_EXCLUSIVE, NULL)); +} + +static void +iopiic_release_bus(void *cookie, int flags) +{ + struct iopiic_softc *sc = cookie; + + /* XXX See above. */ + if (flags & I2C_F_POLL) + return; + + (void) lockmgr(&sc->sc_buslock, LK_RELEASE, NULL); +} + +#define IOPIIC_TIMEOUT 100 /* protocol timeout, in uSecs */ + +static int +iopiic_wait(struct iopiic_softc *sc, int bit, int flags) +{ + uint32_t isr; + int timeout, error=0; + + /* XXX We never sleep, we always poll. Fix me. */ + + /* + * For some reason, we seem to run into problems if we poll + * the ISR while the transfer is in progress--at least on the + * i80312. The condition that we're looking for never seems + * to appear on a read, and it's not clear why; perhaps reads + * of the I2C register file interfere with its proper operation? + * For now, just delay for a while up front. + * + * We _really_ need this to be interrupt-driven, but a problem + * with that is that the i80312 has no way to mask interrupts... + * So we need to deal with that. For DMA and AAU, too, for that + * matter. + * Note that delay(100) doesn't quite work on the npwr w/ m41t00. + */ + delay(110); + for (timeout = IOPIIC_TIMEOUT; timeout != 0; timeout--) { + isr = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_ISR); + if (isr & (bit | IIC_ISR_BED)) + break; + delay(1); + } + + if (isr & (IIC_ISR_BED | (bit & IIC_ISR_ALD))) + error = EIO; + else if (isr & (bit & ~IIC_ISR_ALD)) + error = 0; + else + error = ETIMEDOUT; + + if (error) + printf("%s: iopiic_wait, (%08x) error %d: ISR = 0x%08x\n", + sc->sc_dev.dv_xname, bit, error, isr); + + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ISR, 0); + + return (error); +} + +static int +iopiic_send_start(void *cookie, int flags) +{ + struct iopiic_softc *sc = cookie; + + /* + * This may only work in conjunction with a data transfer; + * we might need to un-export the "start" primitive. + */ + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, + sc->sc_icr | IIC_ICR_START); + delay(IOPIIC_TIMEOUT); + + return (0); +} + +static int +iopiic_send_stop(void *cookie, int flags) +{ + struct iopiic_softc *sc = cookie; + + /* + * The STOP bit is only used in conjunction with + * a data transfer, so we need to use MA in this + * case. + * + * Consider adding an I2C_F_STOP so we can + * do a read-with-STOP and write-with-STOP. + */ + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, + sc->sc_icr | IIC_ICR_MA); + delay(IOPIIC_TIMEOUT); + + return (0); +} + +static int +iopiic_initiate_xfer(void *cookie, uint16_t addr, int flags) +{ + struct iopiic_softc *sc = cookie; + int error, rd_req = (flags & I2C_F_READ) != 0; + uint32_t idbr; + + /* We only support 7-bit addressing. */ + if ((addr & 0x78) == 0x78) + return (EINVAL); + + idbr = (addr << 1) | (rd_req ? 1 : 0); + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, idbr); + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, + sc->sc_icr | IIC_ICR_START | IIC_ICR_TB); + + error = iopiic_wait(sc, IIC_ISR_ITE, flags); +#if 0 + if (error) + printf("%s: failed to initiate %s xfer\n", sc->sc_dev.dv_xname, + rd_req ? "read" : "write"); +#endif + return (error); +} + +static int +iopiic_read_byte(void *cookie, uint8_t *bytep, int flags) +{ + struct iopiic_softc *sc = cookie; + int error, last_byte = (flags & I2C_F_LAST) != 0, + send_stop = (flags & I2C_F_STOP) != 0; + + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, + sc->sc_icr | IIC_ICR_TB | (last_byte ? IIC_ICR_NACK : 0) | + (send_stop ? IIC_ICR_STOP : 0)); + if ((error = iopiic_wait(sc, IIC_ISR_IRF | IIC_ISR_ALD, flags)) == 0) + *bytep = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_IDBR); +#if 0 + if (error) + printf("%s: read byte failed\n", sc->sc_dev.dv_xname); +#endif + + return (error); +} + +static int +iopiic_write_byte(void *cookie, uint8_t byte, int flags) +{ + struct iopiic_softc *sc = cookie; + int error, send_stop = (flags & I2C_F_STOP) != 0; + + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, byte); + bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR, + sc->sc_icr | IIC_ICR_TB | (send_stop ? IIC_ICR_STOP : 0)); + error = iopiic_wait(sc, IIC_ISR_ITE | IIC_ISR_ALD, flags); + +#if 0 + if (error) + printf("%s: write byte failed\n", sc->sc_dev.dv_xname); +#endif + + return (error); +} diff --git a/sys/arch/arm/xscale/iopi2creg.h b/sys/arch/arm/xscale/iopi2creg.h new file mode 100644 index 000000000000..f49e962c394d --- /dev/null +++ b/sys/arch/arm/xscale/iopi2creg.h @@ -0,0 +1,77 @@ +/* $NetBSD: iopi2creg.h,v 1.1 2003/10/06 16:06:06 thorpej Exp $ */ + +/* + * Copyright (c) 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_XSCALE_IOPIICREG_H_ +#define _ARM_XSCALE_IOPIICREG_H_ + +#define IIC_ICR 0x00 /* i2c control register */ +#define IIC_ISR 0x04 /* i2c status register */ +#define IIC_ISAR 0x08 /* i2c slave address register */ +#define IIC_IDBR 0x0c /* i2c data buffer register */ +#define IIC_ICCR 0x10 /* i2c clock control register (i80312 only) */ +#define IIC_IBMR 0x14 /* i2c bus monitor register */ + +#define IIC_ICR_FM (1U << 15) /* fast mode (i80321 only) */ +#define IIC_ICR_RESET (1U << 14) /* i2c unit reset */ +#define IIC_ICR_SADIE (1U << 13) /* slave addr det int en */ +#define IIC_ICR_ALDIE (1U << 12) /* arb loss det int en */ +#define IIC_ICR_SSDIE (1U << 11) /* slave stop det in en */ +#define IIC_ICR_BEIE (1U << 10) /* bus error int en */ +#define IIC_ICR_IRFIE (1U << 9) /* IDBR Rx full int en */ +#define IIC_ICR_ITEIE (1U << 8) /* IDBR Tx empty int en */ +#define IIC_ICR_GCD (1U << 7) /* general call disable */ +#define IIC_ICR_UE (1U << 6) /* i2c unit enable */ +#define IIC_ICR_SCLE (1U << 5) /* SCL master enable */ +#define IIC_ICR_MA (1U << 4) /* abort as master */ +#define IIC_ICR_TB (1U << 3) /* transfer byte */ +#define IIC_ICR_NACK (1U << 2) /* 0=ACK, 1=NACK */ +#define IIC_ICR_STOP (1U << 1) /* initiate STOP condition */ +#define IIC_ICR_START (1U << 0) /* initiate START condition */ + +#define IIC_ISR_BED (1U << 10) /* bus error detected */ +#define IIC_ISR_SAD (1U << 9) /* slave address detected */ +#define IIC_ISR_GCAD (1U << 8) /* general call addr detected */ +#define IIC_ISR_IRF (1U << 7) /* IDBR Rx full */ +#define IIC_ISR_ITE (1U << 6) /* IDBR Tx empty */ +#define IIC_ISR_ALD (1U << 5) /* arb loss detected */ +#define IIC_ISR_SSD (1U << 4) /* slave STOP detected */ +#define IIC_ISR_IBB (1U << 3) /* i2c bus busy */ +#define IIC_ISR_UB (1U << 2) /* unit busy */ +#define IIC_ISR_NACK (1U << 1) /* NACK received */ +#define IIC_ISR_RW (1U << 0) /* 0=mt/sr, 1=mr/st */ + +#endif /* _ARM_XSCALE_IOPIICREG_H_ */ diff --git a/sys/arch/arm/xscale/iopi2cvar.h b/sys/arch/arm/xscale/iopi2cvar.h new file mode 100644 index 000000000000..0db3375ca302 --- /dev/null +++ b/sys/arch/arm/xscale/iopi2cvar.h @@ -0,0 +1,55 @@ +/* $NetBSD: iopi2cvar.h,v 1.1 2003/10/06 16:06:06 thorpej Exp $ */ + +/* + * Copyright (c) 2003 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_XSCALE_IOPIICVAR_H_ +#define _ARM_XSCALE_IOPIICVAR_H_ + +struct iopiic_softc { + struct device sc_dev; + bus_space_tag_t sc_st; + bus_space_handle_t sc_sh; + + void *sc_ih; + + struct i2c_controller sc_i2c; + struct lock sc_buslock; + uint32_t sc_icr; +}; + +void iopiic_attach(struct iopiic_softc *sc); + +#endif /* _ARM_XSCALE_IOPIICVAR_H_ */ diff --git a/sys/arch/evbarm/conf/IQ31244 b/sys/arch/evbarm/conf/IQ31244 index 193fd74134dd..56a876ee0ec2 100644 --- a/sys/arch/evbarm/conf/IQ31244 +++ b/sys/arch/evbarm/conf/IQ31244 @@ -1,4 +1,4 @@ -# $NetBSD: IQ31244,v 1.5 2003/09/13 13:30:06 chris Exp $ +# $NetBSD: IQ31244,v 1.6 2003/10/06 16:06:06 thorpej Exp $ # # IQ31244 -- Intel IQ31244 Evaluation Board Kernel # @@ -151,6 +151,9 @@ com0 at obio? addr 0xfe800000 xint 1 # on-board TI 165C50 UART iopxs* at mainbus? iopaau* at iopxs? # Application Accelerator Unit +iopiic* at iopxs? # I2C Controller Unit(s) +iic0 at iopiic? +iic1 at iopiic? iopwdog* at iopxs? # Watchdog timer pci0 at iopxs? bus ? # PCI/PCI-X support diff --git a/sys/arch/evbarm/conf/IQ80310 b/sys/arch/evbarm/conf/IQ80310 index 1747337c4fe3..e3af4286f648 100644 --- a/sys/arch/evbarm/conf/IQ80310 +++ b/sys/arch/evbarm/conf/IQ80310 @@ -1,4 +1,4 @@ -# $NetBSD: IQ80310,v 1.26 2003/09/13 13:30:06 chris Exp $ +# $NetBSD: IQ80310,v 1.27 2003/10/06 16:06:06 thorpej Exp $ # # IQ80310 -- Intel IQ80310 Evaluation Board Kernel # @@ -157,6 +157,10 @@ com1 at obio? addr 0xfe800000 xint3 2 # i80312 Companion I/O support iopxs* at mainbus? + +iopiic* at iopxs? # I2C Controller Unit +iic* at iopiic? + pci0 at iopxs? bus ? # PCI-PCI bridges diff --git a/sys/arch/evbarm/conf/IQ80321 b/sys/arch/evbarm/conf/IQ80321 index b1cd9029ddab..b71554c0fb84 100644 --- a/sys/arch/evbarm/conf/IQ80321 +++ b/sys/arch/evbarm/conf/IQ80321 @@ -1,4 +1,4 @@ -# $NetBSD: IQ80321,v 1.21 2003/09/13 13:30:06 chris Exp $ +# $NetBSD: IQ80321,v 1.22 2003/10/06 16:06:06 thorpej Exp $ # # IQ80321 -- Intel IQ80321 Evaluation Board Kernel # @@ -153,6 +153,9 @@ com0 at obio? addr 0xfe800000 xint 1 # on-board TI 165C50 UART iopxs* at mainbus? iopaau* at iopxs? # Application Accelerator Unit +iopiic* at iopxs? # I2C Controller Unit(s) +iic0 at iopiic? +iic1 at iopiic? iopwdog* at iopxs? # Watchdog timer pci0 at iopxs? bus ? # PCI/PCI-X support