From d268a0e37f295b8135c17f11c592d2da802e995f Mon Sep 17 00:00:00 2001 From: fvdl Date: Sun, 20 Apr 2003 22:53:56 +0000 Subject: [PATCH] Add register definitions for the PCI-X capability. --- sys/dev/pci/pcireg.h | 66 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h index 6004d4479167..34f2420f6f0b 100644 --- a/sys/dev/pci/pcireg.h +++ b/sys/dev/pci/pcireg.h @@ -1,4 +1,4 @@ -/* $NetBSD: pcireg.h,v 1.40 2003/03/25 21:56:20 thorpej Exp $ */ +/* $NetBSD: pcireg.h,v 1.41 2003/04/20 22:53:56 fvdl Exp $ */ /* * Copyright (c) 1995, 1996, 1999, 2000 @@ -450,6 +450,70 @@ typedef u_int8_t pci_revision_t; #define PCI_PMCSR_STATE_D2 0x02 #define PCI_PMCSR_STATE_D3 0x03 +/* + * PCI-X capability. + */ + +/* + * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit + * word at the capability). + */ +#define PCI_PCIX_CMD 0x02 +#define PCI_PCIX_CMD_PERR_RECOVER 0x0001 +#define PCI_PCIX_CMD_RELAXED_ORDER 0x0002 +#define PCI_PCIX_CMD_BYTECNT_MASK 0x000c +#define PCI_PCIX_CMD_BCNT_512 0x0000 +#define PCI_PCIX_CMD_BCNT_1024 0x0004 +#define PCI_PCIX_CMD_BCNT_2048 0x0008 +#define PCI_PCIX_CMD_BCNT_4096 0x000c +#define PCI_PCIX_CMD_SPLTRANS_MASK 0x0070 +#define PCI_PCIX_CMD_SPLTRANS_1 0x0000 +#define PCI_PCIX_CMD_SPLTRANS_2 0x0010 +#define PCI_PCIX_CMD_SPLTRANS_3 0x0020 +#define PCI_PCIX_CMD_SPLTRANS_4 0x0030 +#define PCI_PCIX_CMD_SPLTRANS_8 0x0040 +#define PCI_PCIX_CMD_SPLTRANS_12 0x0050 +#define PCI_PCIX_CMD_SPLTRANS_16 0x0060 +#define PCI_PCIX_CMD_SPLTRANS_32 0x0070 + +/* + * Status. 32 bits at offset 4. + */ +#define PCI_PCIX_STATUS 0x04 +#define PCI_PCIX_STATUS_FN_MASK 0x00000007 +#define PCI_PCIX_STATUS_DEV_MASK 0x000000f8 +#define PCI_PCIX_STATUS_BUS_MASK 0x0000ff00 +#define PCI_PCIX_STATUS_64BIT 0x00010000 +#define PCI_PCIX_STATUS_133 0x00020000 +#define PCI_PCIX_STATUS_SPLDISC 0x00040000 +#define PCI_PCIX_STATUS_SPLUNEX 0x00080000 +#define PCI_PCIX_STATUS_DEVCPLX 0x00100000 +#define PCI_PCIX_STATUS_MAXB_MASK 0x00600000 +#define PCI_PCIX_STATUS_MAXB_512 0x00000000 +#define PCI_PCIX_STATUS_MAXB_1024 0x00200000 +#define PCI_PCIX_STATUS_MAXB_2048 0x00400000 +#define PCI_PCIX_STATUS_MAXB_4096 0x00600000 +#define PCI_PCIX_STATUS_MAXST_MASK 0x03800000 +#define PCI_PCIX_STATUS_MAXST_1 0x00000000 +#define PCI_PCIX_STATUS_MAXST_2 0x00800000 +#define PCI_PCIX_STATUS_MAXST_3 0x01000000 +#define PCI_PCIX_STATUS_MAXST_4 0x01800000 +#define PCI_PCIX_STATUS_MAXST_8 0x02000000 +#define PCI_PCIX_STATUS_MAXST_12 0x02800000 +#define PCI_PCIX_STATUS_MAXST_16 0x03000000 +#define PCI_PCIX_STATUS_MAXST_32 0x03800000 +#define PCI_PCIX_STATUS_MAXRS_MASK 0x1c000000 +#define PCI_PCIX_STATUS_MAXRS_1K 0x00000000 +#define PCI_PCIX_STATUS_MAXRS_2K 0x04000000 +#define PCI_PCIX_STATUS_MAXRS_4K 0x08000000 +#define PCI_PCIX_STATUS_MAXRS_8K 0x0c000000 +#define PCI_PCIX_STATUS_MAXRS_16K 0x10000000 +#define PCI_PCIX_STATUS_MAXRS_32K 0x14000000 +#define PCI_PCIX_STATUS_MAXRS_64K 0x18000000 +#define PCI_PCIX_STATUS_MAXRS_128K 0x1c000000 +#define PCI_PCIX_STATUS_SCERR 0x20000000 + + /* * Interrupt Configuration Register; contains interrupt pin and line. */