Only use 32-bit addresses for all accesses that don't bypass the MMU.
Makes SBus work again.
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eeh
parent
b18cd8346c
commit
d26027dd5b
@ -1,4 +1,4 @@
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/* $NetBSD: ctlreg.h,v 1.16 2000/06/08 17:43:24 eeh Exp $ */
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/* $NetBSD: ctlreg.h,v 1.17 2000/06/10 20:51:43 eeh Exp $ */
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/*
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* Copyright (c) 1996-1999 Eduardo Horvath
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@ -471,10 +471,8 @@
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"r" ((unsigned long)(loc)), "r" (_loc_hi), \
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"r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
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" rdpr %%pstate,%1; wrpr %1,8,%%pstate; " \
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" or %0,%2,%0; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
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"=&r" (_lduba_v), "=&r" (_pstate) : \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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_lduba_v; \
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@ -530,10 +528,8 @@
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"r" ((unsigned long)(loc)), "r" (_loc_hi), \
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"r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \
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" sllx %3,32,%0; wrpr %1,8,%%pstate; " \
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" or %0,%2,%0; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
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"=&r" (_lduha_v), "=&r" (_pstate) : \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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_lduha_v; \
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@ -611,10 +607,8 @@
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"r" ((unsigned long)(loc)), "r" (_loc_hi), \
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"r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \
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" sllx %3,32,%0; wrpr %1,8,%%pstate;" \
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" or %0,%2,%0; lda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
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"=&r" (_lda_v), "=&r" (_pstate) : \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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_lda_v; \
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@ -632,10 +626,8 @@
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"r" ((unsigned long)(loc)), "r" (_loc_hi), \
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"r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0;" \
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" rdpr %%pstate,%1; wrpr %1,8,%%pstate;" \
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" or %0,%2,%0; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
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"=&r" (_lda_v), "=&r" (_pstate) : \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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_lda_v; \
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@ -692,10 +684,9 @@
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"=&r" (_lda_v), "=&r" (_pstate) : \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
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" rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; ldda [%0]%%asi,%0;" \
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" wrpr %1,0,%%pstate" : "=&r" (_lda_v), "=&r" (_pstate) : \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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_lda_v; \
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})
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@ -731,8 +722,7 @@
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"r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
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" or %0,%2,%0; ldxa [%0]%%asi,%0; " \
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" srlx %0,32,%1; srl %0,0,%0;" : \
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" or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
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"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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@ -775,11 +765,18 @@
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#define ldxa(loc, asi) ({ \
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register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; rdpr %%pstate,%1;" \
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if (PHYS_ASI(asi)) { \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; rdpr %%pstate,%1;" \
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" or %0,%1,%0; wrpr %1,8,%%pstate; ldxa [%0]%%asi,%0; wrpr %1,0,%%pstate;" \
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" srlx %0,32,%1; srl %0,0,%0;" : \
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"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
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"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \
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})
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#endif
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@ -796,10 +793,18 @@
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#define stba(loc, asi, value) ({ \
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register int _loc_hi, _pstate; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
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if (PHYS_ASI(asi)) { \
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__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
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" or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
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"=&r" (_loc_hi), "=&r" (_pstate) : \
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"r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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"r" ((int)(value)), "r" ((unsigned long)(loc)), \
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"r" (_loc_hi), "r" (asi)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
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" or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : \
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"r" ((int)(value)), "r" ((unsigned long)(loc)), \
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"r" (_loc_hi), "r" (asi)); \
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} \
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})
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#endif
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@ -813,10 +818,18 @@
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#define stha(loc, asi, value) ({ \
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register int _loc_hi, _pstate; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
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if (PHYS_ASI(asi)) { \
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__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
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" or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
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"=&r" (_loc_hi), "=&r" (_pstate) : \
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"r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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"r" ((int)(value)), "r" ((unsigned long)(loc)), \
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"r" (_loc_hi), "r" (asi)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
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" or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : \
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"r" ((int)(value)), "r" ((unsigned long)(loc)), \
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"r" (_loc_hi), "r" (asi)); \
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} \
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})
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#endif
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@ -830,10 +843,18 @@ __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
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#define sta(loc, asi, value) ({ \
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register int _loc_hi, _pstate; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
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if (PHYS_ASI(asi)) { \
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__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
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" or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
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"=&r" (_loc_hi), "=&r" (_pstate) : \
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"r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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"r" ((int)(value)), "r" ((unsigned long)(loc)), \
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"r" (_loc_hi), "r" (asi)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
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" or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : \
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"r" ((int)(value)), "r" ((unsigned long)(loc)), \
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"r" (_loc_hi), "r" (asi)); \
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} \
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})
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#endif
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@ -847,10 +868,18 @@ __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
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#define stda(loc, asi, value) ({ \
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register int _loc_hi, _pstate; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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if (PHYS_ASI(asi)) { \
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__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; " \
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" or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
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"=&r" (_loc_hi), "=&r" (_pstate) : \
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"r" ((long long)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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"r" ((long long)(value)), "r" ((unsigned long)(loc)), \
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"r" (_loc_hi), "r" (asi)); \
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} else { \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
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" or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : \
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"r" ((long long)(value)), "r" ((unsigned long)(loc)), \
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"r" (_loc_hi), "r" (asi)); \
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} \
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})
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#endif
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@ -866,12 +895,20 @@ __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
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int _stxa_lo, _stxa_hi, _loc_hi; \
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_stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \
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_loc_hi = (((u_int64_t)(u_long)loc)>>32); \
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__asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " \
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if (PHYS_ASI(asi)) { \
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__asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " \
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" or %1,%3,%1; rdpr %%pstate,%3; or %0,%5,%0; wrpr %3,8,%%pstate; " \
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" stxa %1,[%0]%%asi; wrpr %3,0,%%pstate" : \
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"=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)): \
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"=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)): \
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"r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} else { \
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__asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " \
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" or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : \
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"=&r" (_loc_hi), "=&r" (_stxa_hi) : \
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"r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \
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"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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})
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#endif
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