Work around another problem (that causes horrible performance) on the 82547:
- Change the Tx:Rx on-chip RAM allocation ratio based on MTU: => 82547: > 8192 18K:22K, else 10K:30K => others: > 8192 24K:40K, else 16K:48K Values derived from Linux driver. - On the 82547, keep track of how much of the Tx FIFO has been used. When in half-duplex mode, don't let packets wrap around the FIFO ring buffer, because that causes the chip to croak. Detect this, stall the Tx queue, use a timer to wait for the packets to drain from the Tx FIFO, reset the internal FIFO pointers, and restart the Tx queue. Basic algorithm (and some magic numbers) derived from FreeBSD and Linux drivers.
This commit is contained in:
thorpej
parent
f911795b30
commit
d1c33ede84
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wm.c,v 1.77 2004/09/14 08:40:26 simonb Exp $ */
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/* $NetBSD: if_wm.c,v 1.78 2004/10/05 20:14:52 thorpej Exp $ */
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/*
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* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
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@ -47,7 +47,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.77 2004/09/14 08:40:26 simonb Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.78 2004/10/05 20:14:52 thorpej Exp $");
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#include "bpfilter.h"
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#include "rnd.h"
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@ -263,6 +263,7 @@ struct wm_softc {
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/* Event counters. */
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struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */
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struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */
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struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */
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struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */
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struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */
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struct evcnt sc_ev_rxintr; /* Rx interrupts */
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@ -298,6 +299,13 @@ struct wm_softc {
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int sc_txsnext; /* next free Tx job */
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int sc_txsdirty; /* dirty Tx jobs */
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/* These 5 variables are used only on the 82547. */
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int sc_txfifo_size; /* Tx FIFO size */
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int sc_txfifo_head; /* current head of FIFO */
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uint32_t sc_txfifo_addr; /* internal address of start of FIFO */
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int sc_txfifo_stall; /* Tx FIFO is stalled */
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struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */
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uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */
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uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */
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@ -320,6 +328,7 @@ struct wm_softc {
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uint32_t sc_txcw; /* prototype TXCW register */
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uint32_t sc_tipg; /* prototype TIPG register */
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uint32_t sc_fcrtl; /* prototype FCRTL register */
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uint32_t sc_pba; /* prototype PBA register */
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int sc_tbi_linkup; /* TBI link status */
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int sc_tbi_anstate; /* autonegotiation state */
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@ -365,6 +374,8 @@ do { \
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bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define CSR_WRITE_FLUSH(sc) \
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(void) CSR_READ((sc), WMREG_STATUS)
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#define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x)))
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#define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x)))
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@ -488,6 +499,8 @@ static void wm_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(wm, sizeof(struct wm_softc),
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wm_match, wm_attach, NULL, NULL);
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static void wm_82547_txfifo_stall(void *);
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/*
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* Devices supported by this driver.
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*/
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@ -843,6 +856,13 @@ wm_attach(struct device *parent, struct device *self, void *aux)
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sc->sc_bus_speed = 66;
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aprint_verbose("%s: Communication Streaming Architecture\n",
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sc->sc_dev.dv_xname);
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if (sc->sc_type == WM_T_82547) {
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callout_init(&sc->sc_txfifo_ch);
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callout_setfunc(&sc->sc_txfifo_ch,
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wm_82547_txfifo_stall, sc);
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aprint_verbose("%s: using 82547 Tx FIFO stall "
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"work-around\n", sc->sc_dev.dv_xname);
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}
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} else {
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reg = CSR_READ(sc, WMREG_STATUS);
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if (reg & STATUS_BUS64)
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@ -1200,6 +1220,8 @@ wm_attach(struct device *parent, struct device *self, void *aux)
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NULL, sc->sc_dev.dv_xname, "txsstall");
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evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
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NULL, sc->sc_dev.dv_xname, "txdstall");
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evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC,
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NULL, sc->sc_dev.dv_xname, "txfifo_stall");
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evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR,
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NULL, sc->sc_dev.dv_xname, "txdw");
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evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR,
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@ -1442,6 +1464,97 @@ wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
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printf("\t%d mbuf%s in chain\n", i, i == 1 ? "" : "s");
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}
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/*
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* wm_82547_txfifo_stall:
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*
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* Callout used to wait for the 82547 Tx FIFO to drain,
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* reset the FIFO pointers, and restart packet transmission.
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*/
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static void
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wm_82547_txfifo_stall(void *arg)
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{
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struct wm_softc *sc = arg;
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int s;
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s = splnet();
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if (sc->sc_txfifo_stall) {
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if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) &&
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CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
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CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
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/*
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* Packets have drained. Stop transmitter, reset
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* FIFO pointers, restart transmitter, and kick
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* the packet queue.
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*/
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uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
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CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
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CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr);
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CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr);
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CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr);
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CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr);
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CSR_WRITE(sc, WMREG_TCTL, tctl);
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CSR_WRITE_FLUSH(sc);
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sc->sc_txfifo_head = 0;
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sc->sc_txfifo_stall = 0;
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wm_start(&sc->sc_ethercom.ec_if);
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} else {
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/*
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* Still waiting for packets to drain; try again in
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* another tick.
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*/
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callout_schedule(&sc->sc_txfifo_ch, 1);
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}
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}
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splx(s);
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}
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/*
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* wm_82547_txfifo_bugchk:
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*
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* Check for bug condition in the 82547 Tx FIFO. We need to
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* prevent enqueueing a packet that would wrap around the end
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* if the Tx FIFO ring buffer, otherwise the chip will croak.
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*
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* We do this by checking the amount of space before the end
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* of the Tx FIFO buffer. If the packet will not fit, we "stall"
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* the Tx FIFO, wait for all remaining packets to drain, reset
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* the internal FIFO pointers to the beginning, and restart
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* transmission on the interface.
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*/
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#define WM_FIFO_HDR 0x10
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#define WM_82547_PAD_LEN 0x3e0
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static int
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wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
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{
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int space = sc->sc_txfifo_size - sc->sc_txfifo_head;
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int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
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/* Just return if already stalled. */
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if (sc->sc_txfifo_stall)
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return (1);
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if (sc->sc_mii.mii_media_active & IFM_FDX) {
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/* Stall only occurs in half-duplex mode. */
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goto send_packet;
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}
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if (len >= WM_82547_PAD_LEN + space) {
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sc->sc_txfifo_stall = 1;
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callout_schedule(&sc->sc_txfifo_ch, 1);
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return (1);
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}
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send_packet:
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sc->sc_txfifo_head += len;
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if (sc->sc_txfifo_head >= sc->sc_txfifo_size)
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sc->sc_txfifo_head -= sc->sc_txfifo_size;
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return (0);
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}
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/*
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* wm_start: [ifnet interface function]
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*
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break;
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}
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/*
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* Check for 82547 Tx FIFO bug. We need to do this
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* once we know we can transmit the packet, since we
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* do some internal FIFO space accounting here.
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*/
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if (sc->sc_type == WM_T_82547 &&
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wm_82547_txfifo_bugchk(sc, m0)) {
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DPRINTF(WM_DEBUG_TX,
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("%s: TX: 82547 Tx FIFO bug detected\n",
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sc->sc_dev.dv_xname));
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ifp->if_flags |= IFF_OACTIVE;
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bus_dmamap_unload(sc->sc_dmat, dmamap);
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WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall);
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break;
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}
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IFQ_DEQUEUE(&ifp->if_snd, m0);
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/*
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@ -2252,6 +2381,25 @@ wm_reset(struct wm_softc *sc)
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{
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int i;
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/*
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* Allocate on-chip memory according to the MTU size.
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* The Packet Buffer Allocation register must be written
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* before the chip is reset.
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*/
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if (sc->sc_type < WM_T_82547) {
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sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
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PBA_40K : PBA_48K;
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} else {
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sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
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PBA_22K : PBA_30K;
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sc->sc_txfifo_head = 0;
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sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
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sc->sc_txfifo_size =
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(PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
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sc->sc_txfifo_stall = 0;
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}
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CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
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switch (sc->sc_type) {
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case WM_T_82544:
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case WM_T_82540:
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@ -2593,6 +2741,10 @@ wm_stop(struct ifnet *ifp, int disable)
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/* Stop the one second clock. */
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callout_stop(&sc->sc_tick_ch);
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/* Stop the 82547 Tx FIFO stall check timer. */
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if (sc->sc_type == WM_T_82547)
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callout_stop(&sc->sc_txfifo_ch);
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if (sc->sc_flags & WM_F_HAS_MII) {
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/* Down the MII. */
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mii_down(&sc->sc_mii);
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