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Adapt to cpu_hatch_data changes

This commit is contained in:
matt 2011-06-29 06:13:08 +00:00
parent 4d00b9f7cd
commit d15a7b73fb
3 changed files with 31 additions and 31 deletions
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20
sys/arch/macppc/macppc/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.56 2011/06/05 17:03:16 matt Exp $ */
/* $NetBSD: cpu.c,v 1.57 2011/06/29 06:13:08 matt Exp $ */
/*-
* Copyright (c) 2001 Tsubai Masanari.
@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.56 2011/06/05 17:03:16 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.57 2011/06/29 06:13:08 matt Exp $");
#include "opt_ppcparam.h"
#include "opt_multiprocessor.h"
@ -218,7 +218,7 @@ md_setup_trampoline(volatile struct cpu_hatch_data *h, struct cpu_info *ci)
*(u_int *)EXC_RST = /* ba cpu_spinup_trampoline */
0x48000002 | (u_int)cpu_spinup_trampoline;
__syncicache((void *)EXC_RST, 0x100);
h->running = -1;
h->hatch_running = -1;
/* see if there's an OF property for the reset register */
sprintf(cpupath, "/cpus/@%x", ci->ci_cpuid);
@ -260,14 +260,14 @@ md_presync_timebase(volatile struct cpu_hatch_data *h)
tb = mftb();
tb += 100000; /* 3ms @ 33MHz */
h->tbu = tb >> 32;
h->tbl = tb & 0xffffffff;
h->hatch_tbu = tb >> 32;
h->hatch_tbl = tb & 0xffffffff;
while (tb > mftb())
;
__asm volatile ("sync; isync");
h->running = 0;
h->hatch_running = 0;
delay(500000);
} else
@ -291,7 +291,7 @@ md_start_timebase(volatile struct cpu_hatch_data *h)
* running.
*/
for (i = 0; i < 100000; i++)
if (h->running)
if (h->hatch_running)
break;
/* Start timebase. */
@ -308,9 +308,9 @@ md_sync_timebase(volatile struct cpu_hatch_data *h)
#ifdef OPENPIC
if (openpic_base) {
/* Sync timebase. */
u_int tbu = h->tbu;
u_int tbl = h->tbl;
while (h->running == -1)
u_int tbu = h->hatch_tbu;
u_int tbl = h->hatch_tbl;
while (h->hatch_running == -1)
;
__asm volatile ("sync; isync");
__asm volatile ("mttbl %0" :: "r"(0));

24
sys/arch/ofppc/ofppc/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.15 2011/06/05 17:03:16 matt Exp $ */
/* $NetBSD: cpu.c,v 1.16 2011/06/29 06:13:09 matt Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.15 2011/06/05 17:03:16 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.16 2011/06/29 06:13:09 matt Exp $");
#include "opt_ppcparam.h"
#include "opt_multiprocessor.h"
@ -241,7 +241,7 @@ md_setup_trampoline(volatile struct cpu_hatch_data *h, struct cpu_info *ci)
u_int msr;
msr = mfmsr();
h->running = -1;
h->hatch_running = -1;
cpu_spinstart_cpunum = ci->ci_cpuid;
__asm volatile("dcbf 0,%0"::"r"(&cpu_spinstart_cpunum):"memory");
@ -262,10 +262,10 @@ md_presync_timebase(volatile struct cpu_hatch_data *h)
/* Sync timebase. */
tb = mftb();
h->tbu = tb >> 32;
h->tbl = tb & 0xffffffff;
h->hatch_tbu = tb >> 32;
h->hatch_tbl = tb & 0xffffffff;
h->running = 0;
h->hatch_running = 0;
}
/* otherwise, the machine has no rtas, or if it does, things
* are pre-syncd, per PAPR v2.2. I don't have anything without
@ -284,7 +284,7 @@ md_start_timebase(volatile struct cpu_hatch_data *h)
* running.
*/
for (i = 0; i < 100000; i++)
if (h->running)
if (h->hatch_running)
break;
/* Start timebase. */
@ -293,17 +293,17 @@ md_start_timebase(volatile struct cpu_hatch_data *h)
}
/*
* We wait for h->running to become 0, and then we know that the time is
* frozen and h->tb is correct.
* We wait for h->hatch_running to become 0, and then we know that the time is
* frozen and h->hatch_tb is correct.
*/
void
md_sync_timebase(volatile struct cpu_hatch_data *h)
{
/* Sync timebase. */
u_int tbu = h->tbu;
u_int tbl = h->tbl;
while (h->running == -1)
u_int tbu = h->hatch_tbu;
u_int tbl = h->hatch_tbl;
while (h->hatch_running == -1)
;
__asm volatile ("sync; isync");
__asm volatile ("mttbl %0" :: "r"(0));

18
sys/arch/prep/prep/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.16 2011/06/05 17:03:17 matt Exp $ */
/* $NetBSD: cpu.c,v 1.17 2011/06/29 06:13:09 matt Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.16 2011/06/05 17:03:17 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.17 2011/06/29 06:13:09 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -105,7 +105,7 @@ md_setup_trampoline(volatile struct cpu_hatch_data *h, struct cpu_info *ci)
/* ba cpu_spinup_trampoline */
*(u_int *)EXC_RST = 0x48000002 | (u_int)cpu_spinup_trampoline;
__syncicache((void *)EXC_RST, 0x100);
h->running = -1;
h->hatch_running = -1;
/* Start secondary CPU. */
openpic_write(OPENPIC_PROC_INIT, (1 << 1));
@ -121,14 +121,14 @@ md_presync_timebase(volatile struct cpu_hatch_data *h)
tb = mftb();
tb += 100000; /* 3ms @ 33MHz */
h->tbu = tb >> 32;
h->tbl = tb & 0xffffffff;
h->hatch_tbu = tb >> 32;
h->hatch_tbl = tb & 0xffffffff;
while (tb > mftb())
;
__asm volatile ("sync; isync");
h->running = 0;
h->hatch_running = 0;
delay(500000);
}
@ -142,10 +142,10 @@ md_start_timebase(volatile struct cpu_hatch_data *h)
void
md_sync_timebase(volatile struct cpu_hatch_data *h)
{
u_int tbu = h->tbu;
u_int tbl = h->tbl;
u_int tbu = h->hatch_tbu;
u_int tbl = h->hatch_tbl;
while (h->running == -1)
while (h->hatch_running == -1)
;
__asm volatile ("sync; isync");