Before attach card, check card is detected.
This commit is contained in:
uch
parent
98e266aba9
commit
d136e27a9c
@ -1,4 +1,4 @@
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/* $NetBSD: it8368.c,v 1.3 1999/12/27 18:49:20 uch Exp $ */
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/* $NetBSD: it8368.c,v 1.4 1999/12/30 16:50:43 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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@ -53,45 +53,52 @@ void it8368e_attach __P((struct device*, struct device*, void*));
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int it8368_print __P((void*, const char*));
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int it8368_submatch __P((struct device*, struct cfdata*, void*));
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#define IT8368_LASTSTATE_PRESENT 0x0002
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#define IT8368_LASTSTATE_HALF 0x0001
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#define IT8368_LASTSTATE_EMPTY 0x0000
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struct it8368e_softc {
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struct device sc_dev;
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struct device *sc_pcmcia;
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tx_chipset_tag_t sc_tc;
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void *sc_ih;
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/* Register space */
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bus_space_tag_t sc_csregt;
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bus_space_handle_t sc_csregh;
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bus_space_tag_t sc_csregt;
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bus_space_handle_t sc_csregh;
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/* I/O, attribute space */
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bus_space_tag_t sc_csiot;
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bus_space_handle_t sc_csioh;
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bus_addr_t sc_csiobase;
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bus_size_t sc_csiosize;
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bus_space_tag_t sc_csiot;
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bus_space_handle_t sc_csioh;
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bus_addr_t sc_csiobase;
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bus_size_t sc_csiosize;
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/*
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* XXX theses means attribute memory. not memory space.
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* memory space is 0x64000000.
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*/
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bus_space_tag_t sc_csmemt;
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bus_space_handle_t sc_csmemh;
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bus_addr_t sc_csmembase;
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bus_size_t sc_csmemsize;
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bus_space_tag_t sc_csmemt;
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bus_space_handle_t sc_csmemh;
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bus_addr_t sc_csmembase;
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bus_size_t sc_csmemsize;
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/* Separate I/O and attribute space mode */
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int sc_fixattr;
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/* Card interrupt handler */
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int sc_card_irq;
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int (*sc_card_fun) __P((void*));
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void *sc_card_arg;
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void *sc_card_ih;
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int (*sc_card_fun) __P((void*));
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void *sc_card_arg;
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void *sc_card_ih;
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int sc_card_irq;
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/* Card status change */
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int sc_irq;
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void *sc_ih;
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int sc_laststate;
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};
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void it8368_init_socket __P((struct it8368e_softc*));
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void it8368_attach_socket __P((struct it8368e_softc*));
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void it8368_access __P((struct it8368e_softc*, int, int));
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int it8368_intr __P((void*));
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int it8368_insert_intr __P((void*));
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int it8368_remove_intr __P((void*));
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void it8368_intr_ack __P((struct it8368e_softc*));
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void it8368_dump __P((struct it8368e_softc*));
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int it8368_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t,
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@ -146,6 +153,11 @@ __inline void it8368_reg_write __P((bus_space_tag_t,
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bus_space_handle_t, int,
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u_int16_t));
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#define PRINTGPIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \
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IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, 1)
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#define PRINTMFIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \
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IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, 1)
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int
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it8368e_match(parent, cf, aux)
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struct device *parent;
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@ -168,7 +180,6 @@ it8368e_attach(parent, self, aux)
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bus_space_handle_t csregh;
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u_int16_t reg;
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printf(" ");
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sc->sc_tc = tc = ca->ca_tc;
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sc->sc_csregt = csregt = ca->ca_csreg.cstag;
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@ -180,10 +191,9 @@ it8368e_attach(parent, self, aux)
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sc->sc_csiosize = ca->ca_csio.cssize;
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#ifdef IT8368DEBUG
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printf("\t[Windows CE setting]\n");
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printf("\n\t[Windows CE setting]\n");
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it8368_dump(sc); /* print WindowsCE setting */
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#endif
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/* LHA[14:13] <= HA[14:13] */
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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reg &= ~IT8368_CTRL_ADDRSEL;
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@ -213,19 +223,6 @@ it8368e_attach(parent, self, aux)
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IT8368_PIN_BCRDRST;
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it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg);
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/* Interrupt */
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reg = IT8368_PIN_CRDSW | IT8368_PIN_CRDDET2 | IT8368_PIN_CRDDET1 |
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/* CSC */
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IT8368_PIN_BCRDRDY; /* #IREQ */
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/*
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* Enable negative edge only.
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*/
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
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it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0);
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/* Clear interrupt */
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it8368_intr_ack(sc);
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/*
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* Separate I/O and attribute memory region
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*/
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@ -236,13 +233,13 @@ it8368e_attach(parent, self, aux)
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if (IT8368_CTRL_FIXATTRIO & it8368_reg_read(csregt, csregh,
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IT8368_CTRL_REG)) {
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sc->sc_fixattr = 1;
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printf(":fix attr mode\n");
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printf(":fix attr mode");
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sc->sc_csmemt = sc->sc_csiot;
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sc->sc_csiosize /= 2;
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sc->sc_csmemsize = sc->sc_csiosize;
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sc->sc_csmembase = sc->sc_csiosize;
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} else {
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printf(":legacy attr mode\n");
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printf(":legacy attr mode");
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sc->sc_fixattr = 0;
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sc->sc_csmemt = sc->sc_csiot;
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sc->sc_csmemh = sc->sc_csmemh;
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@ -250,18 +247,15 @@ it8368e_attach(parent, self, aux)
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sc->sc_csmemsize = sc->sc_csiosize;
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}
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it8368_dump(sc);
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it8368_chip_socket_enable(sc);
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/*
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* CSC interrupt (IO bit1 5:8/1) XXX this is something bogus.
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*/
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tx_intr_establish(tc, ca->ca_irq1, IST_EDGE, IPL_TTY,
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it8368_insert_intr, sc);
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tx_intr_establish(tc, ca->ca_irq2, IST_EDGE, IPL_TTY,
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it8368_remove_intr, sc);
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/*
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* Card interrupt (3:2)
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*/
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/* Enable card and interrupt driving. */
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN);
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if (sc->sc_fixattr)
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reg |= IT8368_CTRL_FIXATTRIO;
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
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sc->sc_irq = ca->ca_irq1;
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sc->sc_card_irq = ca->ca_irq3;
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printf("\n");
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@ -294,66 +288,38 @@ it8368_reg_write(t, h, ofs, v)
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bus_space_write_2(t, h, ofs, val);
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}
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void
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it8368_intr_ack(sc)
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struct it8368e_softc *sc;
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{
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bus_space_tag_t csregt = sc->sc_csregt;
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bus_space_handle_t csregh = sc->sc_csregh;
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/* Clear interrupt */
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it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTSTAT_REG,
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it8368_reg_read(csregt, csregh,
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IT8368_GPIOPOSINTSTAT_REG));
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG,
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it8368_reg_read(csregt, csregh,
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IT8368_GPIONEGINTSTAT_REG));
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it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTSTAT_REG,
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it8368_reg_read(csregt, csregh,
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IT8368_MFIOPOSINTSTAT_REG));
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it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTSTAT_REG,
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it8368_reg_read(csregt, csregh,
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IT8368_MFIONEGINTSTAT_REG));
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}
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int
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it8368_insert_intr(arg)
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void *arg;
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{
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/* not coded yet */
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printf("[CSC insert]\n");
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return it8368_intr(arg);
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}
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int
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it8368_remove_intr(arg)
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void *arg;
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{
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/* not coded yet */
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printf("[CSC remove]\n");
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return it8368_intr(arg);
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}
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#define LIMIT_GPIO 12
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#define LIMIT_MFIO 10
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#define PRINTGPIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \
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IT8368_GPIO##m##_REG), 0, LIMIT_GPIO, #m, 1)
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#define PRINTMFIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \
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IT8368_MFIO##m##_REG), 0, LIMIT_MFIO, #m, 1)
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int
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it8368_intr(arg)
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void *arg;
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{
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struct it8368e_softc *sc = arg;
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bus_space_tag_t csregt = sc->sc_csregt;
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bus_space_handle_t csregh = sc->sc_csregh;
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u_int16_t reg;
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it8368_intr_ack(sc);
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reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG);
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/* Dispatch card interrupt handler */
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if (sc->sc_card_fun) {
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(*sc->sc_card_fun)(sc->sc_card_arg);
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if (reg & IT8368_PIN_BCRDRDY) {
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if (sc->sc_card_fun) {
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/* clear interrupt */
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it8368_reg_write(csregt, csregh,
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IT8368_GPIONEGINTSTAT_REG,
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IT8368_PIN_BCRDRDY);
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/* Dispatch card interrupt handler */
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(*sc->sc_card_fun)(sc->sc_card_arg);
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}
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} else if (reg & IT8368_PIN_CRDDET2) {
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG,
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IT8368_PIN_CRDDET2);
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printf("[CSC]\n");
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it8368_dump(sc);
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it8368_chip_socket_disable(sc);
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} else {
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printf("unknown it8368 interrupt\n");
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it8368_dump(sc);
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}
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return 0;
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}
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@ -391,8 +357,46 @@ it8368_attach_socket(sc)
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if ((sc->sc_pcmcia = config_found_sm((void*)sc, &paa, it8368_print,
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it8368_submatch))) {
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/* XXX Check card here XXX */
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pcmcia_card_attach(sc->sc_pcmcia);
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it8368_init_socket(sc);
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}
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}
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void
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it8368_init_socket(sc)
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struct it8368e_softc *sc;
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{
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bus_space_tag_t csregt = sc->sc_csregt;
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bus_space_handle_t csregh = sc->sc_csregh;
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u_int16_t reg;
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/*
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* set up the card to interrupt on card detect
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*/
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reg = IT8368_PIN_CRDDET2; /* CSC */
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/* enable negative edge */
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
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/* disable positive edge */
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it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0);
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sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq,
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IST_EDGE, IPL_BIO, it8368_intr, sc);
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if (sc->sc_ih == NULL) {
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printf("%s: can't establish interrupt\n",
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sc->sc_dev.dv_xname);
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return;
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}
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/*
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* if there's a card there, then attach it.
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*/
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reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG);
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if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) {
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sc->sc_laststate = IT8368_LASTSTATE_EMPTY;
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} else {
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pcmcia_card_attach(sc->sc_pcmcia);
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sc->sc_laststate = IT8368_LASTSTATE_PRESENT;
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}
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}
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@ -405,23 +409,26 @@ it8368_chip_intr_establish(pch, pf, ipl, ih_fun, ih_arg)
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void *ih_arg;
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{
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struct it8368e_softc *sc = (struct it8368e_softc*) pch;
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tx_chipset_tag_t tc = sc->sc_tc;
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bus_space_tag_t csregt = sc->sc_csregt;
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bus_space_handle_t csregh = sc->sc_csregh;
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u_int16_t reg;
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if (sc->sc_card_fun) {
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if (sc->sc_card_fun)
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panic("it8368_chip_intr_establish: "
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"duplicate card interrupt handler.");
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}
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sc->sc_card_fun = ih_fun;
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sc->sc_card_arg = ih_arg;
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if (!(sc->sc_card_ih =
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tx_intr_establish(tc, sc->sc_card_irq, IST_EDGE, IPL_BIO,
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it8368_intr, sc))) {
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printf("it8368_chip_intr_establish: can't establish.\n");
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return 0;
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}
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sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq,
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IST_EDGE, IPL_BIO, it8368_intr,
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sc);
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/* enable card interrupt */
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reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG);
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reg |= IT8368_PIN_BCRDRDY;
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
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return sc->sc_card_ih;
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}
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@ -431,15 +438,23 @@ it8368_chip_intr_disestablish(pch, ih)
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void *ih;
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{
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struct it8368e_softc *sc = (struct it8368e_softc*) pch;
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bus_space_tag_t csregt = sc->sc_csregt;
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bus_space_handle_t csregh = sc->sc_csregh;
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u_int16_t reg;
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if (!sc->sc_card_fun) {
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if (!sc->sc_card_fun)
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panic("it8368_chip_intr_disestablish:"
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"no handler established.");
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}
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assert(ih == sc->sc_card_ih);
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sc->sc_card_fun = 0;
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sc->sc_card_arg = 0;
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/* disable card interrupt */
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reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG);
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reg &= ~IT8368_PIN_BCRDRDY;
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
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tx_intr_disestablish(sc->sc_tc, ih);
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}
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@ -586,8 +601,6 @@ it8368_chip_io_map(pch, width, offset, size, pcihp, windowp)
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{
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struct it8368e_softc *sc = (struct it8368e_softc*) pch;
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assert(offset == 0); /* XXX */
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it8368_access(sc, 1, 0);
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DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", pcihp->ioh, offset,
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@ -625,12 +638,6 @@ it8368_chip_socket_enable(pch)
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bus_space_handle_t csregh = sc->sc_csregh;
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volatile u_int16_t reg;
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/* Disable card */
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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reg &= ~IT8368_CTRL_CARDEN;
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
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delay(20000);
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/* Power off */
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reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
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reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
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@ -659,21 +666,16 @@ it8368_chip_socket_enable(pch)
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*/
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delay((100 + 20 + 300) * 1000);
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/* Enable card and interrupt driving. */
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN);
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reg |= IT8368_CTRL_FIXATTRIO; /* XXX */
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
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delay(200000);
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/* Assert reset signal */
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reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
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reg |= IT8368_PIN_BCRDRST;
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it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
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/*
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* hold RESET at least 10us.
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*/
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delay(10);
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|
||||
/* Dessert reset signal */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
||||
reg &= ~IT8368_PIN_BCRDRST;
|
||||
@ -681,8 +683,6 @@ it8368_chip_socket_enable(pch)
|
||||
delay(20000);
|
||||
|
||||
DPRINTF(("socket enabled\n"));
|
||||
it8368_dump(sc);
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
@ -694,12 +694,6 @@ it8368_chip_socket_disable(pch)
|
||||
bus_space_handle_t csregh = sc->sc_csregh;
|
||||
u_int16_t reg;
|
||||
|
||||
/* Disable card */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
|
||||
reg &= ~IT8368_CTRL_CARDEN;
|
||||
it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
|
||||
delay(20000);
|
||||
|
||||
/* Power down */
|
||||
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
||||
reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
|
||||
@ -711,8 +705,8 @@ it8368_chip_socket_disable(pch)
|
||||
* wait 300ms until power fails (Tpf).
|
||||
*/
|
||||
delay(300 * 1000);
|
||||
|
||||
DPRINTF(("socket disabled\n"));
|
||||
it8368_dump(sc);
|
||||
}
|
||||
|
||||
void
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: it8368reg.h,v 1.1 1999/11/21 06:48:59 uch Exp $ */
|
||||
/* $NetBSD: it8368reg.h,v 1.2 1999/12/30 16:50:43 uch Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1999, by UCHIYAMA Yasushi
|
||||
@ -47,6 +47,9 @@
|
||||
#define IT8368_MFIONEGINTSTAT_REG 0x1e
|
||||
#define IT8368_CTRL_REG 0x20
|
||||
|
||||
#define IT8368_GPIO_MAX 12
|
||||
#define IT8368_MFIO_MAX 10
|
||||
|
||||
#define IT8368_GPIODATAOUT_MASK 0x1fff
|
||||
#define IT8368_MFIODATAOUT_MASK 0x07ff
|
||||
#define IT8368_GPIODIR_MASK 0x1fff
|
||||
|
||||
Loading…
Reference in New Issue
Block a user