Add an optionnal controller callback for channel reset. If the callback
is set to NULL, use the generic reset code. Use this to work around a bug in some Acer IDE controllers (like the one found in some sparc systems) where a controller disable/enable is required after a reset to avoid data corruption when Ultra-DMA is used. Workaround from opensolaris, thanks to Hiroki Sato for testing.
This commit is contained in:
bouyer
parent
c1494c99c6
commit
d1278fcba8
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@ -1,4 +1,4 @@
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/* $NetBSD: wdc.c,v 1.224 2005/06/19 18:14:27 bouyer Exp $ */
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/* $NetBSD: wdc.c,v 1.225 2005/08/06 22:07:24 bouyer Exp $ */
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/*
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* Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved.
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@ -70,7 +70,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.224 2005/06/19 18:14:27 bouyer Exp $");
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__KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.225 2005/08/06 22:07:24 bouyer Exp $");
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#ifndef ATADEBUG
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#define ATADEBUG
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@ -613,23 +613,10 @@ wdcprobe1(struct ata_channel *chp, int poll)
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delay(5000);
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#endif
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if (wdc->select)
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wdc->select(chp,0);
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bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM);
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delay(10); /* 400ns delay */
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/* assert SRST, wait for reset to complete */
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bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
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WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
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DELAY(1000);
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bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
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WDCTL_IDS | WDCTL_4BIT);
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wdc->reset(chp, RESET_POLL);
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DELAY(2000);
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(void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0);
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bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
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delay(10); /* 400ns delay */
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/* ACK interrupt in case there is one pending left (Promise ATA100) */
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if (wdc->irqack != NULL)
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wdc->irqack(chp);
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splx(s);
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ret_value = __wdcwait_reset(chp, ret_value, poll);
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@ -703,6 +690,9 @@ wdcattach(struct ata_channel *chp)
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wdc->datain_pio = wdc_datain_pio;
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if (wdc->dataout_pio == NULL)
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wdc->dataout_pio = wdc_dataout_pio;
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/* default reset method */
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if (wdc->reset == NULL)
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wdc->reset = wdc_do_reset;
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/* initialise global data */
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if (atac->atac_bustype_ata == NULL)
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@ -948,27 +938,8 @@ wdcreset(struct ata_channel *chp, int poll)
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struct wdc_softc *wdc = CHAN_TO_WDC(chp);
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struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
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int drv_mask1, drv_mask2;
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int s = 0;
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if (wdc->select)
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wdc->select(chp,0);
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if (poll != RESET_SLEEP)
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s = splbio();
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/* master */
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bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM);
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delay(10); /* 400ns delay */
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bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
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WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
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delay(2000);
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(void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0);
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bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
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WDCTL_4BIT | WDCTL_IDS);
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delay(10); /* 400ns delay */
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if (poll != RESET_SLEEP) {
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if (wdc->irqack)
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wdc->irqack(chp);
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splx(s);
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}
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wdc->reset(chp, poll);
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drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00;
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drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00;
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@ -987,6 +958,35 @@ wdcreset(struct ata_channel *chp, int poll)
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return (drv_mask1 != drv_mask2) ? 1 : 0;
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}
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void
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wdc_do_reset(struct ata_channel *chp, int poll)
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{
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struct wdc_softc *wdc = CHAN_TO_WDC(chp);
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struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
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int s = 0;
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if (poll != RESET_SLEEP)
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s = splbio();
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if (wdc->select)
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wdc->select(chp,0);
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/* master */
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bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM);
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delay(10); /* 400ns delay */
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/* assert SRST, wait for reset to complete */
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bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
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WDCTL_RST | WDCTL_IDS | WDCTL_4BIT);
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delay(2000);
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(void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0);
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bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
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WDCTL_4BIT | WDCTL_IDS);
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delay(10); /* 400ns delay */
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if (poll != RESET_SLEEP) {
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if (wdc->irqack)
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wdc->irqack(chp);
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splx(s);
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}
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}
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static int
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__wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll)
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{
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@ -1,4 +1,4 @@
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/* $NetBSD: wdcvar.h,v 1.82 2005/03/02 12:25:28 mycroft Exp $ */
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/* $NetBSD: wdcvar.h,v 1.83 2005/08/06 22:07:24 bouyer Exp $ */
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/*-
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* Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc.
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@ -101,6 +101,9 @@ struct wdc_softc {
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/* Optional callback to ack IRQ. */
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void (*irqack)(struct ata_channel *);
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/* Optional callback to perform a bus reset */
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void (*reset)(struct ata_channel *, int);
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/* overridden if the backend has a different data transfer method */
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void (*datain_pio)(struct ata_channel *, int, void *, size_t);
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void (*dataout_pio)(struct ata_channel *, int, void *, size_t);
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@ -144,6 +147,7 @@ void wdccommandshort(struct ata_channel *, int, int);
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void wdctimeout(void *arg);
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void wdc_reset_drive(struct ata_drive_datas *, int);
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void wdc_reset_channel(struct ata_channel *, int);
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void wdc_do_reset(struct ata_channel *, int);
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int wdc_exec_command(struct ata_drive_datas *, struct ata_command*);
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@ -1,4 +1,4 @@
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/* $NetBSD: aceride.c,v 1.15 2005/05/24 05:25:15 lukem Exp $ */
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/* $NetBSD: aceride.c,v 1.16 2005/08/06 22:07:24 bouyer Exp $ */
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/*
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* Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: aceride.c,v 1.15 2005/05/24 05:25:15 lukem Exp $");
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__KERNEL_RCSID(0, "$NetBSD: aceride.c,v 1.16 2005/08/06 22:07:24 bouyer Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -41,6 +41,8 @@ __KERNEL_RCSID(0, "$NetBSD: aceride.c,v 1.15 2005/05/24 05:25:15 lukem Exp $");
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_acer_reg.h>
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static int acer_pcib_match(struct pci_attach_args *);
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static void acer_do_reset(struct ata_channel *, int);
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static void acer_chip_map(struct pciide_softc*, struct pci_attach_args*);
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static void acer_setup_channel(struct ata_channel*);
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static int acer_pci_intr(void *);
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@ -48,7 +50,12 @@ static int acer_pci_intr(void *);
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static int aceride_match(struct device *, struct cfdata *, void *);
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static void aceride_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(aceride, sizeof(struct pciide_softc),
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struct aceride_softc {
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struct pciide_softc pciide_sc;
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struct pci_attach_args pcib_pa;
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};
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CFATTACH_DECL(aceride, sizeof(struct aceride_softc),
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aceride_match, aceride_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_acer_products[] = {
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@ -89,6 +96,21 @@ aceride_attach(struct device *parent, struct device *self, void *aux)
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}
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static int
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acer_pcib_match(struct pci_attach_args *pa)
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{
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/*
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* we need to access the PCI config space of the pcib, see
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* acer_do_reset()
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*/
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
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PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)
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return 1;
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return 0;
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}
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static void
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acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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@ -97,6 +119,7 @@ acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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pcireg_t cr, interface;
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bus_size_t cmdsize, ctlsize;
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pcireg_t rev = PCI_REVISION(pa->pa_class);
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struct aceride_softc *acer_sc = (struct aceride_softc *)sc;
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if (pciide_chipen(sc, pa) == 0)
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return;
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@ -154,6 +177,14 @@ acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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}
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wdc_allocate_regs(&sc->sc_wdcdev);
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if (rev == 0xC3) {
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/* install reset bug workaround */
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if (pci_find_device(&acer_sc->pcib_pa, acer_pcib_match) == 0) {
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printf("%s: WARNING: can't find pci-isa bridge\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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} else
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sc->sc_wdcdev.reset = acer_do_reset;
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}
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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@ -172,6 +203,30 @@ acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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}
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}
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static void
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acer_do_reset(struct ata_channel *chp, int poll)
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{
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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struct aceride_softc *acer_sc = (struct aceride_softc *)sc;
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u_int8_t reg;
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/*
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* From OpenSolaris: after a reset we need to disable/enable the
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* corresponding channel, or data corruption will occur in
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* UltraDMA modes
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*/
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wdc_do_reset(chp, poll);
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reg = pciide_pci_read(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag,
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ACER_PCIB_CTRL);
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printf("acer_do_reset reg 0x%x\n", reg);
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pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag,
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ACER_PCIB_CTRL, reg & ACER_PCIB_CTRL_ENCHAN(chp->ch_channel));
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delay(1000);
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pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag,
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ACER_PCIB_CTRL, reg);
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}
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static void
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acer_setup_channel(struct ata_channel *chp)
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{
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide_acer_reg.h,v 1.8 2005/02/27 00:27:33 perry Exp $ */
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/* $NetBSD: pciide_acer_reg.h,v 1.9 2005/08/06 22:07:24 bouyer Exp $ */
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/*
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* Copyright (c) 1999 Manuel Bouyer.
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@ -90,6 +90,10 @@
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#define ACER_0x79_REVC2_EN 0x4
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#define ACER_0x79_EN 0x2
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/* OpenSolaris: channel enable/disable in the PCI-ISA bridge */
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#define ACER_PCIB_CTRL 0x58
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#define ACER_PCIB_CTRL_ENCHAN(chan) (0x4 << (chan))
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/*
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* IDE bus frequency (1 byte)
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* This should be setup by the BIOS - can we rely on this ?
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