Overhaul the interrupt system to use hardware interrupts directly.
This commit is contained in:
eeh
parent
4da598993d
commit
d0f2652711
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@ -1,4 +1,4 @@
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# $NetBSD: WALNUT,v 1.5 2001/08/29 17:37:48 briggs Exp $
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# $NetBSD: WALNUT,v 1.6 2001/11/08 23:28:13 eeh Exp $
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#
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# GENERIC -- everything that's currently supported
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#
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@ -38,7 +38,7 @@ options DEBUG # expensive debugging checks/support
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options DDB # in-kernel debugger
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options DDB_HISTORY_SIZE=512 # enable history editing in DDB
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options TRAP_PANICWAIT
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options SYMTAB_SPACE=180000 # size for embedded symbol table
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options SYMTAB_SPACE=230000 # size for embedded symbol table
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makeoptions DEBUG="-g" # compile full symbol table
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@ -101,6 +101,7 @@ options PFIL_HOOKS # pfil(9) packet filter hooks
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options IPFILTER_LOG # ipmon(8) log support
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#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
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options NMBCLUSTERS=1024
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options NEW_PIPE
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# These options enable verbose messages for several subsystems.
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# Warning, these may compile large string tables into the kernel!
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@ -127,11 +128,11 @@ mainbus0 at root
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cpu0 at mainbus0
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# UARTs
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com0 at mainbus? addr 0xef600300 irq 5 # UIC IRQ 0
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com1 at mainbus? addr 0xef600400 irq 6 # UIC IRQ 1
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com0 at mainbus? addr 0xef600300 irq 0 # UIC IRQ 0
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com1 at mainbus? addr 0xef600400 irq 1 # UIC IRQ 1
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# Ethernet Media Access Controller
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emac0 at mainbus? addr 0xef600800 irq 9 # UIC IRQ 15
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emac0 at mainbus? addr 0xef600800 irq 15 # UIC IRQ 15
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# RTC
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dsrtc0 at mainbus? addr 0xf0000000
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@ -252,3 +253,4 @@ pseudo-device gif 4 # IPv[46] over IPv[46] tunnel (RFC1933)
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pseudo-device vlan # IEEE 802.1q encapsulation
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pseudo-device pty # pseudo-terminals
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pseudo-device rnd # /dev/random and in-kernel generator
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pseudo-device wsmux 2 # ick
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.2 2001/11/06 01:26:47 simonb Exp $ */
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/* $NetBSD: intr.h,v 1.3 2001/11/08 23:28:14 eeh Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -157,19 +157,26 @@ set_sint(pending)
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#define ICU_LEN 32
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#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN)
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#define IRQ_TO_MASK(x) (0x80000000UL >> (x))
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#define SINT_NET 0x20000000
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#define SINT_CLOCK 0x40000000
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#define SINT_SERIAL 0x80000000
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#define SPL_CLOCK 0x00000001
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/*
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* Interrupts 19-24 are not used by hardware and therefore useable
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* by us for softints.
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*/
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#define HWINT_MASK ~0x1fc0
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#define CNT_SINT_NET 19
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#define CNT_SINT_CLOCK 20
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#define CNT_SINT_SERIAL 21
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#define CNT_CLOCK 22
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#define CNT_STATCLOCK 23
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#define SINT_NET IRQ_TO_MASK(CNT_SINT_NET)
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#define SINT_CLOCK IRQ_TO_MASK(CNT_SINT_CLOCK)
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#define SINT_SERIAL IRQ_TO_MASK(CNT_SINT_SERIAL)
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#define SPL_CLOCK IRQ_TO_MASK(CNT_CLOCK)
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#define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_SERIAL)
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#define CNT_SINT_NET 29
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#define CNT_SINT_CLOCK 30
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#define CNT_SINT_SERIAL 31
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#define CNT_CLOCK 0
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#define CNT_STATCLOCK 32 /* note: make sure locore.S has enough space for it */
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#define splbio() splraise(imask[IPL_BIO])
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#define splnet() splraise(imask[IPL_NET])
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#define spltty() splraise(imask[IPL_TTY])
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_machdep.c,v 1.4 2001/10/29 23:38:35 thorpej Exp $ */
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/* $NetBSD: pci_machdep.c,v 1.5 2001/11/08 23:28:15 eeh Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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@ -171,13 +171,20 @@ pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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goto bad;
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}
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/*
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* We need to map the interrupt pin to the interrupt bit in the UIC
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* associated with it. This is highly machine-dependent.
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*/
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switch(dev) {
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case 1: *ihp = 4; break; /* Slot 3 Ext IRQ 3 */
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case 2: *ihp = 3; break; /* Slot 2 Ext IRQ 4 */
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case 3: *ihp = 2; break; /* Slot 1 Ext IRQ 5 */
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case 4: *ihp = 1; break; /* Slot 0 Ext IRQ 6 */
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case 1:
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case 2:
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case 3:
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case 4:
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*ihp = 27 + dev;
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break;
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default:
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printf("Hmm.. PCI device %d should not exist on this board\n", dev);
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printf("Hmm.. PCI device %d should not exist on this board\n",
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dev);
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goto bad;
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}
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return 0;
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@ -1,4 +1,4 @@
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/* $NetBSD: clock.c,v 1.1 2001/06/13 06:02:00 simonb Exp $ */
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/* $NetBSD: clock.c,v 1.2 2001/11/08 23:28:15 eeh Exp $ */
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/* $OpenBSD: clock.c,v 1.3 1997/10/13 13:42:53 pefo Exp $ */
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/*
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@ -101,7 +101,6 @@ decr_intr(struct clockframe *frame)
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lasttb = tick - xticks;
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intrcnt[CNT_CLOCK]++;
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pri = splclock();
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if (pri & SPL_CLOCK) {
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tickspending += nticks;
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@ -131,7 +130,6 @@ decr_intr(struct clockframe *frame)
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void
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cpu_initclocks(void)
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{
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ticks_per_intr = ticks_per_sec / hz;
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stathz = profhz = ticks_per_sec / (1<<PERIOD_POWER);
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printf("Setting PIT to %ld/%d = %ld\n", ticks_per_sec, hz, ticks_per_intr);
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@ -1,4 +1,4 @@
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/* $NetBSD: extintr.c,v 1.3 2001/11/06 01:26:48 simonb Exp $ */
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/* $NetBSD: extintr.c,v 1.4 2001/11/08 23:28:15 eeh Exp $ */
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/* $OpenBSD: isabus.c,v 1.1 1997/10/11 11:53:00 pefo Exp $ */
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/*
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@ -87,48 +87,6 @@
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#include <powerpc/spr.h>
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#include <powerpc/ibm4xx/dcr.h>
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#define GALAXY_INTR(x) (0x80000000U >> x)
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/*
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* Galaxy interrupt list
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*/
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#define GALAXY_INTR_UART0 GALAXY_INTR(0)
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#define GALAXY_INTR_UART1 GALAXY_INTR(1)
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#define GALAXY_INTR_IIC GALAXY_INTR(2)
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#define GALAXY_INTR_EMI GALAXY_INTR(3)
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#define GALAXY_INTR_PCI GALAXY_INTR(4)
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#define GALAXY_INTR_DMA0 GALAXY_INTR(5)
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#define GALAXY_INTR_DMA1 GALAXY_INTR(6)
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#define GALAXY_INTR_DMA2 GALAXY_INTR(7)
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#define GALAXY_INTR_DMA3 GALAXY_INTR(8)
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#define GALAXY_INTR_EWOL GALAXY_INTR(9)
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#define GALAXY_INTR_MSERR GALAXY_INTR(10)
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#define GALAXY_INTR_MTXE GALAXY_INTR(11)
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#define GALAXY_INTR_MRXE GALAXY_INTR(12)
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#define GALAXY_INTR_MTXD GALAXY_INTR(13)
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#define GALAXY_INTR_MRXD GALAXY_INTR(14)
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#define GALAXY_INTR_ETH GALAXY_INTR(15)
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#define GALAXY_INTR_PCISERR GALAXY_INTR(16)
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#define GALAXY_INTR_ECC GALAXY_INTR(17)
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#define GALAXY_INTR_PCIPM GALAXY_INTR(18)
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#define GALAXY_INTR_IRQ0 GALAXY_INTR(25)
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#define GALAXY_INTR_IRQ1 GALAXY_INTR(26)
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#define GALAXY_INTR_IRQ2 GALAXY_INTR(27)
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#define GALAXY_INTR_IRQ3 GALAXY_INTR(28)
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#define GALAXY_INTR_IRQ4 GALAXY_INTR(29)
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#define GALAXY_INTR_IRQ5 GALAXY_INTR(30)
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#define GALAXY_INTR_IRQ6 GALAXY_INTR(31)
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#define WALNUT_INTR_FPGA GALAXY_INTR_IRQ0
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#define WALNUT_INTR_SMI GALAXY_INTR_IRQ1
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#define WALNUT_INTR_PCI_S3 GALAXY_INTR_IRQ3
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#define WALNUT_INTR_PCI_S2 GALAXY_INTR_IRQ4
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#define WALNUT_INTR_PCI_S1 GALAXY_INTR_IRQ5
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#define WALNUT_INTR_PCI_S0 GALAXY_INTR_IRQ6
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static inline void galaxy_disable_irq(int irq);
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static inline void galaxy_enable_irq(int irq);
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static void intr_calculatemasks(void);
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@ -144,31 +102,6 @@ u_long imask[NIPL];
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static int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN];
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static struct intrhand *intrhand[ICU_LEN];
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/* SW irq# -> hw interrupt bitmask */
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static unsigned int galaxy_intr_map[] = {
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~0U, /* Reserved for clock interrupts */
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WALNUT_INTR_PCI_S0, /* PCI dev 1 irq1 */
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WALNUT_INTR_PCI_S1, /* PCI dev 2 irq2 */
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WALNUT_INTR_PCI_S2, /* PCI dev 3 irq3 */
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WALNUT_INTR_PCI_S3, /* PCI dev 4 irq4 */
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GALAXY_INTR_UART0, /* com0 irq5 */
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GALAXY_INTR_UART1, /* com1 irq6 */
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GALAXY_INTR_IIC, /* iic irq7 */
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~0U, /* irq8 - unused */
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GALAXY_INTR_EWOL, /* emac irq9 .. 15 */
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GALAXY_INTR_MSERR,
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GALAXY_INTR_MTXE,
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GALAXY_INTR_MRXE,
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GALAXY_INTR_MTXD,
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GALAXY_INTR_MRXD,
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GALAXY_INTR_ETH,
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WALNUT_INTR_FPGA, /* keyboard irq16 */
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WALNUT_INTR_SMI /* mouse irq17 */
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};
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#define GALAXY_INTR_SIZE (sizeof (galaxy_intr_map) / sizeof (galaxy_intr_map[0]))
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static uint32_t hwirq_mask; /* Mask sw interrupts in use */
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static int hw2swirq[32]; /* map MSR bit into sw irq#. */
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static inline int
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@ -193,18 +126,7 @@ fakeintr(void *arg)
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void
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intr_init(void)
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{
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int i;
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hwirq_mask = 0;
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for (i = 0; i < 32; i++)
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hw2swirq[i] = -1;
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for (i = 0; i < GALAXY_INTR_SIZE; i++) {
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if (galaxy_intr_map[i] == ~0U)
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continue;
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hwirq_mask |= (1 << i);
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hw2swirq[31 - cntlzw(galaxy_intr_map[i])] = i;
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}
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}
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/*
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@ -213,7 +135,7 @@ intr_init(void)
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void
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ext_intr(void)
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{
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int i, irq, bits_to_clear;
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int i, bits_to_clear;
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int r_imen, msr;
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int pcpl;
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struct intrhand *ih;
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@ -226,25 +148,19 @@ ext_intr(void)
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bits_to_clear = int_state;
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while (int_state) {
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i = 31 - cntlzw(int_state);
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int_state &= ~(1 << i);
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i = cntlzw(int_state);
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int_state &= ~IRQ_TO_MASK(i);
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irq = hw2swirq[i];
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if (irq == -1) {
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printf("Unexpected interrupt %d\n",i);
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continue;
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}
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r_imen = 1 << irq;
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r_imen = IRQ_TO_MASK(i);
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if ((pcpl & r_imen) != 0) {
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ipending |= r_imen; /* Masked! Mark this as pending */
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galaxy_disable_irq(irq);
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galaxy_disable_irq(i);
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} else {
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splraise(intrmask[irq]);
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splraise(intrmask[i]);
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asm volatile ("mtmsr %0" :: "r"(msr | PSL_EE));
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KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
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ih = intrhand[irq];
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ih = intrhand[i];
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while (ih) {
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(*ih->ih_fun)(ih->ih_arg);
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ih = ih->ih_next;
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@ -253,7 +169,7 @@ ext_intr(void)
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asm volatile ("mtmsr %0" :: "r"(msr));
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cpl = pcpl;
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uvmexp.intrs++;
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intrcnt[irq]++;
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intrcnt[i]++;
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}
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}
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mtdcr(DCR_UIC0_SR, bits_to_clear); /* Acknowledge all pending interrupts */
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@ -268,13 +184,8 @@ galaxy_disable_irq(int irq)
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{
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int mask, omask;
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if (irq >= GALAXY_INTR_SIZE)
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return;
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if (galaxy_intr_map[irq] == ~0U)
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return;
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mask = omask = mfdcr(DCR_UIC0_ER);
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mask &= ~galaxy_intr_map[irq];
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mask &= ~IRQ_TO_MASK(irq);
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if (mask == omask)
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return;
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mtdcr(DCR_UIC0_ER, mask);
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@ -288,13 +199,8 @@ galaxy_enable_irq(int irq)
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{
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int mask, omask;
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if (irq >= GALAXY_INTR_SIZE)
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return;
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if (galaxy_intr_map[irq] == ~0U)
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return;
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mask = omask = mfdcr(DCR_UIC0_ER);
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mask |= galaxy_intr_map[irq];
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mask |= IRQ_TO_MASK(irq);
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if (mask == omask)
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return;
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mtdcr(DCR_UIC0_ER, mask);
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@ -380,7 +286,7 @@ intr_establish(int irq, int type, int level, int (*ih_fun)(void *), void *ih_arg
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ih->ih_irq = irq;
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*p = ih;
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#ifdef IRQ_DEBUG
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printf("intr_establish: irq%d h=%p arg=%p\n",irq, ih_fun, ih_arg);
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printf("***** intr_establish: irq%d h=%p arg=%p\n",irq, ih_fun, ih_arg);
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#endif
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return (ih);
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}
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@ -441,7 +347,7 @@ intr_calculatemasks(void)
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register int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrlevel[irq] & (1 << level))
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irqs |= 1 << irq;
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irqs |= IRQ_TO_MASK(irq);
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imask[level] = irqs | SINT_MASK;
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}
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@ -502,7 +408,7 @@ intr_calculatemasks(void)
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/* And eventually calculate the complete masks. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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register int irqs = 1 << irq;
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register int irqs = IRQ_TO_MASK(irq);
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for (q = intrhand[irq]; q; q = q->ih_next)
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irqs |= imask[q->ih_level];
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intrmask[irq] = irqs;
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@ -535,11 +441,11 @@ do_pending_int(void)
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pcpl = cpl; /* Turn off all */
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again:
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while ((hwpend = ipending & ~pcpl & hwirq_mask)) {
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irq = 31 - cntlzw(hwpend);
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while ((hwpend = ipending & ~pcpl & HWINT_MASK)) {
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irq = cntlzw(hwpend);
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galaxy_enable_irq(irq);
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ipending &= ~(1 << irq);
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ipending &= ~IRQ_TO_MASK(irq);
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splraise(intrmask[irq]);
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asm volatile("mtmsr %0" :: "r"(emsr));
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@ -1,4 +1,4 @@
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/* $NetBSD: mainbus.c,v 1.5 2001/10/29 01:37:29 simonb Exp $ */
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/* $NetBSD: mainbus.c,v 1.6 2001/11/08 23:28:15 eeh Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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@ -94,14 +94,14 @@ const struct ppc405gp_dev {
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bus_addr_t addr;
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int irq;
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} ppc405gp_devs [] = {
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{ "com", UART0_BASE, 5 },
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{ "com", UART1_BASE, 6 },
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{ "com", UART0_BASE, 0 },
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{ "com", UART1_BASE, 1 },
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{ "dsrtc", NVRAM_BASE, -1 },
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{ "emac", EMAC0_BASE, 9 }, /* XXX: really irq 9..15 */
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{ "emac", EMAC0_BASE, 15 }, /* XXX: really irq 9..15 */
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{ "gpio", GPIO0_BASE, -1 },
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{ "i2c", IIC0_BASE, -1 },
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{ "wdog", -1, -1 },
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{ "pckbc", KEY_MOUSE_BASE, 16 }, /* XXX: really irq x..x+1 */
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{ "pckbc", KEY_MOUSE_BASE, 10 }, /* XXX: really irq x..x+1 */
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{ NULL }
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};
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