Optimised version of in_cksum(). This started life as the sparc one
and then had the inline assembly replaced.
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/* $NetBSD: in_cksum_arm32.c,v 1.1 1997/10/14 09:32:29 mark Exp $ */
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/*
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* ARM version:
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*
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* Copyright (c) 1997 Mark Brinicome
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* Copyright (c) 1997 Causality Limited
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*
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* Based on the sparc version.
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*/
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/*
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* Sparc version:
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*
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* Copyright (c) 1995 Zubin Dittia.
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* Copyright (c) 1995 Matthew R. Green.
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* Copyright (c) 1994 Charles Hannum.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)in_cksum.c 8.1 (Berkeley) 6/11/93
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*/
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#include <sys/param.h>
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#include <sys/mbuf.h>
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#include <netinet/in.h>
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/*
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* Checksum routine for Internet Protocol family headers.
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*
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* This routine is very heavily used in the network
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* code and should be modified for each CPU to be as fast as possible.
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*
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* ARM version.
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*/
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#define ADD64 __asm __volatile(" \n\
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ldmia %2!, {%3, %4, %5, %6} \n\
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adds %0,%0,%3; adcs %0,%0,%4 \n\
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adcs %0,%0,%5; adcs %0,%0,%6 \n\
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ldmia %2!, {%3, %4, %5, %6} \n\
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adcs %0,%0,%3; adcs %0,%0,%4 \n\
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adcs %0,%0,%5; adcs %0,%0,%6 \n\
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ldmia %2!, {%3, %4, %5, %6} \n\
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adcs %0,%0,%3; adcs %0,%0,%4 \n\
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adcs %0,%0,%5; adcs %0,%0,%6 \n\
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ldmia %2!, {%3, %4, %5, %6} \n\
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adcs %0,%0,%3; adcs %0,%0,%4 \n\
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adcs %0,%0,%5; adcs %0,%0,%6 \n\
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adcs %0,%0,#0\n" \
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: "=r" (sum) \
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: "0" (sum), "r" (w), "r" (tmp1), "r" (tmp2), "r" (tmp3), "r" (tmp4))
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#define ADD32 __asm __volatile(" \n\
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ldmia %2!, {%3, %4, %5, %6} \n\
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adds %0,%0,%3; adcs %0,%0,%4 \n\
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adcs %0,%0,%5; adcs %0,%0,%6 \n\
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ldmia %2!, {%3, %4, %5, %6} \n\
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adcs %0,%0,%3; adcs %0,%0,%4 \n\
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adcs %0,%0,%5; adcs %0,%0,%6 \n\
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adcs %0,%0,#0\n" \
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: "=r" (sum) \
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: "0" (sum), "r" (w), "r" (tmp1), "r" (tmp2), "r" (tmp3), "r" (tmp4))
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#define ADD16 __asm __volatile(" \n\
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ldmia %2!, {%3, %4, %5, %6} \n\
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adds %0,%0,%3; adcs %0,%0,%4 \n\
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adcs %0,%0,%5; adcs %0,%0,%6 \n\
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adcs %0,%0,#0\n" \
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: "=r" (sum) \
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: "0" (sum), "r" (w), "r" (tmp1), "r" (tmp2), "r" (tmp3), "r" (tmp4))
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#define ADD8 __asm __volatile(" \n\
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ldmia %2!, {%3, %4} \n\
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adds %0,%0,%3; adcs %0,%0,%4 \n\
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adcs %0,%0,#0\n" \
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: "=r" (sum) \
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: "0" (sum), "r" (w), "r" (tmp1), "r" (tmp2))
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#define ADD4 __asm __volatile(" \n\
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ldr %3,[%2],#4 \n\
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adds %0,%0,%3 \n\
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adcs %0,%0,#0\n" \
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: "=r" (sum) \
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: "0" (sum), "r" (w), "r" (tmp1))
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/*#define REDUCE {sum = (sum & 0xffff) + (sum >> 16);}*/
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#define REDUCE __asm __volatile(" \n\
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mov %2, #0x00ff \n\
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orr %2, %2, #0xff00 \n\
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and %2, %0, %2 \n\
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add %0, %2, %0, lsr #16\n" \
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: "=r" (sum) \
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: "0" (sum), "r" (tmp1))
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#define ADDCARRY {if (sum > 0xffff) sum -= 0xffff;}
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#define ROL {sum = sum << 8;} /* depends on recent REDUCE */
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#define ADDBYTE {ROL; sum += (*w << 8); byte_swapped ^= 1;}
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#define ADDSHORT {sum += *(u_short *)w;}
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#define ADVANCE(n) {w += n; mlen -= n;}
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#define ADVANCEML(n) {mlen -= n;}
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int
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in_cksum(m, len)
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register struct mbuf *m;
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register int len;
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{
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register u_char *w;
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register u_int sum = 0;
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register int mlen = 0;
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int byte_swapped = 0;
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/*
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* Declare two temporary registers for use by the asm code. We
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* allow the compiler to pick which specific machine registers to
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* use, instead of hard-coding this in the asm code above.
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*/
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/* XXX - initialized because of gcc's `-Wuninitialized' ! */
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register u_int tmp1 = 0, tmp2 = 0, tmp3 = 0, tmp4 = 0;
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for (; m && len; m = m->m_next) {
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if (m->m_len == 0)
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continue;
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w = mtod(m, u_char *);
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mlen = m->m_len;
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if (len < mlen)
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mlen = len;
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len -= mlen;
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/*
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* Ensure that we're aligned on a word boundary here so
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* that we can do 32 bit operations below.
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*/
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if ((3 & (long)w) != 0) {
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REDUCE;
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if ((1 & (long)w) != 0 && mlen >= 1) {
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ADDBYTE;
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ADVANCE(1);
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}
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if ((2 & (long)w) != 0 && mlen >= 2) {
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ADDSHORT;
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ADVANCE(2);
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}
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}
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/*
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* Do as many 32 bit operattions as possible using the
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* 64/32/16/8/4 macro's above, using as many as possible of
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* these.
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*/
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while (mlen >= 64) {
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ADD64;
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ADVANCEML(64);
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}
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if (mlen >= 32) {
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ADD32;
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ADVANCEML(32);
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}
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if (mlen >= 16) {
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ADD16;
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ADVANCEML(16);
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}
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if (mlen >= 8) {
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ADD8;
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ADVANCEML(8);
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}
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if (mlen >= 4) {
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ADD4;
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ADVANCEML(4)
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}
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if (mlen == 0)
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continue;
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REDUCE;
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if (mlen >= 2) {
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ADDSHORT;
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ADVANCE(2);
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}
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if (mlen == 1) {
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ADDBYTE;
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}
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}
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if (byte_swapped) {
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REDUCE;
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ROL;
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}
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REDUCE;
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ADDCARRY;
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return (0xffff ^ sum);
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}
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