Performance improvements for PCIe and 8168 based devices:
- When using the countdown timer for interrupt moderation on PCIe devices, use a timer rate value based on a 125MHz PCIe reference clock instead of 33 MHz. - For 8168 based devices, ditch the countdown timer and instead use the (undocumented) hardware interrupt moderation feature. - Support TSOv4 on 8168D and later devices.
This commit is contained in:
jmcneill
parent
415d159521
commit
cf1efaaa6a
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@ -1,4 +1,4 @@
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/* $NetBSD: rtl8169.c,v 1.149 2017/02/20 06:46:41 ozaki-r Exp $ */
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/* $NetBSD: rtl8169.c,v 1.150 2017/04/19 00:20:02 jmcneill Exp $ */
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/*
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* Copyright (c) 1997, 1998-2003
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@ -33,7 +33,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.149 2017/02/20 06:46:41 ozaki-r Exp $");
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__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.150 2017/04/19 00:20:02 jmcneill Exp $");
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/* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
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/*
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@ -837,14 +837,6 @@ re_attach(struct rtk_softc *sc)
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IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
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IFCAP_TSOv4;
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/*
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* XXX
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* Still have no idea how to make TSO work on 8168C, 8168CP,
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* 8102E, 8111C and 8111CP.
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*/
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if ((sc->sc_quirk & RTKQ_DESCV2) != 0)
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ifp->if_capabilities &= ~IFCAP_TSOv4;
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ifp->if_watchdog = re_watchdog;
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ifp->if_init = re_init;
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ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN;
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@ -1418,7 +1410,8 @@ re_txeof(struct rtk_softc *sc)
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* This is done in case the transmitter has gone idle.
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*/
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if (sc->re_ldata.re_txq_free < RE_TX_QLEN) {
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CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
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if ((sc->sc_quirk & RTKQ_IM_HW) == 0)
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CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
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if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
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/*
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* Some chips will ignore a second TX request
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@ -1466,6 +1459,9 @@ re_intr(void *arg)
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if ((ifp->if_flags & IFF_UP) == 0)
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return 0;
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const uint16_t status_mask = (sc->sc_quirk & RTKQ_IM_HW) ?
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RTK_INTRS_IM_HW : RTK_INTRS_CPLUS;
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for (;;) {
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status = CSR_READ_2(sc, RTK_ISR);
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@ -1477,14 +1473,14 @@ re_intr(void *arg)
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CSR_WRITE_2(sc, RTK_ISR, status);
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}
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if ((status & RTK_INTRS_CPLUS) == 0)
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if ((status & status_mask) == 0)
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break;
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if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR))
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re_rxeof(sc);
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if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR |
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RTK_ISR_TX_DESC_UNAVAIL))
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RTK_ISR_TX_DESC_UNAVAIL | RTK_ISR_TX_OK))
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re_txeof(sc);
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if (status & RTK_ISR_SYSTEM_ERR) {
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@ -1552,8 +1548,14 @@ re_start(struct ifnet *ifp)
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if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) {
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uint32_t segsz = m->m_pkthdr.segsz;
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re_flags = RE_TDESC_CMD_LGSEND |
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(segsz << RE_TDESC_CMD_MSSVAL_SHIFT);
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if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
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re_flags = RE_TDESC_CMD_LGSEND |
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(segsz << RE_TDESC_CMD_MSSVAL_SHIFT);
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} else {
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re_flags = RE_TDESC_CMD_LGSEND_V4;
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vlanctl |=
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(segsz << RE_TDESC_VLANCTL_MSSVAL_SHIFT);
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}
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} else {
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/*
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* set RE_TDESC_CMD_IPCSUM if any checksum offloading
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@ -1746,15 +1748,17 @@ re_start(struct ifnet *ifp)
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else
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CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
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/*
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* Use the countdown timer for interrupt moderation.
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* 'TX done' interrupts are disabled. Instead, we reset the
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* countdown timer, which will begin counting until it hits
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* the value in the TIMERINT register, and then trigger an
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* interrupt. Each time we write to the TIMERCNT register,
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* the timer count is reset to 0.
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*/
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CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
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if ((sc->sc_quirk & RTKQ_IM_HW) == 0) {
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/*
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* Use the countdown timer for interrupt moderation.
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* 'TX done' interrupts are disabled. Instead, we reset
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* the countdown timer, which will begin counting until
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* it hits the value in the TIMERINT register, and then
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* trigger an interrupt. Each time we write to the
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* TIMERCNT register, the timer count is reset to 0.
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*/
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CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
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}
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/*
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* Set a timeout in case the chip goes out to lunch.
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@ -1813,8 +1817,13 @@ re_init(struct ifnet *ifp)
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CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
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/* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */
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if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
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CSR_WRITE_2(sc, RTK_IM, 0x0000);
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if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
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if ((sc->sc_quirk & RTKQ_IM_HW) == 0) {
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CSR_WRITE_2(sc, RTK_IM, 0x0000);
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} else {
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CSR_WRITE_2(sc, RTK_IM, 0x5151);
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}
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}
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DELAY(10000);
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@ -1907,6 +1916,8 @@ re_init(struct ifnet *ifp)
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*/
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if (sc->re_testmode)
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CSR_WRITE_2(sc, RTK_IMR, 0);
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else if ((sc->sc_quirk & RTKQ_IM_HW) == 0)
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CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_IM_HW);
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else
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CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS);
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@ -1928,7 +1939,15 @@ re_init(struct ifnet *ifp)
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if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
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CSR_WRITE_4(sc, RTK_TIMERINT, 0x400);
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else {
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CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800);
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if ((sc->sc_quirk & RTKQ_IM_HW) == 0) {
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if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
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CSR_WRITE_4(sc, RTK_TIMERINT_8169, 15000);
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} else {
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CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800);
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}
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} else {
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CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0);
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}
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/*
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* For 8169 gigE NICs, set the max allowed RX packet
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@ -1,4 +1,4 @@
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/* $NetBSD: rtl81x9reg.h,v 1.47 2015/08/28 13:20:46 nonaka Exp $ */
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/* $NetBSD: rtl81x9reg.h,v 1.48 2017/04/19 00:20:02 jmcneill Exp $ */
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/*
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* Copyright (c) 1997, 1998
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@ -258,6 +258,8 @@
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RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \
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RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR|RTK_ISR_TIMEOUT_EXPIRED)
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#define RTK_INTRS_IM_HW \
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(RTK_INTRS_CPLUS|RTK_ISR_TX_OK)
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/*
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* Media status register. (8139 only)
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@ -507,12 +509,16 @@ struct re_desc {
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#define RE_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
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#define RE_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
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#define RE_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
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#define RE_TDESC_CMD_LGSEND_V4 0x04000000 /* DESCV2 TCPv4 large send en */
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#define RE_TDESC_CMD_LGSEND_V6 0x08000000 /* DESCV2 TCPv6 large send en */
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#define RE_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
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#define RE_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
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#define RE_TDESC_VLANCTL_UDPCSUM 0x80000000 /* DESCV2 UDP cksum enable */
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#define RE_TDESC_VLANCTL_TCPCSUM 0x40000000 /* DESCV2 TCP cksum enable */
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#define RE_TDESC_VLANCTL_IPCSUM 0x20000000 /* DESCV2 IP hdr cksum enable */
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#define RE_TDESC_VLANCTL_MSSVAL 0x0ffc0000 /* DESCV2 large send MSS val */
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#define RE_TDESC_VLANCTL_MSSVAL_SHIFT 18
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/*
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* Error bits are valid only on the last descriptor of a frame
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@ -1,4 +1,4 @@
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/* $NetBSD: rtl81x9var.h,v 1.55 2015/04/13 16:33:24 riastradh Exp $ */
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/* $NetBSD: rtl81x9var.h,v 1.56 2017/04/19 00:20:02 jmcneill Exp $ */
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/*
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* Copyright (c) 1997, 1998
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@ -193,6 +193,7 @@ struct rtk_softc {
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#define RTKQ_CMDSTOP 0x00000200 /* set STOPREQ on stop */
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#define RTKQ_PHYWAKE_PM 0x00000400 /* wake PHY from power down */
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#define RTKQ_RXDV_GATED 0x00000800
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#define RTKQ_IM_HW 0x00001000 /* HW interrupt mitigation */
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bus_dma_tag_t sc_dmat;
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@ -1,4 +1,4 @@
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/* $NetBSD: if_re_pci.c,v 1.45 2015/12/14 20:01:17 jakllsch Exp $ */
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/* $NetBSD: if_re_pci.c,v 1.46 2017/04/19 00:20:02 jmcneill Exp $ */
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/*
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* Copyright (c) 1997, 1998-2003
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@ -46,7 +46,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_re_pci.c,v 1.45 2015/12/14 20:01:17 jakllsch Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_re_pci.c,v 1.46 2017/04/19 00:20:02 jmcneill Exp $");
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#include <sys/types.h>
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@ -240,6 +240,9 @@ re_pci_attach(device_t parent, device_t self, void *aux)
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t->rtk_basetype == RTK_8101E)
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sc->sc_quirk |= RTKQ_PCIE;
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if (t->rtk_basetype == RTK_8168)
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sc->sc_quirk |= RTKQ_IM_HW;
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if (pci_dma64_available(pa) && (sc->sc_quirk & RTKQ_PCIE))
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sc->sc_dmat = pa->pa_dmat64;
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else
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