KNF a bit. No functional change.
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642c61d6f3
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wm.c,v 1.594 2018/11/02 08:16:49 msaitoh Exp $ */
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/* $NetBSD: if_wm.c,v 1.595 2018/11/02 08:26:32 msaitoh Exp $ */
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/*
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* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
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@ -83,7 +83,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.594 2018/11/02 08:16:49 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.595 2018/11/02 08:26:32 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_net_mpsafe.h"
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@ -1870,10 +1870,9 @@ wm_attach(device_t parent, device_t self, void *aux)
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0, &sc->sc_iot, &sc->sc_ioh,
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NULL, &sc->sc_ios) == 0) {
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sc->sc_flags |= WM_F_IOH_VALID;
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} else {
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} else
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aprint_error_dev(sc->sc_dev,
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"WARNING: unable to map I/O space\n");
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}
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}
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}
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@ -3259,9 +3258,9 @@ wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
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error = 0;
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if (cmd == SIOCSIFCAP) {
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if (cmd == SIOCSIFCAP)
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error = (*ifp->if_init)(ifp);
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} else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
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else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
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;
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else if (ifp->if_flags & IFF_RUNNING) {
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/*
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@ -3859,7 +3858,7 @@ wm_phy_post_reset(struct wm_softc *sc)
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/* Perform any necessary post-reset workarounds */
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if (sc->sc_type == WM_T_PCH)
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wm_hv_phy_workaround_ich8lan(sc);
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if (sc->sc_type == WM_T_PCH2)
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else if (sc->sc_type == WM_T_PCH2)
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wm_lv_phy_workaround_ich8lan(sc);
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/* Clear the host wakeup bit after lcd reset */
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@ -4520,9 +4519,8 @@ wm_reset(struct wm_softc *sc)
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if (sc->sc_type != WM_T_82574) {
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CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
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CSR_WRITE(sc, WMREG_EIAC, 0);
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} else {
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} else
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CSR_WRITE(sc, WMREG_EIAC_82574, 0);
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}
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}
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/* Stop the transmit and receive processes. */
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@ -5885,9 +5883,9 @@ wm_init_locked(struct ifnet *ifp)
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CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO);
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}
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if (MCLBYTES == 2048) {
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if (MCLBYTES == 2048)
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sc->sc_rctl |= RCTL_2k;
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} else {
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else {
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if (sc->sc_type >= WM_T_82543) {
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switch (MCLBYTES) {
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case 4096:
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@ -5904,7 +5902,8 @@ wm_init_locked(struct ifnet *ifp)
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MCLBYTES);
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break;
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}
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} else panic("wm_init: i82542 requires MCLBYTES = 2048");
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} else
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panic("wm_init: i82542 requires MCLBYTES = 2048");
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}
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/* Enable ECC */
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@ -6944,9 +6943,9 @@ wm_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
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if ((m0->m_pkthdr.csum_flags &
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(M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) {
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iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
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} else {
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} else
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iphl = M_CSUM_DATA_IPv6_IPHL(m0->m_pkthdr.csum_data);
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}
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ipcse = offset + iphl - 1;
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cmd = WTX_CMD_DEXT | WTX_DTYP_D;
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@ -7675,22 +7674,22 @@ wm_nq_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
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if (m0->m_pkthdr.csum_flags &
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(M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
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WM_Q_EVCNT_INCR(txq, tusum);
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if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
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if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TSOv4))
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cmdc |= NQTXC_CMD_TCP;
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} else {
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else
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cmdc |= NQTXC_CMD_UDP;
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}
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cmdc |= NQTXC_CMD_IP4;
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*fieldsp |= NQTXD_FIELDS_TUXSM;
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}
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if (m0->m_pkthdr.csum_flags &
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(M_CSUM_UDPv6 | M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
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WM_Q_EVCNT_INCR(txq, tusum6);
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if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
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if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv6 | M_CSUM_TSOv6))
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cmdc |= NQTXC_CMD_TCP;
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} else {
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else
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cmdc |= NQTXC_CMD_UDP;
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}
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cmdc |= NQTXC_CMD_IP6;
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*fieldsp |= NQTXD_FIELDS_TUXSM;
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}
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@ -7988,9 +7987,9 @@ retry:
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htole32(WTX_CMD_VLE);
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txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =
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htole16(vlan_get_tag(m0));
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} else {
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} else
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txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0;
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}
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dcmdlen = 0;
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} else {
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/* setup an advanced data descriptor */
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@ -9845,10 +9844,9 @@ wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid)
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CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
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}
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}
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} else {
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} else
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mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
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MII_OFFSET_ANY, MIIF_DOPAUSE);
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}
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/*
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* If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
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@ -12178,9 +12176,8 @@ wm_ich8_cycle_init(struct wm_softc *sc)
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hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
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/* May be check the Flash Des Valid bit in Hw status */
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if ((hsfsts & HSFSTS_FLDVAL) == 0) {
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if ((hsfsts & HSFSTS_FLDVAL) == 0)
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return error;
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}
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/* Clear FCERR in Hw status by writing 1 */
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/* Clear DAEL in Hw status by writing a 1 */
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@ -14652,9 +14649,8 @@ wm_phy_is_accessible_pchlan(struct wm_softc *sc)
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continue;
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break;
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}
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if (!MII_INVALIDID(id1) && !MII_INVALIDID(id2)) {
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if (!MII_INVALIDID(id1) && !MII_INVALIDID(id2))
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goto out;
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}
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if (sc->sc_type < WM_T_PCH_LPT) {
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sc->phy.release(sc);
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