Update a comment to reflect ARM ARMv7
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/* $NetBSD: pte.h,v 1.18 2014/08/08 07:47:24 skrll Exp $ */
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/* $NetBSD: pte.h,v 1.19 2014/10/29 10:59:48 skrll Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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@ -304,34 +304,32 @@ typedef uint32_t pt_entry_t; /* L2 table entry */
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/*
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* Type Extension bits for ARM V6 and V7 MMU
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*
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* TEX C B Shared
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* 000 0 0 Strong order yes
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* 000 0 1 Shared device yes
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* 000 1 0 write through, no write alloc S-bit
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* 000 1 1 write back, no write alloc S-bit
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* 001 0 0 non-cacheable S-bit
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* TEX C B Shared
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* 000 0 0 Strong order yes
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* 000 0 1 Shared device yes
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* 000 1 0 Outer and Inner write through, no write alloc S-bit
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* 000 1 1 Outer and Inner write back, no write alloc S-bit
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* 001 0 0 Outer and Inner non-cacheable S-bit
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* 001 0 1 reserved
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* 001 1 0 reserved
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* 001 1 1 write back, write alloc S-bit
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* 010 0 0 Non-shared device no
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* 001 1 1 Outer and Inner write back, write alloc S-bit
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* 010 0 0 Non-shared device no
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* 010 0 1 reserved
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* 010 1 X reserved
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* 011 X X reserved
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* 1BB A A BB for internal, AA for external S-bit
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* 1BB A A BB for inner, AA for outer S-bit
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*
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* BB internal cache
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* 0 0 Non-cacheable non-buffered
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* 0 1 Write back, write alloc, buffered
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* 1 0 Write through, no write alloc, buffered
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* (non-cacheable for MPCore)
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* 1 1 Write back, no write alloc, buffered
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* (write back, write alloc for MPCore)
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* BB inner cache
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* 0 0 Non-cacheable
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* 0 1 Write back, write alloc
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* 1 0 Write through, no write alloc
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* 1 1 Write back, no write alloc
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*
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* AA external cache
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* 0 0 Non-cacheable non-buffered
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* 0 1 Write back, write alloc, buffered
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* 1 0 Write through, no write alloc, buffered
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* 1 1 Write back, no write alloc, buffered
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* AA outer cache
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* 0 0 Non-cacheable
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* 0 1 Write back, write alloc
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* 1 0 Write through, no write alloc
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* 1 1 Write back, no write alloc
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*/
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#define TEX_ARMV6_TEX 0x07 /* 3 bits in TEX */
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