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Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

This commit is contained in:
skrll 2020-10-30 18:54:35 +00:00
parent bfb6e5613b
commit ce993bccb4
26 changed files with 119 additions and 156 deletions
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14
sys/arch/aarch64/include/locore.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.h,v 1.5 2018/07/09 09:09:47 jmcneill Exp $ */
/* $NetBSD: locore.h,v 1.6 2020/10/30 18:54:35 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@ -86,18 +86,6 @@ daif_disable(register_t psw)
return oldpsw;
}
static inline void
arm_dsb(void)
{
__asm __volatile("dsb sy" ::: "memory");
}
static inline void
arm_isb(void)
{
__asm __volatile("isb" ::: "memory");
}
#endif /* _LOCORE */
#elif defined(__arm__)

6
sys/arch/arm/arm/cpufunc.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc.c,v 1.177 2020/07/10 12:25:08 skrll Exp $ */
/* $NetBSD: cpufunc.c,v 1.178 2020/10/30 18:54:36 skrll Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.177 2020/07/10 12:25:08 skrll Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.178 2020/10/30 18:54:36 skrll Exp $");
#include "opt_arm_start.h"
#include "opt_compat_netbsd.h"
@ -1330,7 +1330,7 @@ get_cachesize_cp15(int cssr)
__asm volatile(".arch\tarmv7a");
armreg_csselr_write(cssr);
arm_isb(); /* sync to the new cssr */
isb(); /* sync to the new cssr */
#else
__asm volatile("mcr p15, 1, %0, c0, c0, 2" :: "r" (cssr) : "memory");

6
sys/arch/arm/arm32/arm32_kvminit.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: arm32_kvminit.c,v 1.65 2020/08/28 13:36:52 skrll Exp $ */
/* $NetBSD: arm32_kvminit.c,v 1.66 2020/10/30 18:54:36 skrll Exp $ */
/*
* Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
@ -127,7 +127,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: arm32_kvminit.c,v 1.65 2020/08/28 13:36:52 skrll Exp $");
__KERNEL_RCSID(0, "$NetBSD: arm32_kvminit.c,v 1.66 2020/10/30 18:54:36 skrll Exp $");
#include <sys/param.h>
@ -1050,7 +1050,7 @@ arm32_kernel_vm_init(vaddr_t kernel_vm_base, vaddr_t vectors, vaddr_t iovbase,
*/
armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0);
cpu_setttb(l1pt_pa, KERNEL_PID);
arm_isb();
isb();
#else
cpu_setttb(l1pt_pa, true);
#endif

6
sys/arch/arm/arm32/arm32_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: arm32_machdep.c,v 1.137 2020/08/28 13:15:05 skrll Exp $ */
/* $NetBSD: arm32_machdep.c,v 1.138 2020/10/30 18:54:36 skrll Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.137 2020/08/28 13:15:05 skrll Exp $");
__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.138 2020/10/30 18:54:36 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_arm_start.h"
@ -752,7 +752,7 @@ cpu_init_secondary_processor(int cpuindex)
armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0);
cpu_setttb(pmap_kernel()->pm_l1_pa , KERNEL_PID);
arm_isb();
isb();
#else
cpu_setttb(pmap_kernel()->pm_l1->l1_physaddr, true);
#endif

34
sys/arch/arm/arm32/arm32_tlb.c
View File

@ -31,7 +31,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.13 2020/09/29 19:58:49 jmcneill Exp $");
__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.14 2020/10/30 18:54:36 skrll Exp $");
#include <sys/param.h>
#include <sys/types.h>
@ -52,26 +52,26 @@ tlb_get_asid(void)
void
tlb_set_asid(tlb_asid_t asid)
{
arm_dsb();
dsb(sy);
if (asid == KERNEL_PID) {
armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0);
arm_isb();
isb();
}
armreg_contextidr_write(asid);
arm_isb();
isb();
}
void
tlb_invalidate_all(void)
{
const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
arm_dsb();
dsb(sy);
if (arm_has_mpext_p) {
armreg_tlbiallis_write(0);
} else {
armreg_tlbiall_write(0);
}
arm_isb();
isb();
if (__predict_false(vivt_icache_p)) {
if (arm_has_tlbiasid_p) {
armreg_icialluis_write(0);
@ -79,8 +79,8 @@ tlb_invalidate_all(void)
armreg_iciallu_write(0);
}
}
arm_dsb();
arm_isb();
dsb(sy);
isb();
}
void
@ -93,7 +93,7 @@ void
tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
{
const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
arm_dsb();
dsb(sy);
if (arm_has_tlbiasid_p) {
for (; lo <= hi; lo++) {
if (arm_has_mpext_p) {
@ -102,8 +102,8 @@ tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
armreg_tlbiasid_write(lo);
}
}
arm_dsb();
arm_isb();
dsb(sy);
isb();
if (__predict_false(vivt_icache_p)) {
if (arm_has_mpext_p) {
armreg_icialluis_write(0);
@ -113,18 +113,18 @@ tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
}
} else {
armreg_tlbiall_write(0);
arm_isb();
isb();
if (__predict_false(vivt_icache_p)) {
armreg_iciallu_write(0);
}
}
arm_isb();
isb();
}
void
tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
{
arm_dsb();
dsb(sy);
va = trunc_page(va) | asid;
for (vaddr_t eva = va + PAGE_SIZE; va < eva; va += L2_S_SIZE) {
if (arm_has_mpext_p) {
@ -133,7 +133,7 @@ tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
armreg_tlbimva_write(va);
}
}
arm_isb();
isb();
}
bool
@ -153,7 +153,7 @@ tlb_cortex_a5_record_asids(u_long *mapp, tlb_asid_t asid_max)
armreg_tlbdataop_write(
__SHIFTIN(way, ARM_TLBDATAOP_WAY)
| __SHIFTIN(va_index, ARM_A5_TLBDATAOP_INDEX));
arm_isb();
isb();
const uint64_t d = ((uint64_t) armreg_tlbdata1_read())
| armreg_tlbdata0_read();
if (!(d & ARM_TLBDATA_VALID)
@ -185,7 +185,7 @@ tlb_cortex_a7_record_asids(u_long *mapp, tlb_asid_t asid_max)
armreg_tlbdataop_write(
__SHIFTIN(way, ARM_TLBDATAOP_WAY)
| __SHIFTIN(va_index, ARM_A7_TLBDATAOP_INDEX));
arm_isb();
isb();
const uint32_t d0 = armreg_tlbdata0_read();
const uint32_t d1 = armreg_tlbdata1_read();
if (!(d0 & ARM_TLBDATA_VALID)

6
sys/arch/arm/arm32/armv7_generic_space.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: armv7_generic_space.c,v 1.12 2020/06/20 07:10:36 skrll Exp $ */
/* $NetBSD: armv7_generic_space.c,v 1.13 2020/10/30 18:54:36 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@ -31,7 +31,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: armv7_generic_space.c,v 1.12 2020/06/20 07:10:36 skrll Exp $");
__KERNEL_RCSID(0, "$NetBSD: armv7_generic_space.c,v 1.13 2020/10/30 18:54:36 skrll Exp $");
#include <sys/param.h>
@ -374,7 +374,7 @@ armv7_generic_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
flags &= BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE;
if (flags)
arm_dsb();
dsb(sy);
}
void *

12
sys/arch/arm/arm32/db_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_machdep.c,v 1.36 2020/09/29 19:58:49 jmcneill Exp $ */
/* $NetBSD: db_machdep.c,v 1.37 2020/10/30 18:54:36 skrll Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
@ -34,7 +34,7 @@
#endif
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.36 2020/09/29 19:58:49 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.37 2020/10/30 18:54:36 skrll Exp $");
#include <sys/param.h>
@ -135,9 +135,11 @@ const struct db_command db_machine_command_table[] = {
{ DDB_ADD_CMD("reset", db_reset_cmd, 0,
"Reset the system",
NULL,NULL) },
#ifdef _ARM_ARCH_7
{ DDB_ADD_CMD("tlb", db_show_tlb_cmd, 0,
"Displays the TLB",
NULL,NULL) },
#endif
#endif /* _KERNEL */
{ DDB_ADD_CMD(NULL, NULL, 0,NULL,NULL,NULL) }
@ -403,6 +405,7 @@ tlb_lookup_tlbinfo(void)
return NULL;
}
#ifdef _ARM_ARCH_7
void
db_show_tlb_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
{
@ -420,7 +423,7 @@ db_show_tlb_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *mod
armreg_tlbdataop_write(
__SHIFTIN(va_index, dti->dti_index)
| __SHIFTIN(way, ARM_TLBDATAOP_WAY));
arm_isb();
isb();
const uint32_t d0 = armreg_tlbdata0_read();
const uint32_t d1 = armreg_tlbdata1_read();
if ((d0 & ARM_TLBDATA_VALID)
@ -441,7 +444,7 @@ db_show_tlb_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *mod
armreg_tlbdataop_write(
__SHIFTIN(way, ARM_TLBDATAOP_WAY)
| __SHIFTIN(va_index, dti->dti_index));
arm_isb();
isb();
const uint32_t d0 = armreg_tlbdata0_read();
const uint32_t d1 = armreg_tlbdata1_read();
if (d0 & ARM_TLBDATA_VALID) {
@ -456,6 +459,7 @@ db_show_tlb_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *mod
}
db_printf("%zu TLB valid entries found\n", n);
}
#endif
#if defined(MULTIPROCESSOR)
void

16
sys/arch/arm/arm32/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.421 2020/08/12 18:30:46 skrll Exp $ */
/* $NetBSD: pmap.c,v 1.422 2020/10/30 18:54:36 skrll Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@ -192,7 +192,7 @@
#endif
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.421 2020/08/12 18:30:46 skrll Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.422 2020/10/30 18:54:36 skrll Exp $");
#include <sys/param.h>
#include <sys/types.h>
@ -932,7 +932,7 @@ pmap_pte_sync_current(pmap_t pm, pt_entry_t *ptep)
{
if (PMAP_NEEDS_PTE_SYNC && pmap_is_cached(pm))
PTE_SYNC(ptep);
arm_dsb();
dsb(sy);
}
# define PTE_SYNC_CURRENT(pm, ptep) pmap_pte_sync_current(pm, ptep)
@ -4749,7 +4749,7 @@ pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user)
armreg_ats1cuw_write(va);
else
armreg_ats1cur_write(va);
arm_isb();
isb();
printf("fixup: par %#x\n", armreg_par_read());
#endif
#endif
@ -4864,7 +4864,7 @@ pmap_md_pdetab_activate(pmap_t pm, struct lwp *l)
*/
const uint32_t old_ttbcr = armreg_ttbcr_read();
armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0);
arm_isb();
isb();
pmap_tlb_asid_acquire(pm, l);
@ -4873,7 +4873,7 @@ pmap_md_pdetab_activate(pmap_t pm, struct lwp *l)
* Now we can reenable tablewalks since the CONTEXTIDR and TTRB0
* have been updated.
*/
arm_isb();
isb();
if (pm != pmap_kernel()) {
armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0);
@ -4900,10 +4900,10 @@ pmap_md_pdetab_deactivate(pmap_t pm)
*/
const uint32_t old_ttbcr = armreg_ttbcr_read();
armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0);
arm_isb();
isb();
pmap_tlb_asid_deactivate(pm);
cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID);
arm_isb();
isb();
ci->ci_pmap_cur = pmap_kernel();
KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u",

6
sys/arch/arm/broadcom/bcm53xx_pax.c
View File

@ -34,7 +34,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: bcm53xx_pax.c,v 1.19 2020/07/07 03:38:45 thorpej Exp $");
__KERNEL_RCSID(1, "$NetBSD: bcm53xx_pax.c,v 1.20 2020/10/30 18:54:36 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -417,12 +417,12 @@ bcmpax_conf_addr_write(struct bcmpax_softc *sc, pcitag_t tag)
bcmpax_write_4(sc, PCIE_CFG_IND_ADDR,
__SHIFTIN(func, CFG_IND_ADDR_FUNC)
| __SHIFTIN(reg, CFG_IND_ADDR_REG));
arm_dsb();
dsb(sy);
return PCIE_CFG_IND_DATA;
}
if (sc->sc_linkup) {
bcmpax_write_4(sc, PCIE_CFG_ADDR, tag);
arm_dsb();
dsb(sy);
return PCIE_CFG_DATA;
}
return 0;

6
sys/arch/arm/broadcom/bcmgen_space.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bcmgen_space.c,v 1.6 2018/03/16 17:56:31 ryo Exp $ */
/* $NetBSD: bcmgen_space.c,v 1.7 2020/10/30 18:54:36 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@ -31,7 +31,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: bcmgen_space.c,v 1.6 2018/03/16 17:56:31 ryo Exp $");
__KERNEL_RCSID(0, "$NetBSD: bcmgen_space.c,v 1.7 2020/10/30 18:54:36 skrll Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -242,7 +242,7 @@ bcmgen_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
flags &= BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE;
if (flags)
arm_dsb();
dsb(sy);
}
void *

26
sys/arch/arm/cortex/gicv3.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: gicv3.c,v 1.25 2020/04/13 12:14:55 jmcneill Exp $ */
/* $NetBSD: gicv3.c,v 1.26 2020/10/30 18:54:36 skrll Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.25 2020/04/13 12:14:55 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.26 2020/10/30 18:54:36 skrll Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
@ -214,7 +214,7 @@ gicv3_set_priority(struct pic_softc *pic, int ipl)
struct gicv3_softc * const sc = PICTOSOFTC(pic);
icc_pmr_write(IPL_TO_PMR(sc, ipl));
arm_isb();
isb();
}
static void
@ -439,7 +439,7 @@ gicv3_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi)
if ((ci->ci_gic_sgir & ICC_SGIR_EL1_Aff) != aff) {
if (targets != 0) {
icc_sgi1r_write(intid | aff | targets);
arm_isb();
isb();
targets = 0;
}
aff = (ci->ci_gic_sgir & ICC_SGIR_EL1_Aff);
@ -448,7 +448,7 @@ gicv3_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi)
}
if (targets != 0) {
icc_sgi1r_write(intid | aff | targets);
arm_isb();
isb();
}
}
}
@ -529,7 +529,7 @@ gicv3_lpi_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask)
}
if (!sc->sc_lpiconf_flush)
__asm __volatile ("dsb ishst");
dsb(ishst);
}
static void
@ -546,7 +546,7 @@ gicv3_lpi_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask)
}
if (!sc->sc_lpiconf_flush)
__asm __volatile ("dsb ishst");
dsb(ishst);
}
static void
@ -559,7 +559,7 @@ gicv3_lpi_establish_irq(struct pic_softc *pic, struct intrsource *is)
if (sc->sc_lpiconf_flush)
cpu_dcache_wb_range((vaddr_t)&sc->sc_lpiconf.base[is->is_irq], 1);
else
__asm __volatile ("dsb ishst");
dsb(ishst);
}
static void
@ -582,7 +582,7 @@ gicv3_lpi_cpu_init(struct pic_softc *pic, struct cpu_info *ci)
ctlr = gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR);
ctlr &= ~GICR_CTLR_Enable_LPIs;
gicr_write_4(sc, ci->ci_gic_redist, GICR_CTLR, ctlr);
arm_dsb();
dsb(sy);
/* Setup the LPI configuration table */
propbase = sc->sc_lpiconf.segs[0].ds_addr |
@ -620,7 +620,7 @@ gicv3_lpi_cpu_init(struct pic_softc *pic, struct cpu_info *ci)
ctlr = gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR);
ctlr |= GICR_CTLR_Enable_LPIs;
gicr_write_4(sc, ci->ci_gic_redist, GICR_CTLR, ctlr);
arm_dsb();
dsb(sy);
/* Setup ITS if present */
LIST_FOREACH(cb, &sc->sc_lpi_callbacks, list)
@ -721,7 +721,7 @@ gicv3_irq_handler(void *frame)
for (;;) {
const uint32_t iar = icc_iar1_read();
arm_dsb();
dsb(sy);
const uint32_t irq = __SHIFTOUT(iar, ICC_IAR_INTID);
if (irq == ICC_IAR_INTID_SPURIOUS)
break;
@ -745,7 +745,7 @@ gicv3_irq_handler(void *frame)
if (early_eoi) {
icc_eoi1r_write(iar);
arm_isb();
isb();
}
cpsie(I32_bit);
@ -754,7 +754,7 @@ gicv3_irq_handler(void *frame)
if (!early_eoi) {
icc_eoi1r_write(iar);
arm_isb();
isb();
}
}

16
sys/arch/arm/cortex/gtmr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: gtmr.c,v 1.41 2019/08/12 23:31:48 jmcneill Exp $ */
/* $NetBSD: gtmr.c,v 1.42 2020/10/30 18:54:36 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.41 2019/08/12 23:31:48 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.42 2020/10/30 18:54:36 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -172,7 +172,7 @@ gtmr_attach(device_t parent, device_t self, void *aux)
static uint64_t
gtmr_read_cntct(struct gtmr_softc *sc)
{
arm_isb();
isb();
if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) {
/*
@ -209,7 +209,7 @@ gtmr_write_ctl(struct gtmr_softc *sc, uint32_t val)
else
gtmr_cntv_ctl_write(val);
arm_isb();
isb();
}
static void
@ -220,7 +220,7 @@ gtmr_write_tval(struct gtmr_softc *sc, uint32_t val)
else
gtmr_cntv_tval_write(val);
arm_isb();
isb();
}
static void
@ -231,7 +231,7 @@ gtmr_write_cval(struct gtmr_softc *sc, uint64_t val)
else
gtmr_cntv_cval_write(val);
arm_isb();
isb();
}
@ -259,7 +259,7 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
val &= ~CNTKCTL_PL0PCTEN;
}
gtmr_cntk_ctl_write(val);
arm_isb();
isb();
/*
* enable timer and stop masking the timer.
@ -364,7 +364,7 @@ gtmr_intr(void *arg)
delta = 0;
}
arm_isb();
isb();
if (ISSET(sc->sc_flags, GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER)) {
gtmr_write_cval(sc, now + sc->sc_autoinc - delta);
} else {

4
sys/arch/arm/include/arm32/pmap.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.168 2020/07/03 06:49:26 skrll Exp $ */
/* $NetBSD: pmap.h,v 1.169 2020/10/30 18:54:36 skrll Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@ -538,7 +538,7 @@ pmap_ptesync(pt_entry_t *ptep, size_t cnt)
cnt * sizeof(pt_entry_t));
#endif
}
arm_dsb();
dsb(sy);
}
#define PDE_SYNC(pdep) pmap_ptesync((pdep), 1)

31
sys/arch/arm/include/locore.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.h,v 1.33 2020/08/14 16:18:36 skrll Exp $ */
/* $NetBSD: locore.h,v 1.34 2020/10/30 18:54:36 skrll Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@ -238,35 +238,6 @@ read_thumb_insn(vaddr_t va, bool user_p)
return insn;
}
#ifndef _RUMPKERNEL
static inline void
arm_dmb(void)
{
if (CPU_IS_ARMV6_P())
armreg_dmb_write(0);
else if (CPU_IS_ARMV7_P())
__asm __volatile("dmb" ::: "memory");
}
static inline void
arm_dsb(void)
{
if (CPU_IS_ARMV6_P())
armreg_dsb_write(0);
else if (CPU_IS_ARMV7_P())
__asm __volatile("dsb" ::: "memory");
}
static inline void
arm_isb(void)
{
if (CPU_IS_ARMV6_P())
armreg_isb_write(0);
else if (CPU_IS_ARMV7_P())
__asm __volatile("isb" ::: "memory");
}
#endif
/*
* Random cruft
*/

16
sys/arch/arm/marvell/armadaxp.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: armadaxp.c,v 1.22 2020/05/14 08:34:20 msaitoh Exp $ */
/* $NetBSD: armadaxp.c,v 1.23 2020/10/30 18:54:36 skrll Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.22 2020/05/14 08:34:20 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.23 2020/10/30 18:54:36 skrll Exp $");
#define _INTR_PRIVATE
@ -950,7 +950,7 @@ armadaxp_sdcache_wb_all(void)
{
L2_WRITE(ARMADAXP_L2_WB_WAY, L2_ALL_WAYS);
L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__("dsb");
dsb(sy);
}
void
@ -958,7 +958,7 @@ armadaxp_sdcache_wbinv_all(void)
{
L2_WRITE(ARMADAXP_L2_WBINV_WAY, L2_ALL_WAYS);
L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__("dsb");
dsb(sy);
}
static paddr_t
@ -984,7 +984,7 @@ armadaxp_sdcache_wbalign_base(vaddr_t va, paddr_t pa, psize_t sz)
memcpy((void *)save_start, save_buf, unalign);
L2_WRITE(ARMADAXP_L2_WB_PHYS, line_start);
L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__("dsb");
dsb(sy);
return line_start;
}
@ -1012,7 +1012,7 @@ armadaxp_sdcache_wbalign_end(vaddr_t va, paddr_t pa, psize_t sz)
/* write back saved data */
memcpy((void *)save_start, save_buf, save_len);
L2_WRITE(ARMADAXP_L2_WB_PHYS, line_start);
__asm__ __volatile__("dsb");
dsb(sy);
return line_start;
}
@ -1050,7 +1050,7 @@ armadaxp_sdcache_wb_range(vaddr_t va, paddr_t pa, psize_t sz)
L2_WRITE(ARMADAXP_L2_WB_RANGE, pa_end);
}
L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__("dsb");
dsb(sy);
}
void
@ -1066,7 +1066,7 @@ armadaxp_sdcache_wbinv_range(vaddr_t va, paddr_t pa, psize_t sz)
L2_WRITE(ARMADAXP_L2_WBINV_RANGE, pa_end);
}
L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__("dsb");
dsb(sy);
}
#ifdef AURORA_IO_CACHE_COHERENCY

6
sys/arch/arm/samsung/exynos_platform.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: exynos_platform.c,v 1.30 2020/09/28 11:54:23 jmcneill Exp $ */
/* $NetBSD: exynos_platform.c,v 1.31 2020/10/30 18:54:36 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca>
@ -35,7 +35,7 @@
#include "ukbd.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.30 2020/09/28 11:54:23 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.31 2020/10/30 18:54:36 skrll Exp $");
/*
@ -129,7 +129,7 @@ exynos5800_mpstart(void)
bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1), val | option);
bus_space_write_4(bst, sysram_bsh, EXYNOS5800_SYSRAM_HOTPLUG, KERN_VTOPHYS((vaddr_t)cpu_mpstart));
arm_dsb();
dsb(sy);
/* Power on clusters */
bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(0),

6
sys/arch/arm/vexpress/vexpress_platform.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: vexpress_platform.c,v 1.18 2020/09/28 11:54:23 jmcneill Exp $ */
/* $NetBSD: vexpress_platform.c,v 1.19 2020/10/30 18:54:36 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
@ -30,7 +30,7 @@
#include "opt_console.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: vexpress_platform.c,v 1.18 2020/09/28 11:54:23 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: vexpress_platform.c,v 1.19 2020/10/30 18:54:36 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -104,7 +104,7 @@ vexpress_platform_early_putchar(char c)
continue;
uartaddr[PL01XCOM_DR / 4] = htole32(c);
arm_dsb();
dsb(sy);
while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
continue;

6
sys/arch/arm/vfp/vfp_init.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: vfp_init.c,v 1.71 2020/08/01 02:13:04 riastradh Exp $ */
/* $NetBSD: vfp_init.c,v 1.72 2020/10/30 18:54:37 skrll Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@ -32,7 +32,7 @@
#include "opt_cputypes.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: vfp_init.c,v 1.71 2020/08/01 02:13:04 riastradh Exp $");
__KERNEL_RCSID(0, "$NetBSD: vfp_init.c,v 1.72 2020/10/30 18:54:37 skrll Exp $");
#include <sys/param.h>
#include <sys/types.h>
@ -287,7 +287,7 @@ vfp_attach(struct cpu_info *ci)
cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp2);
armreg_cpacr_write(cpacr);
arm_isb();
isb();
/*
* If we could enable them, then they exist.

6
sys/arch/arm/virt/virt_platform.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: virt_platform.c,v 1.11 2020/09/28 11:54:23 jmcneill Exp $ */
/* $NetBSD: virt_platform.c,v 1.12 2020/10/30 18:54:37 skrll Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
@ -30,7 +30,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: virt_platform.c,v 1.11 2020/09/28 11:54:23 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: virt_platform.c,v 1.12 2020/10/30 18:54:37 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -75,7 +75,7 @@ virt_platform_early_putchar(char c)
continue;
uartaddr[PL01XCOM_DR / 4] = htole32(c);
arm_dsb();
dsb(sy);
while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
continue;

6
sys/arch/arm/zynq/zynq_space.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: zynq_space.c,v 1.3 2018/03/16 17:56:32 ryo Exp $ */
/* $NetBSD: zynq_space.c,v 1.4 2020/10/30 18:54:37 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: zynq_space.c,v 1.3 2018/03/16 17:56:32 ryo Exp $");
__KERNEL_RCSID(0, "$NetBSD: zynq_space.c,v 1.4 2020/10/30 18:54:37 skrll Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -230,7 +230,7 @@ zynq_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
flags &= BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE;
if (flags)
arm_dsb();
dsb(sy);
}
void *

6
sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bcm53xx_machdep.c,v 1.23 2020/02/15 08:16:12 skrll Exp $ */
/* $NetBSD: bcm53xx_machdep.c,v 1.24 2020/10/30 18:54:37 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@ -33,7 +33,7 @@
#define IDM_PRIVATE
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: bcm53xx_machdep.c,v 1.23 2020/02/15 08:16:12 skrll Exp $");
__KERNEL_RCSID(0, "$NetBSD: bcm53xx_machdep.c,v 1.24 2020/10/30 18:54:37 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_console.h"
@ -242,7 +242,7 @@ bcm53xx_mpstart(void)
*/
bus_space_write_4(bcm53xx_rom_bst, bcm53xx_rom_entry_bsh, mpstart);
arm_dsb();
dsb(sy);
__asm __volatile("sev" ::: "memory");
for (int loop = 0; loop < 16; loop++) {

6
sys/arch/evbarm/beagle/beagle_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: beagle_machdep.c,v 1.84 2020/09/29 19:58:50 jmcneill Exp $ */
/* $NetBSD: beagle_machdep.c,v 1.85 2020/10/30 18:54:37 skrll Exp $ */
/*
* Machine dependent functions for kernel setup for TI OSK5912 board.
@ -125,7 +125,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.84 2020/09/29 19:58:50 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.85 2020/10/30 18:54:37 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_console.h"
@ -487,7 +487,7 @@ beagle_mpstart(void)
}
arm_dsb();
dsb(sy);
__asm __volatile("sev" ::: "memory");
u_int hatched = 0;

4
sys/arch/evbarm/gumstix/gumstix_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: gumstix_machdep.c,v 1.68 2020/10/01 08:27:20 skrll Exp $ */
/* $NetBSD: gumstix_machdep.c,v 1.69 2020/10/30 18:54:37 skrll Exp $ */
/*
* Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation.
* All rights reserved.
@ -537,7 +537,7 @@ gumstix_mpstart(void)
bus_space_write_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT0, boot);
}
arm_dsb();
dsb(sy);
__asm __volatile("sev" ::: "memory");
for (int loop = 0; loop < 16; loop++) {

6
sys/arch/evbarm/zynq/zynq_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: zynq_machdep.c,v 1.13 2020/07/10 12:25:11 skrll Exp $ */
/* $NetBSD: zynq_machdep.c,v 1.14 2020/10/30 18:54:37 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: zynq_machdep.c,v 1.13 2020/07/10 12:25:11 skrll Exp $");
__KERNEL_RCSID(0, "$NetBSD: zynq_machdep.c,v 1.14 2020/10/30 18:54:37 skrll Exp $");
#include "opt_evbarm_boardtype.h"
#include "opt_arm_debug.h"
@ -220,7 +220,7 @@ zynq_mpstart(void)
bus_space_unmap(bst, bsh, ZYNQ7000_CPU1_ENTRY_SZ);
arm_dsb();
dsb(sy);
__asm __volatile("sev" ::: "memory");

8
sys/dev/tprof/tprof_armv7.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tprof_armv7.c,v 1.3 2020/02/24 12:38:57 rin Exp $ */
/* $NetBSD: tprof_armv7.c,v 1.4 2020/10/30 18:54:37 skrll Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tprof_armv7.c,v 1.3 2020/02/24 12:38:57 rin Exp $");
__KERNEL_RCSID(0, "$NetBSD: tprof_armv7.c,v 1.4 2020/10/30 18:54:37 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -77,7 +77,7 @@ static void
armv7_pmu_set_pmevtyper(u_int counter, uint64_t val)
{
armreg_pmselr_write(counter);
arm_isb();
isb();
armreg_pmxevtyper_write(val);
}
@ -85,7 +85,7 @@ static void
armv7_pmu_set_pmevcntr(u_int counter, uint32_t val)
{
armreg_pmselr_write(counter);
arm_isb();
isb();
armreg_pmxevcntr_write(val);
}

10
sys/dev/tprof/tprof_armv8.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tprof_armv8.c,v 1.5 2020/03/30 11:38:29 jmcneill Exp $ */
/* $NetBSD: tprof_armv8.c,v 1.6 2020/10/30 18:54:37 skrll Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tprof_armv8.c,v 1.5 2020/03/30 11:38:29 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: tprof_armv8.c,v 1.6 2020/10/30 18:54:37 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -37,7 +37,7 @@ __KERNEL_RCSID(0, "$NetBSD: tprof_armv8.c,v 1.5 2020/03/30 11:38:29 jmcneill Exp
#include <dev/tprof/tprof.h>
#include <arm/armreg.h>
#include <arm/locore.h>
#include <arm/cpufunc.h>
#include <dev/tprof/tprof_armv8.h>
@ -70,7 +70,7 @@ static void
armv8_pmu_set_pmevtyper(u_int counter, uint64_t val)
{
reg_pmselr_el0_write(counter);
arm_isb();
isb();
reg_pmxevtyper_el0_write(val);
}
@ -78,7 +78,7 @@ static void
armv8_pmu_set_pmevcntr(u_int counter, uint32_t val)
{
reg_pmselr_el0_write(counter);
arm_isb();
isb();
reg_pmxevcntr_el0_write(val);
}