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initial import of GCC 4.8 snapshot 2014-10-09. this fixes at

Browse Source 
least the below GCC PRs, among many other changes.

it also makes sh3 reasonably useful again.

	c++/60731
	c/61271
	c/61271
	c/61271
	debug/55794
	debug/60655
	debug/61923
	debug/63284
	debug/63342
	inline-asm/63282
	ipa/61986
	ipa/62015
	libobjc/61920
	libobjc/61920
	libstdc++/58962
	libstdc++/60734
	libstdc++/60966
	libstdc++/61946
	libstdc++/63449
	middle-end/61010
	middle-end/61045
	middle-end/62103
	rtl-optimization/57003
	rtl-optimization/60866
	rtl-optimization/60901
	rtl-optimization/61801
	rtl-optimization/62004
	rtl-optimization/62030
	target/49423
	target/52941
	target/61044
	target/61202
	target/61208
	target/61231
	target/61239
	target/61249
	target/61300
	target/61423
	target/61431
	target/61443
	target/61483
	target/61542
	target/61545
	target/61570
	target/61586
	target/61996
	target/62195
	target/62218
	target/63428
	tree-optimization/60196
	tree-optimization/61375
	tree-optimization/61383
	tree-optimization/61452
	tree-optimization/61684
	tree-optimization/61964
	tree-optimization/62073
	tree-optimization/62075
	tree-optimization/63189
	tree-optimization/63341
	tree-optimization/63375
This commit is contained in:
mrg 2014-10-12 06:58:16 +00:00
parent 407f45cc7c
commit cd5ea10d63
97 changed files with 1453 additions and 703 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
external/gpl3/gcc/dist/ChangeLog vendored
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@ -1,3 +1,9 @@
2014-07-26 Uros Bizjak <ubizjak@gmail.com>
PR target/47230
* configure.ac (alpha*-*-linux*): Use mh-alpha-linux.
* configure: Regenerate.
2014-05-22 Release Manager
* GCC 4.8.3 released.

5
external/gpl3/gcc/dist/config/ChangeLog vendored
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@ -1,3 +1,8 @@
2014-07-26 Uros Bizjak <ubizjak@gmail.com>
PR target/47230
* mh-alpha-linux: New file.
2014-05-22 Release Manager
* GCC 4.8.3 released.

3
external/gpl3/gcc/dist/config/mh-alpha-linux vendored Normal file
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@ -0,0 +1,3 @@
# Prevent GPREL16 relocation truncation
LDFLAGS += -Wl,--no-relax
BOOT_LDFLAGS += -Wl,--no-relax

4
external/gpl3/gcc/dist/contrib/ChangeLog vendored
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@ -1,3 +1,7 @@
2014-07-07 Richard Biener <rguenther@suse.de>
* gennews: Use gcc-3.0/index.html.
2014-05-22 Release Manager
* GCC 4.8.3 released.

2
external/gpl3/gcc/dist/contrib/gennews vendored
View File

@ -37,7 +37,7 @@ files="
gcc-3.3/index.html gcc-3.3/changes.html
gcc-3.2/index.html gcc-3.2/changes.html
gcc-3.1/index.html gcc-3.1/changes.html
gcc-3.0/gcc-3.0.html gcc-3.0/features.html gcc-3.0/caveats.html
gcc-3.0/index.html gcc-3.0/features.html gcc-3.0/caveats.html
gcc-2.95/index.html gcc-2.95/features.html gcc-2.95/caveats.html
egcs-1.1/index.html egcs-1.1/features.html egcs-1.1/caveats.html
egcs-1.0/index.html egcs-1.0/features.html egcs-1.0/caveats.html"

2
external/gpl3/gcc/dist/gcc/BASE-VER vendored
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@ -1 +1 @@
4.8.3
4.8.4

2
external/gpl3/gcc/dist/gcc/DATESTAMP vendored
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@ -1 +1 @@
20140522
20141009

1
external/gpl3/gcc/dist/gcc/DEV-PHASE vendored
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@ -0,0 +1 @@
prerelease

2
external/gpl3/gcc/dist/gcc/cgraphunit.c vendored
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@ -1097,7 +1097,7 @@ handle_alias_pairs (void)
/* We use local aliases for C++ thunks to force the tailcall
to bind locally. This is a hack - to keep it working do
the following (which is not strictly correct). */
&& (! TREE_CODE (target_node->symbol.decl) == FUNCTION_DECL
&& (TREE_CODE (target_node->symbol.decl) != FUNCTION_DECL
|| ! DECL_VIRTUAL_P (target_node->symbol.decl))
&& ! lookup_attribute ("weakref", DECL_ATTRIBUTES (p->decl)))
{

4
external/gpl3/gcc/dist/gcc/common.opt vendored
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@ -1226,6 +1226,10 @@ fgnu-tm
Common Report Var(flag_tm)
Enable support for GNU transactional memory
fgnu-unique
Common Report Var(flag_gnu_unique) Init(1)
Use STB_GNU_UNIQUE if supported by the assembler
floop-flatten
Common Ignore
Does nothing. Preserved for backward compatibility.

2
external/gpl3/gcc/dist/gcc/config/aarch64/aarch64-linux.h vendored
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@ -43,4 +43,6 @@
} \
while (0)
#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
#endif /* GCC_AARCH64_LINUX_H */

17
external/gpl3/gcc/dist/gcc/config/aarch64/aarch64.c vendored
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@ -1201,6 +1201,7 @@ aarch64_layout_arg (cumulative_args_t pcum_v, enum machine_mode mode,
CUMULATIVE_ARGS *pcum = get_cumulative_args (pcum_v);
int ncrn, nvrn, nregs;
bool allocate_ncrn, allocate_nvrn;
HOST_WIDE_INT size;
/* We need to do this once per argument. */
if (pcum->aapcs_arg_processed)
@ -1208,6 +1209,11 @@ aarch64_layout_arg (cumulative_args_t pcum_v, enum machine_mode mode,
pcum->aapcs_arg_processed = true;
/* Size in bytes, rounded to the nearest multiple of 8 bytes. */
size
= AARCH64_ROUND_UP (type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode),
UNITS_PER_WORD);
allocate_ncrn = (type) ? !(FLOAT_TYPE_P (type)) : !FLOAT_MODE_P (mode);
allocate_nvrn = aarch64_vfp_is_call_candidate (pcum_v,
mode,
@ -1258,9 +1264,7 @@ aarch64_layout_arg (cumulative_args_t pcum_v, enum machine_mode mode,
}
ncrn = pcum->aapcs_ncrn;
nregs = ((type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode))
+ UNITS_PER_WORD - 1) / UNITS_PER_WORD;
nregs = size / UNITS_PER_WORD;
/* C6 - C9. though the sign and zero extension semantics are
handled elsewhere. This is the case where the argument fits
@ -1309,13 +1313,12 @@ aarch64_layout_arg (cumulative_args_t pcum_v, enum machine_mode mode,
pcum->aapcs_nextncrn = NUM_ARG_REGS;
/* The argument is passed on stack; record the needed number of words for
this argument (we can re-use NREGS) and align the total size if
necessary. */
this argument and align the total size if necessary. */
on_stack:
pcum->aapcs_stack_words = nregs;
pcum->aapcs_stack_words = size / UNITS_PER_WORD;
if (aarch64_function_arg_alignment (mode, type) == 16 * BITS_PER_UNIT)
pcum->aapcs_stack_size = AARCH64_ROUND_UP (pcum->aapcs_stack_size,
16 / UNITS_PER_WORD) + 1;
16 / UNITS_PER_WORD);
return;
}

1
external/gpl3/gcc/dist/gcc/config/aarch64/aarch64.md vendored
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@ -3292,6 +3292,7 @@
(unspec:DI [(match_operand:DI 0 "aarch64_valid_symref" "S")]
UNSPEC_TLSDESC))
(clobber (reg:DI LR_REGNUM))
(clobber (reg:CC CC_REGNUM))
(clobber (match_scratch:DI 1 "=r"))]
"TARGET_TLS_DESC"
"adrp\\tx0, %A0\;ldr\\t%1, [x0, #%L0]\;add\\tx0, x0, %L0\;.tlsdesccall\\t%0\;blr\\t%1"

4
external/gpl3/gcc/dist/gcc/config/aarch64/arm_neon.h vendored
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@ -13815,7 +13815,7 @@ vqdmulh_n_s16 (int16x4_t a, int16_t b)
int16x4_t result;
__asm__ ("sqdmulh %0.4h,%1.4h,%2.h[0]"
: "=w"(result)
: "w"(a), "w"(b)
: "w"(a), "x"(b)
: /* No clobbers */);
return result;
}
@ -13837,7 +13837,7 @@ vqdmulhq_n_s16 (int16x8_t a, int16_t b)
int16x8_t result;
__asm__ ("sqdmulh %0.8h,%1.8h,%2.h[0]"
: "=w"(result)
: "w"(a), "w"(b)
: "w"(a), "x"(b)
: /* No clobbers */);
return result;
}

6
external/gpl3/gcc/dist/gcc/config/alpha/alpha.c vendored
View File

@ -8658,6 +8658,11 @@ alpha_handle_trap_shadows (void)
}
break;
case BARRIER:
/* __builtin_unreachable can expand to no code at all,
leaving (barrier) RTXes in the instruction stream. */
goto close_shadow_notrapb;
case JUMP_INSN:
case CALL_INSN:
case CODE_LABEL:
@ -8673,6 +8678,7 @@ alpha_handle_trap_shadows (void)
n = emit_insn_before (gen_trapb (), i);
PUT_MODE (n, TImode);
PUT_MODE (i, TImode);
close_shadow_notrapb:
trap_pending = 0;
shadow.used.i = 0;
shadow.used.fp = 0;

3
external/gpl3/gcc/dist/gcc/config/arm/arm-protos.h vendored
View File

@ -55,6 +55,7 @@ extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
extern int legitimate_pic_operand_p (rtx);
extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
extern rtx legitimize_tls_address (rtx, rtx);
extern bool arm_legitimate_address_p (enum machine_mode, rtx, bool);
extern int arm_legitimate_address_outer_p (enum machine_mode, rtx, RTX_CODE, int);
extern int thumb_legitimate_offset_p (enum machine_mode, HOST_WIDE_INT);
extern bool arm_legitimize_reload_address (rtx *, enum machine_mode, int, int,
@ -286,4 +287,6 @@ extern bool arm_autoinc_modes_ok_p (enum machine_mode, enum arm_auto_incmodes);
extern void arm_emit_eabi_attribute (const char *, int, int);
extern bool arm_is_constant_pool_ref (rtx);
#endif /* ! GCC_ARM_PROTOS_H */

18
external/gpl3/gcc/dist/gcc/config/arm/arm.c vendored
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@ -82,7 +82,6 @@ static rtx arm_legitimize_address (rtx, rtx, enum machine_mode);
static reg_class_t arm_preferred_reload_class (rtx, reg_class_t);
static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode);
inline static int thumb1_index_register_rtx_p (rtx, int);
static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);
static int thumb_far_jump_used_p (void);
static bool thumb_force_lr_save (void);
static unsigned arm_size_return_regs (void);
@ -24476,9 +24475,13 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
fputs (":\n", file);
if (flag_pic)
{
/* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
/* Output ".word .LTHUNKn-[3,7]-.LTHUNKPCn". */
rtx tem = XEXP (DECL_RTL (function), 0);
tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
/* For TARGET_THUMB1_ONLY the thunk is in Thumb mode, so the PC
pipeline offset is four rather than eight. Adjust the offset
accordingly. */
tem = plus_constant (GET_MODE (tem), tem,
TARGET_THUMB1_ONLY ? -3 : -7);
tem = gen_rtx_MINUS (GET_MODE (tem),
tem,
gen_rtx_SYMBOL_REF (Pmode,
@ -27462,4 +27465,13 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
}
/* return TRUE if x is a reference to a value in a constant pool */
extern bool
arm_is_constant_pool_ref (rtx x)
{
return (MEM_P (x)
&& GET_CODE (XEXP (x, 0)) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)));
}
#include "gt-arm.h"

11
external/gpl3/gcc/dist/gcc/config/arm/constraints.md vendored
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@ -36,7 +36,7 @@
;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
;; The following memory constraints have been used:
;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
;; in ARM/Thumb-2 state: Q, Uh, Ut, Uv, Uy, Un, Um, Us
;; in ARM state: Uq
;; in Thumb state: Uu, Uw
@ -310,6 +310,12 @@
An address valid for loading/storing register exclusive"
(match_operand 0 "mem_noofs_operand"))
(define_memory_constraint "Uh"
"@internal
An address suitable for byte and half-word loads which does not point inside a constant pool"
(and (match_code "mem")
(match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
(define_memory_constraint "Ut"
"@internal
In ARM/Thumb-2 state an address valid for loading/storing opaque structure
@ -356,7 +362,8 @@
(and (match_code "mem")
(match_test "TARGET_ARM
&& arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
SIGN_EXTEND, 0)")))
SIGN_EXTEND, 0)
&& !arm_is_constant_pool_ref (op)")))
(define_memory_constraint "Q"
"@internal

124
external/gpl3/gcc/dist/gcc/config/arm/t-rtems-eabi vendored
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@ -1,47 +1,167 @@
# Custom RTEMS EABI multilibs
MULTILIB_OPTIONS = mthumb march=armv6-m/march=armv7-a/march=armv7-r/march=armv7-m mfpu=neon mfloat-abi=hard
MULTILIB_DIRNAMES = thumb armv6-m armv7-a armv7-r armv7-m neon hard
MULTILIB_OPTIONS = mbig-endian mthumb march=armv6-m/march=armv7-a/march=armv7-r/march=armv7-m mfpu=neon/mfpu=vfpv3-d16/mfpu=fpv4-sp-d16 mfloat-abi=hard
MULTILIB_DIRNAMES = eb thumb armv6-m armv7-a armv7-r armv7-m neon vfpv3-d16 fpv4-sp-d16 hard
# Enumeration of multilibs
MULTILIB_EXCEPTIONS =
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=neon
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv6-m
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=neon
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-a
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=neon
# MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r/mfloat-abi=hard
# MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-r
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=neon
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/march=armv7-m
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=neon
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mbig-endian/mthumb/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mthumb
MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=neon
MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv6-m
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=neon
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-a
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=neon
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-r
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=neon
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/march=armv7-m
MULTILIB_EXCEPTIONS += mbig-endian/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mfpu=neon
MULTILIB_EXCEPTIONS += mbig-endian/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mbig-endian/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mbig-endian/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mbig-endian
MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=neon
MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mthumb/march=armv6-m/mfloat-abi=hard
# MULTILIB_EXCEPTIONS += mthumb/march=armv6-m
# MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=neon
MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mthumb/march=armv7-a/mfloat-abi=hard
# MULTILIB_EXCEPTIONS += mthumb/march=armv7-a
MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=neon
# MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mthumb/march=armv7-r/mfloat-abi=hard
# MULTILIB_EXCEPTIONS += mthumb/march=armv7-r
MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=neon
MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=vfpv3-d16
# MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mthumb/march=armv7-m/mfloat-abi=hard
# MULTILIB_EXCEPTIONS += mthumb/march=armv7-m
MULTILIB_EXCEPTIONS += mthumb/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/mfpu=neon
MULTILIB_EXCEPTIONS += mthumb/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mthumb/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mthumb/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mthumb/mfloat-abi=hard
# MULTILIB_EXCEPTIONS += mthumb
MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=neon
MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv6-m/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += march=armv6-m/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv6-m
MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=neon
MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-a/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += march=armv7-a/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-a
MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=neon
MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-r/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += march=armv7-r/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-r
MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=neon
MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-m/mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += march=armv7-m/mfloat-abi=hard
MULTILIB_EXCEPTIONS += march=armv7-m
MULTILIB_EXCEPTIONS += mfpu=neon/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mfpu=neon
MULTILIB_EXCEPTIONS += mfpu=vfpv3-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mfpu=vfpv3-d16
MULTILIB_EXCEPTIONS += mfpu=fpv4-sp-d16/mfloat-abi=hard
MULTILIB_EXCEPTIONS += mfpu=fpv4-sp-d16
MULTILIB_EXCEPTIONS += mfloat-abi=hard

4
external/gpl3/gcc/dist/gcc/config/avr/avr-fixed.md vendored
View File

@ -430,8 +430,8 @@
}
// Input and output of the libgcc function
const unsigned int regno_in[] = { -1, 22, 22, -1, 18 };
const unsigned int regno_out[] = { -1, 24, 24, -1, 22 };
const unsigned int regno_in[] = { -1U, 22, 22, -1U, 18 };
const unsigned int regno_out[] = { -1U, 24, 24, -1U, 22 };
operands[3] = gen_rtx_REG (<MODE>mode, regno_out[(size_t) GET_MODE_SIZE (<MODE>mode)]);
operands[4] = gen_rtx_REG (<MODE>mode, regno_in[(size_t) GET_MODE_SIZE (<MODE>mode)]);

14
external/gpl3/gcc/dist/gcc/config/avr/avr.h vendored
View File

@ -250,18 +250,18 @@ enum reg_class {
#define REG_CLASS_CONTENTS { \
{0x00000000,0x00000000}, /* NO_REGS */ \
{0x00000001,0x00000000}, /* R0_REG */ \
{3 << REG_X,0x00000000}, /* POINTER_X_REGS, r26 - r27 */ \
{3 << REG_Y,0x00000000}, /* POINTER_Y_REGS, r28 - r29 */ \
{3 << REG_Z,0x00000000}, /* POINTER_Z_REGS, r30 - r31 */ \
{3u << REG_X,0x00000000}, /* POINTER_X_REGS, r26 - r27 */ \
{3u << REG_Y,0x00000000}, /* POINTER_Y_REGS, r28 - r29 */ \
{3u << REG_Z,0x00000000}, /* POINTER_Z_REGS, r30 - r31 */ \
{0x00000000,0x00000003}, /* STACK_REG, STACK */ \
{(3 << REG_Y) | (3 << REG_Z), \
{(3u << REG_Y) | (3u << REG_Z), \
0x00000000}, /* BASE_POINTER_REGS, r28 - r31 */ \
{(3 << REG_X) | (3 << REG_Y) | (3 << REG_Z), \
{(3u << REG_X) | (3u << REG_Y) | (3u << REG_Z), \
0x00000000}, /* POINTER_REGS, r26 - r31 */ \
{(3 << REG_X) | (3 << REG_Y) | (3 << REG_Z) | (3 << REG_W), \
{(3u << REG_X) | (3u << REG_Y) | (3u << REG_Z) | (3u << REG_W), \
0x00000000}, /* ADDW_REGS, r24 - r31 */ \
{0x00ff0000,0x00000000}, /* SIMPLE_LD_REGS r16 - r23 */ \
{(3 << REG_X)|(3 << REG_Y)|(3 << REG_Z)|(3 << REG_W)|(0xff << 16), \
{(3u << REG_X)|(3u << REG_Y)|(3u << REG_Z)|(3u << REG_W)|(0xffu << 16),\
0x00000000}, /* LD_REGS, r16 - r31 */ \
{0x0000ffff,0x00000000}, /* NO_LD_REGS r0 - r15 */ \
{0xffffffff,0x00000000}, /* GENERAL_REGS, r0 - r31 */ \

9
external/gpl3/gcc/dist/gcc/config/avr/avr.md vendored
View File

@ -367,6 +367,15 @@
""
{
int i;
// Avoid (subreg (mem)) for non-generic address spaces below. Because
// of the poor addressing capabilities of these spaces it's better to
// load them in one chunk. And it avoids PR61443.
if (MEM_P (operands[0])
&& !ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (operands[0])))
operands[0] = copy_to_mode_reg (<MODE>mode, operands[0]);
for (i = GET_MODE_SIZE (<MODE>mode) - 1; i >= 0; --i)
{
rtx part = simplify_gen_subreg (QImode, operands[0], <MODE>mode, i);

2
external/gpl3/gcc/dist/gcc/config/elfos.h vendored
View File

@ -287,7 +287,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
/* Write the extra assembler code needed to declare an object properly. */
#ifdef HAVE_GAS_GNU_UNIQUE_OBJECT
#define USE_GNU_UNIQUE_OBJECT 1
#define USE_GNU_UNIQUE_OBJECT flag_gnu_unique
#else
#define USE_GNU_UNIQUE_OBJECT 0
#endif

79
external/gpl3/gcc/dist/gcc/config/i386/i386.md vendored
View File

@ -5339,66 +5339,37 @@
;; Avoid store forwarding (partial memory) stall penalty by extending
;; SImode value to DImode through XMM register instead of pushing two
;; SImode values to stack. Note that even !TARGET_INTER_UNIT_MOVES
;; targets benefit from this optimization. Also note that fild
;; loads from memory only.
;; SImode values to stack. Also note that fild loads from memory only.
(define_insn "*floatunssi<mode>2_1"
[(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
(define_insn_and_split "*floatunssi<mode>2_i387_with_xmm"
[(set (match_operand:X87MODEF 0 "register_operand" "=f")
(unsigned_float:X87MODEF
(match_operand:SI 1 "nonimmediate_operand" "x,m")))
(clobber (match_operand:DI 2 "memory_operand" "=m,m"))
(clobber (match_scratch:SI 3 "=X,x"))]
(match_operand:SI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:DI 3 "=x"))
(clobber (match_operand:DI 2 "memory_operand" "=m"))]
"!TARGET_64BIT
&& TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE"
&& TARGET_SSE2 && TARGET_INTER_UNIT_MOVES"
"#"
"&& reload_completed"
[(set (match_dup 3) (zero_extend:DI (match_dup 1)))
(set (match_dup 2) (match_dup 3))
(set (match_dup 0)
(float:X87MODEF (match_dup 2)))]
""
[(set_attr "type" "multi")
(set_attr "mode" "<MODE>")])
(define_split
[(set (match_operand:X87MODEF 0 "register_operand")
(unsigned_float:X87MODEF
(match_operand:SI 1 "register_operand")))
(clobber (match_operand:DI 2 "memory_operand"))
(clobber (match_scratch:SI 3))]
"!TARGET_64BIT
&& TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE
&& reload_completed"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0)
(float:X87MODEF (match_dup 2)))]
"operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);")
(define_split
[(set (match_operand:X87MODEF 0 "register_operand")
(unsigned_float:X87MODEF
(match_operand:SI 1 "memory_operand")))
(clobber (match_operand:DI 2 "memory_operand"))
(clobber (match_scratch:SI 3))]
"!TARGET_64BIT
&& TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE
&& reload_completed"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0)
(float:X87MODEF (match_dup 2)))]
{
emit_move_insn (operands[3], operands[1]);
operands[3] = simplify_gen_subreg (DImode, operands[3], SImode, 0);
})
(define_expand "floatunssi<mode>2"
[(parallel
[(set (match_operand:X87MODEF 0 "register_operand")
(unsigned_float:X87MODEF
(match_operand:SI 1 "nonimmediate_operand")))
(clobber (match_dup 2))
(clobber (match_scratch:SI 3))])]
(clobber (match_scratch:DI 3))
(clobber (match_dup 2))])]
"!TARGET_64BIT
&& ((TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE)
&& TARGET_SSE2 && TARGET_INTER_UNIT_MOVES)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
@ -13545,7 +13516,8 @@
(set (reg:CCFP FPSR_REG)
(unspec:CCFP [(match_dup 2) (match_dup 3)]
UNSPEC_C2_FLAG))]
"TARGET_USE_FANCY_MATH_387"
"TARGET_USE_FANCY_MATH_387
&& flag_finite_math_only"
"fprem"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
@ -13554,7 +13526,8 @@
[(use (match_operand:XF 0 "register_operand"))
(use (match_operand:XF 1 "general_operand"))
(use (match_operand:XF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
"TARGET_USE_FANCY_MATH_387
&& flag_finite_math_only"
{
rtx label = gen_label_rtx ();
@ -13577,7 +13550,8 @@
[(use (match_operand:MODEF 0 "register_operand"))
(use (match_operand:MODEF 1 "general_operand"))
(use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
"TARGET_USE_FANCY_MATH_387
&& flag_finite_math_only"
{
rtx (*gen_truncxf) (rtx, rtx);
@ -13616,7 +13590,8 @@
(set (reg:CCFP FPSR_REG)
(unspec:CCFP [(match_dup 2) (match_dup 3)]
UNSPEC_C2_FLAG))]
"TARGET_USE_FANCY_MATH_387"
"TARGET_USE_FANCY_MATH_387
&& flag_finite_math_only"
"fprem1"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
@ -13625,7 +13600,8 @@
[(use (match_operand:XF 0 "register_operand"))
(use (match_operand:XF 1 "general_operand"))
(use (match_operand:XF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
"TARGET_USE_FANCY_MATH_387
&& flag_finite_math_only"
{
rtx label = gen_label_rtx ();
@ -13648,7 +13624,8 @@
[(use (match_operand:MODEF 0 "register_operand"))
(use (match_operand:MODEF 1 "general_operand"))
(use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
"TARGET_USE_FANCY_MATH_387
&& flag_finite_math_only"
{
rtx (*gen_truncxf) (rtx, rtx);

12
external/gpl3/gcc/dist/gcc/config/microblaze/microblaze.md vendored
View File

@ -1119,18 +1119,6 @@
}
)
;;Load and store reverse
(define_insn "movsi4_rev"
[(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Q")
(bswap:SI (match_operand:SF 1 "reg_or_mem_operand" "Q,r")))]
"TARGET_REORDER"
"@
lwr\t%0,%y1,r0
swr\t%1,%y0,r0"
[(set_attr "type" "load,store")
(set_attr "mode" "SI")
(set_attr "length" "4,4")])
;; 32-bit floating point moves
(define_expand "movsf"

4
external/gpl3/gcc/dist/gcc/config/microblaze/predicates.md vendored
View File

@ -85,10 +85,6 @@
(ior (match_operand 0 "const_0_operand")
(match_operand 0 "register_operand")))
(define_predicate "reg_or_mem_operand"
(ior (match_operand 0 "memory_operand")
(match_operand 0 "register_operand")))
;; Return if the operand is either the PC or a label_ref.
(define_special_predicate "pc_or_label_operand"
(ior (match_code "pc,label_ref")

16
external/gpl3/gcc/dist/gcc/config/rs6000/constraints.md vendored
View File

@ -65,6 +65,20 @@
(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
"If -mmfpgpr was used, a floating point register or NO_REGS.")
(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]"
"Floating point register if direct moves are available, or NO_REGS.")
;; At present, DImode is not allowed in the Altivec registers. If in the
;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS.
(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
"FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
"FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]"
"FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.")
(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
"Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
@ -98,7 +112,7 @@
"Floating point register if the STFIWX instruction is enabled or NO_REGS.")
(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"
"VSX vector register to hold scalar float values or NO_REGS.")
"FP or VSX register to perform ISA 2.07 float ops or NO_REGS.")
(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
"Floating point register if the LFIWZX instruction is enabled or NO_REGS.")

2
external/gpl3/gcc/dist/gcc/config/rs6000/freebsd64.h vendored
View File

@ -367,7 +367,7 @@ extern int dot_symbols;
/* PowerPC64 Linux word-aligns FP doubles when -malign-power is given. */
#undef ADJUST_FIELD_ALIGN
#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
((TARGET_ALTIVEC && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
(rs6000_special_adjust_field_align_p ((FIELD), (COMPUTED)) \
? 128 \
: (TARGET_64BIT \
&& TARGET_ALIGN_NATURAL == 0 \

2
external/gpl3/gcc/dist/gcc/config/rs6000/htm.md vendored
View File

@ -179,7 +179,7 @@
(const_int 0)]
UNSPECV_HTM_TABORTWCI))
(set (subreg:CC (match_dup 2) 0) (match_dup 1))
(set (match_dup 3) (lshiftrt:SI (match_dup 2) (const_int 24)))
(set (match_dup 3) (lshiftrt:SI (match_dup 2) (const_int 28)))
(parallel [(set (match_operand:SI 0 "int_reg_operand" "")
(and:SI (match_dup 3) (const_int 15)))
(clobber (scratch:CC))])]

2
external/gpl3/gcc/dist/gcc/config/rs6000/linux64.h vendored
View File

@ -246,7 +246,7 @@ extern int dot_symbols;
/* PowerPC64 Linux word-aligns FP doubles when -malign-power is given. */
#undef ADJUST_FIELD_ALIGN
#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
((TARGET_ALTIVEC && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
(rs6000_special_adjust_field_align_p ((FIELD), (COMPUTED)) \
? 128 \
: (TARGET_64BIT \
&& TARGET_ALIGN_NATURAL == 0 \

85
external/gpl3/gcc/dist/gcc/config/rs6000/predicates.md vendored
View File

@ -1795,7 +1795,7 @@
(define_predicate "fusion_gpr_mem_load"
(match_code "mem,sign_extend,zero_extend")
{
rtx addr;
rtx addr, base, offset;
/* Handle sign/zero extend. */
if (GET_CODE (op) == ZERO_EXTEND
@ -1825,24 +1825,79 @@
}
addr = XEXP (op, 0);
if (GET_CODE (addr) == PLUS)
{
rtx base = XEXP (addr, 0);
rtx offset = XEXP (addr, 1);
if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
return 0;
return (base_reg_operand (base, GET_MODE (base))
&& satisfies_constraint_I (offset));
}
base = XEXP (addr, 0);
if (!base_reg_operand (base, GET_MODE (base)))
return 0;
offset = XEXP (addr, 1);
if (GET_CODE (addr) == PLUS)
return satisfies_constraint_I (offset);
else if (GET_CODE (addr) == LO_SUM)
{
rtx base = XEXP (addr, 0);
rtx offset = XEXP (addr, 1);
if (!base_reg_operand (base, GET_MODE (base)))
return 0;
else if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
return small_toc_ref (offset, GET_MODE (offset));
else if (TARGET_ELF && !TARGET_POWERPC64)
return CONSTANT_P (offset);
}
return 0;
})
;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
;; memory field with both the addis and the memory offset. Sign extension
;; is not handled here, since lha and lwa are not fused.
(define_predicate "fusion_gpr_mem_combo"
(match_code "mem,zero_extend")
{
rtx addr, base, offset;
/* Handle zero extend. */
if (GET_CODE (op) == ZERO_EXTEND)
{
op = XEXP (op, 0);
mode = GET_MODE (op);
}
if (!MEM_P (op))
return 0;
switch (mode)
{
case QImode:
case HImode:
case SImode:
break;
case DImode:
if (!TARGET_POWERPC64)
return 0;
break;
default:
return 0;
}
addr = XEXP (op, 0);
if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
return 0;
base = XEXP (addr, 0);
if (!fusion_gpr_addis (base, GET_MODE (base)))
return 0;
offset = XEXP (addr, 1);
if (GET_CODE (addr) == PLUS)
return satisfies_constraint_I (offset);
else if (GET_CODE (addr) == LO_SUM)
{
if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
return small_toc_ref (offset, GET_MODE (offset));
else if (TARGET_ELF && !TARGET_POWERPC64)

21
external/gpl3/gcc/dist/gcc/config/rs6000/rs6000-builtin.def vendored
View File

@ -622,19 +622,12 @@
| RS6000_BTC_TERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
/* Miscellaneous builtins. */
#define BU_MISC_1(ENUM, NAME, ATTR, ICODE) \
/* 128-bit long double floating point builtins. */
#define BU_LDBL128_2(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_" NAME, /* NAME */ \
RS6000_BTM_HARD_FLOAT, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_UNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_MISC_2(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_" NAME, /* NAME */ \
RS6000_BTM_HARD_FLOAT, /* MASK */ \
(RS6000_BTM_HARD_FLOAT /* MASK */ \
| RS6000_BTM_LDBL128), \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
@ -1593,10 +1586,8 @@ BU_P8V_MISC_3 (BCDSUB_OV, "bcdsub_ov", CONST, bcdsub_unordered)
BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd)
BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd)
BU_MISC_2 (PACK_TF, "pack_longdouble", CONST, packtf)
BU_MISC_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf)
BU_MISC_1 (UNPACK_TF_0, "longdouble_dw0", CONST, unpacktf_0)
BU_MISC_1 (UNPACK_TF_1, "longdouble_dw1", CONST, unpacktf_1)
BU_LDBL128_2 (PACK_TF, "pack_longdouble", CONST, packtf)
BU_LDBL128_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf)
BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti)
BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti)

3
external/gpl3/gcc/dist/gcc/config/rs6000/rs6000-c.c vendored
View File

@ -4126,7 +4126,8 @@ altivec_build_resolved_builtin (tree *args, int n,
argument) is reversed. Patch the arguments here before building
the resolved CALL_EXPR. */
if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P
&& desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P)
&& desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P
&& desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P)
{
tree t;
t = args[2], args[2] = args[1], args[1] = t;

7
external/gpl3/gcc/dist/gcc/config/rs6000/rs6000-protos.h vendored
View File

@ -79,9 +79,9 @@ extern int mems_ok_for_quad_peep (rtx, rtx);
extern bool gpr_or_gpr_p (rtx, rtx);
extern bool direct_move_p (rtx, rtx);
extern bool quad_load_store_p (rtx, rtx);
extern bool fusion_gpr_load_p (rtx *, bool);
extern bool fusion_gpr_load_p (rtx, rtx, rtx, rtx);
extern void expand_fusion_gpr_load (rtx *);
extern const char *emit_fusion_gpr_load (rtx *);
extern const char *emit_fusion_gpr_load (rtx, rtx);
extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx,
enum reg_class);
extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
@ -153,6 +153,7 @@ extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool, rtx);
#ifdef TREE_CODE
extern unsigned int rs6000_data_alignment (tree, unsigned int, enum data_align);
extern bool rs6000_special_adjust_field_align_p (tree, unsigned int);
extern unsigned int rs6000_special_round_type_align (tree, unsigned int,
unsigned int);
extern unsigned int darwin_rs6000_special_round_type_align (tree, unsigned int,
@ -161,7 +162,7 @@ extern tree altivec_resolve_overloaded_builtin (location_t, tree, void *);
extern rtx rs6000_libcall_value (enum machine_mode);
extern rtx rs6000_va_arg (tree, tree);
extern int function_ok_for_sibcall (tree);
extern int rs6000_reg_parm_stack_space (tree);
extern int rs6000_reg_parm_stack_space (tree, bool);
extern void rs6000_elf_declare_function_name (FILE *, const char *, tree);
extern bool rs6000_elf_in_small_data_p (const_tree);
#ifdef ARGS_SIZE_RTX

24
external/gpl3/gcc/dist/gcc/config/rs6000/rs6000.h vendored
View File

@ -1438,6 +1438,10 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */
RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */
RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */
RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
RS6000_CONSTRAINT_wm, /* VSX register for direct move */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
@ -1462,6 +1466,9 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
#define VSX_REG_CLASS_P(CLASS) \
((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
/* Return whether a given register class targets general purpose registers. */
#define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
@ -1593,7 +1600,14 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
/* Define this if stack space is still allocated for a parameter passed
in a register. The value is the number of bytes allocated to this
area. */
#define REG_PARM_STACK_SPACE(FNDECL) rs6000_reg_parm_stack_space((FNDECL))
#define REG_PARM_STACK_SPACE(FNDECL) \
rs6000_reg_parm_stack_space ((FNDECL), false)
/* Define this macro if space guaranteed when compiling a function body
is different to space required when making a call, a situation that
can arise with K&R style function definitions. */
#define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
rs6000_reg_parm_stack_space ((FNDECL), true)
/* Define this if the above stack space is to be considered part of the
space allocated by the caller. */
@ -2483,8 +2497,8 @@ extern int frame_pointer_needed;
#define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
/* Builtin targets. For now, we reuse the masks for those options that are in
target flags, and pick two random bits for SPE and paired which aren't in
target_flags. */
target flags, and pick three random bits for SPE, paired and ldbl128 which
aren't in target_flags. */
#define RS6000_BTM_ALWAYS 0 /* Always enabled. */
#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
@ -2501,6 +2515,7 @@ extern int frame_pointer_needed;
#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
| RS6000_BTM_VSX \
@ -2514,7 +2529,8 @@ extern int frame_pointer_needed;
| RS6000_BTM_POPCNTD \
| RS6000_BTM_CELL \
| RS6000_BTM_DFP \
| RS6000_BTM_HARD_FLOAT)
| RS6000_BTM_HARD_FLOAT \
| RS6000_BTM_LDBL128)
/* Define builtin enum index. */

122
external/gpl3/gcc/dist/gcc/config/rs6000/rs6000.md vendored
View File

@ -134,6 +134,7 @@
UNSPEC_UNPACK_128BIT
UNSPEC_PACK_128BIT
UNSPEC_LSQ
UNSPEC_FUSION_GPR
])
;;
@ -317,7 +318,24 @@
(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
; Definitions for 32-bit fpr direct move
(define_mode_attr f32_dm [(SF "wn") (SD "wm")])
; At present, the decimal modes are not allowed in the traditional altivec
; registers, so restrict the constraints to just the traditional FPRs.
(define_mode_attr f32_dm [(SF "wn") (SD "wh")])
; Definitions for 32-bit VSX
(define_mode_attr f32_vsx [(SF "ww") (SD "wn")])
; Definitions for 32-bit use of altivec registers
(define_mode_attr f32_av [(SF "wu") (SD "wn")])
; Definitions for 64-bit VSX
(define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
; Definitions for 64-bit direct move
(define_mode_attr f64_dm [(DF "wk") (DD "wh")])
; Definitions for 64-bit use of altivec registers
(define_mode_attr f64_av [(DF "wv") (DD "wn")])
; These modes do not fit in integer registers in 32-bit mode.
; but on e500v2, the gpr are 64 bit registers
@ -424,7 +442,7 @@
;; either.
;; Mode attribute for boolean operation register constraints for output
(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v")
(PTI "&r,r,r")
(V16QI "wa,v,&?r,?r,?r")
(V8HI "wa,v,&?r,?r,?r")
@ -435,7 +453,7 @@
(V1TI "wa,v,&?r,?r,?r")])
;; Mode attribute for boolean operation register constraints for operand1
(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v")
(PTI "r,0,r")
(V16QI "wa,v,r,0,r")
(V8HI "wa,v,r,0,r")
@ -446,7 +464,7 @@
(V1TI "wa,v,r,0,r")])
;; Mode attribute for boolean operation register constraints for operand2
(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v")
(PTI "r,r,0")
(V16QI "wa,v,r,r,0")
(V8HI "wa,v,r,r,0")
@ -459,7 +477,7 @@
;; Mode attribute for boolean operation register constraints for operand1
;; for one_cmpl. To simplify things, we repeat the constraint where 0
;; is used for operand1 or operand2
(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v")
(PTI "r,0,0")
(V16QI "wa,v,r,0,0")
(V8HI "wa,v,r,0,0")
@ -566,7 +584,7 @@
"")
(define_insn "*zero_extendsidi2_lfiwzx"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
(zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
"TARGET_POWERPC64 && TARGET_LFIWZX"
"@
@ -736,8 +754,8 @@
"")
(define_insn "*extendsidi2_lfiwax"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")
(sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r,r,Z,Z")))]
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
(sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
"TARGET_POWERPC64 && TARGET_LFIWAX"
"@
lwa%U1%X1 %0,%1
@ -760,7 +778,7 @@
(define_insn "*extendsidi2_nocell"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
(sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r")))]
"TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
"@
lwa%U1%X1 %0,%1
@ -5614,7 +5632,7 @@
; We don't define lfiwax/lfiwzx with the normal definition, because we
; don't want to support putting SImode in FPR registers.
(define_insn "lfiwax"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWAX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
@ -5694,7 +5712,7 @@
(set_attr "type" "fpload")])
(define_insn "lfiwzx"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWZX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
@ -9210,8 +9228,8 @@
}")
(define_insn "mov<mode>_hardfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
(match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
(match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r, h, 0, G,Fn"))]
"(gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))
&& (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
@ -9422,8 +9440,8 @@
;; reloading.
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,!r,!r,!r")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,G,H,F"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@ -9491,8 +9509,8 @@
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,<f64_dm>")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,r,h,0,G,H,F,wg,r,<f64_dm>,r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@ -10272,8 +10290,8 @@
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")
(match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]
[(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
(match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
@ -10293,7 +10311,8 @@
mftgpr %0,%1
mffgpr %0,%1
mfvsrd %0,%x1
mtvsrd %x0,%1"
mtvsrd %x0,%1
xxlxor %x0,%x0,%x0"
[(set_attr_alternative "type"
[(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
@ -10334,8 +10353,9 @@
(const_string "mftgpr")
(const_string "mffgpr")
(const_string "mftgpr")
(const_string "mffgpr")])
(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
(const_string "mffgpr")
(const_string "vecsimple")])
(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
;; immediate value valid for a single instruction hiding in a const_double
(define_insn ""
@ -15751,22 +15771,9 @@
;; a GPR. The addis instruction must be adjacent to the load, and use the same
;; register that is being loaded. The fused ops must be physically adjacent.
;; We use define_peephole for the actual addis/load, and the register used to
;; hold the addis value must be the same as the register being loaded. We use
;; define_peephole2 to change the register used for addis to be the register
;; being loaded, since we can look at whether it is dead after the load insn.
(define_peephole
[(set (match_operand:P 0 "base_reg_operand" "")
(match_operand:P 1 "fusion_gpr_addis" ""))
(set (match_operand:INT1 2 "base_reg_operand" "")
(match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
"TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"
{
return emit_fusion_gpr_load (operands);
}
[(set_attr "type" "load")
(set_attr "length" "8")])
;; Find cases where the addis that feeds into a load instruction is either used
;; once or is the same as the target register, and replace it with the fusion
;; insn
(define_peephole2
[(set (match_operand:P 0 "base_reg_operand" "")
@ -15774,15 +15781,28 @@
(set (match_operand:INT1 2 "base_reg_operand" "")
(match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
"TARGET_P8_FUSION
&& (REGNO (operands[0]) != REGNO (operands[2])
|| GET_CODE (operands[3]) == SIGN_EXTEND)
&& fusion_gpr_load_p (operands, true)"
&& fusion_gpr_load_p (operands[0], operands[1], operands[2],
operands[3])"
[(const_int 0)]
{
expand_fusion_gpr_load (operands);
DONE;
})
;; Fusion insn, created by the define_peephole2 above (and eventually by
;; reload)
(define_insn "fusion_gpr_load_<mode>"
[(set (match_operand:INT1 0 "base_reg_operand" "=&b")
(unspec:INT1 [(match_operand:INT1 1 "fusion_gpr_mem_combo" "")]
UNSPEC_FUSION_GPR))]
"TARGET_P8_FUSION"
{
return emit_fusion_gpr_load (operands[0], operands[1]);
}
[(set_attr "type" "load")
(set_attr "length" "8")])
;; Miscellaneous ISA 2.06 (power7) instructions
(define_insn "addg6s"
@ -15847,26 +15867,6 @@
""
"")
;; The Advance Toolchain 7.0-3 added private builtins: __builtin_longdouble_dw0
;; and __builtin_longdouble_dw1 to optimize glibc. Add support for these
;; builtins here.
(define_expand "unpacktf_0"
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(unspec:DF [(match_operand:TF 1 "register_operand" "")
(const_int 0)]
UNSPEC_UNPACK_128BIT))]
""
"")
(define_expand "unpacktf_1"
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(unspec:DF [(match_operand:TF 1 "register_operand" "")
(const_int 1)]
UNSPEC_UNPACK_128BIT))]
""
"")
(define_insn_and_split "unpack<mode>_dm"
[(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
(unspec:<FP128_64>

362
external/gpl3/gcc/dist/gcc/config/rs6000/vsx.md vendored
View File

@ -24,6 +24,13 @@
;; Iterator for the 2 64-bit vector types
(define_mode_iterator VSX_D [V2DF V2DI])
;; Iterator for the 2 64-bit vector types + 128-bit types that are loaded with
;; lxvd2x to properly handle swapping words on little endian
(define_mode_iterator VSX_LE [V2DF
V2DI
V1TI
(TI "VECTOR_MEM_VSX_P (TImode)")])
;; Iterator for the 2 32-bit vector types
(define_mode_iterator VSX_W [V4SF V4SI])
@ -79,19 +86,26 @@
(V4SF "wf")
(V2DI "wd")
(V2DF "wd")
(DI "wi")
(DF "ws")
(SF "d")
(SF "ww")
(V1TI "v")
(TI "wt")])
;; Map the register class used for float<->int conversions
;; Map the register class used for float<->int conversions (floating point side)
;; VSr2 is the preferred register class, VSr3 is any register class that will
;; hold the data
(define_mode_attr VSr2 [(V2DF "wd")
(V4SF "wf")
(DF "ws")])
(DF "ws")
(SF "ww")
(DI "wi")])
(define_mode_attr VSr3 [(V2DF "wa")
(V4SF "wa")
(DF "ws")])
(DF "ws")
(SF "ww")
(DI "wi")])
;; Map the register class for sp<->dp float conversions, destination
(define_mode_attr VSr4 [(SF "ws")
@ -99,12 +113,27 @@
(V2DF "wd")
(V4SF "v")])
;; Map the register class for sp<->dp float conversions, destination
;; Map the register class for sp<->dp float conversions, source
(define_mode_attr VSr5 [(SF "ws")
(DF "f")
(V2DF "v")
(V4SF "wd")])
;; The VSX register class that a type can occupy, even if it is not the
;; preferred register class (VSr is the preferred register class that will get
;; allocated first).
(define_mode_attr VSa [(V16QI "wa")
(V8HI "wa")
(V4SI "wa")
(V4SF "wa")
(V2DI "wa")
(V2DF "wa")
(DI "wi")
(DF "ws")
(SF "ww")
(V1TI "wa")
(TI "wt")])
;; Same size integer type for floating point data
(define_mode_attr VSi [(V4SF "v4si")
(V2DF "v2di")
@ -200,6 +229,16 @@
(V2DF "V4DF")
(V1TI "V2TI")])
;; Map register class for 64-bit element in 128-bit vector for direct moves
;; to/from gprs
(define_mode_attr VS_64dm [(V2DF "wk")
(V2DI "wj")])
;; Map register class for 64-bit element in 128-bit vector for normal register
;; to register moves
(define_mode_attr VS_64reg [(V2DF "ws")
(V2DI "wi")])
;; Constants for creating unspecs
(define_c_enum "unspec"
[UNSPEC_VSX_CONCAT
@ -228,8 +267,8 @@
;; The patterns for LE permuted loads and stores come before the general
;; VSX moves so they match first.
(define_insn_and_split "*vsx_le_perm_load_<mode>"
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
(match_operand:VSX_D 1 "memory_operand" "Z"))]
[(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>")
(match_operand:VSX_LE 1 "memory_operand" "Z"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX"
"#"
"!BYTES_BIG_ENDIAN && TARGET_VSX"
@ -251,7 +290,7 @@
(set_attr "length" "8")])
(define_insn_and_split "*vsx_le_perm_load_<mode>"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
(match_operand:VSX_W 1 "memory_operand" "Z"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX"
"#"
@ -342,16 +381,16 @@
(set_attr "length" "8")])
(define_insn "*vsx_le_perm_store_<mode>"
[(set (match_operand:VSX_D 0 "memory_operand" "=Z")
(match_operand:VSX_D 1 "vsx_register_operand" "+wa"))]
[(set (match_operand:VSX_LE 0 "memory_operand" "=Z")
(match_operand:VSX_LE 1 "vsx_register_operand" "+<VSa>"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX"
"#"
[(set_attr "type" "vecstore")
(set_attr "length" "12")])
(define_split
[(set (match_operand:VSX_D 0 "memory_operand" "")
(match_operand:VSX_D 1 "vsx_register_operand" ""))]
[(set (match_operand:VSX_LE 0 "memory_operand" "")
(match_operand:VSX_LE 1 "vsx_register_operand" ""))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed"
[(set (match_dup 2)
(vec_select:<MODE>
@ -369,8 +408,8 @@
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
[(set (match_operand:VSX_D 0 "memory_operand" "")
(match_operand:VSX_D 1 "vsx_register_operand" ""))]
[(set (match_operand:VSX_LE 0 "memory_operand" "")
(match_operand:VSX_LE 1 "vsx_register_operand" ""))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed"
[(set (match_dup 1)
(vec_select:<MODE>
@ -388,7 +427,7 @@
(define_insn "*vsx_le_perm_store_<mode>"
[(set (match_operand:VSX_W 0 "memory_operand" "=Z")
(match_operand:VSX_W 1 "vsx_register_operand" "+wa"))]
(match_operand:VSX_W 1 "vsx_register_operand" "+<VSa>"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX"
"#"
[(set_attr "type" "vecstore")
@ -578,8 +617,8 @@
(define_insn "*vsx_mov<mode>"
[(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,wQ,?&r,??Y,??r,??r,<VSr>,?wa,*r,v,wZ, v")
(match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]
[(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?<VSa>,?<VSa>,wQ,?&r,??Y,??r,??r,<VSr>,?<VSa>,*r,v,wZ, v")
(match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,<VSa>,Z,<VSa>,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]
"VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
@ -681,36 +720,36 @@
;; instructions are now combined with the insn for the traditional floating
;; point unit.
(define_insn "*vsx_add<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvadd<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_sub<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvsub<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_mul<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmul<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_mul>")])
(define_insn "*vsx_div<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvdiv<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_div>")
@ -746,8 +785,8 @@
(define_insn "*vsx_tdiv<mode>3_internal"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x")
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")]
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_VSX_TDIV))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>tdiv<VSs> %0,%x1,%x2"
@ -755,8 +794,8 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_fre<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_FRES))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvre<VSs> %x0,%x1"
@ -764,60 +803,60 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_neg<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvneg<VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_abs<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvabs<VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_nabs<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(neg:VSX_F
(abs:VSX_F
(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa"))))]
(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvnabs<VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_smax<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmax<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_smin<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmin<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_sqrt<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvsqrt<VSs> %x0,%x1"
[(set_attr "type" "<VStype_sqrt>")
(set_attr "fp_type" "<VSfptype_sqrt>")])
(define_insn "*vsx_rsqrte<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_RSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvrsqrte<VSs> %x0,%x1"
@ -852,7 +891,7 @@
(define_insn "*vsx_tsqrt<mode>2_internal"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x")
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_VSX_TSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>tsqrt<VSs> %0,%x1"
@ -865,11 +904,11 @@
;; multiply.
(define_insn "*vsx_fmav4sf4"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,v")
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v")
(fma:V4SF
(match_operand:V4SF 1 "vsx_register_operand" "%ws,ws,wa,wa,v")
(match_operand:V4SF 2 "vsx_register_operand" "ws,0,wa,0,v")
(match_operand:V4SF 3 "vsx_register_operand" "0,ws,0,wa,v")))]
(match_operand:V4SF 1 "vsx_register_operand" "%wf,wf,wa,wa,v")
(match_operand:V4SF 2 "vsx_register_operand" "wf,0,wa,0,v")
(match_operand:V4SF 3 "vsx_register_operand" "0,wf,0,wa,v")))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvmaddasp %x0,%x1,%x2
@ -880,11 +919,11 @@
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa")
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wd,wd,?wa,?wa")
(fma:V2DF
(match_operand:V2DF 1 "vsx_register_operand" "%ws,ws,wa,wa")
(match_operand:V2DF 2 "vsx_register_operand" "ws,0,wa,0")
(match_operand:V2DF 3 "vsx_register_operand" "0,ws,0,wa")))]
(match_operand:V2DF 1 "vsx_register_operand" "%wd,wd,wa,wa")
(match_operand:V2DF 2 "vsx_register_operand" "wd,0,wa,0")
(match_operand:V2DF 3 "vsx_register_operand" "0,wd,0,wa")))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"@
xvmaddadp %x0,%x1,%x2
@ -894,12 +933,12 @@
[(set_attr "type" "vecdouble")])
(define_insn "*vsx_fms<mode>4"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa")
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?<VSa>,?<VSa>")
(fma:VSX_F
(match_operand:VSX_F 1 "vsx_register_operand" "%<VSr>,<VSr>,wa,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,wa,0")
(match_operand:VSX_F 1 "vsx_register_operand" "%<VSr>,<VSr>,<VSa>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,<VSa>,0")
(neg:VSX_F
(match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))]
(match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,<VSa>"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"@
xvmsuba<VSs> %x0,%x1,%x2
@ -909,12 +948,12 @@
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfma<mode>4"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa")
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?<VSa>,?<VSa>")
(neg:VSX_F
(fma:VSX_F
(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSr>,wa,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,wa,0")
(match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))]
(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSr>,<VSa>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,<VSa>,0")
(match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,<VSa>"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"@
xvnmadda<VSs> %x0,%x1,%x2
@ -959,27 +998,27 @@
;; Vector conditional expressions (no scalar version for these instructions)
(define_insn "vsx_eq<mode>"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpeq<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_gt<mode>"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpgt<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_ge<mode>"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpge<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
@ -990,10 +1029,10 @@
(define_insn "*vsx_eq_<mode>_p"
[(set (reg:CC 74)
(unspec:CC
[(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))]
[(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
UNSPEC_PREDICATE))
(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(eq:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@ -1003,10 +1042,10 @@
(define_insn "*vsx_gt_<mode>_p"
[(set (reg:CC 74)
(unspec:CC
[(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))]
[(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
UNSPEC_PREDICATE))
(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(gt:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@ -1016,10 +1055,10 @@
(define_insn "*vsx_ge_<mode>_p"
[(set (reg:CC 74)
(unspec:CC
[(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))]
[(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
UNSPEC_PREDICATE))
(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(ge:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@ -1028,33 +1067,33 @@
;; Vector select
(define_insn "*vsx_xxsel<mode>"
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(if_then_else:VSX_L
(ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
(ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_L 4 "zero_constant" ""))
(match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
(match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
[(set_attr "type" "vecperm")])
(define_insn "*vsx_xxsel<mode>_uns"
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(if_then_else:VSX_L
(ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
(ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_L 4 "zero_constant" ""))
(match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
(match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
[(set_attr "type" "vecperm")])
;; Copy sign
(define_insn "vsx_copysign<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(unspec:VSX_F
[(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")]
[(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_COPYSIGN))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcpsgn<VSs> %x0,%x2,%x1"
@ -1067,7 +1106,7 @@
;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX.
;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md.
(define_insn "vsx_float<VSi><mode>2"
[(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa")
[(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?<VSa>")
(float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cvsx<VSc><VSs> %x0,%x1"
@ -1075,7 +1114,7 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_floatuns<VSi><mode>2"
[(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa")
[(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?<VSa>")
(unsigned_float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cvux<VSc><VSs> %x0,%x1"
@ -1084,7 +1123,7 @@
(define_insn "vsx_fix_trunc<mode><VSi>2"
[(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
(fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))]
(fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cv<VSs>sx<VSc>s %x0,%x1"
[(set_attr "type" "<VStype_simple>")
@ -1092,7 +1131,7 @@
(define_insn "vsx_fixuns_trunc<mode><VSi>2"
[(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
(unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))]
(unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cv<VSs>ux<VSc>s %x0,%x1"
[(set_attr "type" "<VStype_simple>")
@ -1100,8 +1139,8 @@
;; Math rounding functions
(define_insn "vsx_x<VSv>r<VSs>i"
[(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
(unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
[(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_VSX_ROUND_I))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>i %x0,%x1"
@ -1109,8 +1148,8 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_x<VSv>r<VSs>ic"
[(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
(unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
[(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_VSX_ROUND_IC))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>ic %x0,%x1"
@ -1118,16 +1157,16 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_btrunc<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>iz %x0,%x1"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_b2trunc<mode>2"
[(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
(unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
[(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_FRIZ))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>iz %x0,%x1"
@ -1135,8 +1174,8 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_floor<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_FRIM))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>im %x0,%x1"
@ -1144,8 +1183,8 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_ceil<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_FRIP))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>ip %x0,%x1"
@ -1160,8 +1199,8 @@
;; scalar single precision instructions internally use the double format.
;; Prefer the altivec registers, since we likely will need to do a vperm
(define_insn "vsx_<VS_spdp_insn>"
[(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?wa")
(unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,wa")]
[(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?<VSa>")
(unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,<VSa>")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"<VS_spdp_insn> %x0,%x1"
@ -1169,8 +1208,8 @@
;; xscvspdp, represent the scalar SF type as V4SF
(define_insn "vsx_xscvspdp"
[(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa")
(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
[(set (match_operand:DF 0 "vsx_register_operand" "=ws")
(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"xscvspdp %x0,%x1"
@ -1197,7 +1236,7 @@
;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs
(define_insn "vsx_xscvdpspn"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,?wa")
[(set (match_operand:V4SF 0 "vsx_register_operand" "=ww,?ww")
(unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wd,wa")]
UNSPEC_VSX_CVDPSPN))]
"TARGET_XSCVDPSPN"
@ -1205,16 +1244,16 @@
[(set_attr "type" "fp")])
(define_insn "vsx_xscvspdpn"
[(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa")
(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
[(set (match_operand:DF 0 "vsx_register_operand" "=ws,?ws")
(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wf,wa")]
UNSPEC_VSX_CVSPDPN))]
"TARGET_XSCVSPDPN"
"xscvspdpn %x0,%x1"
[(set_attr "type" "fp")])
(define_insn "vsx_xscvdpspn_scalar"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
(unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f")]
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,?wa")
(unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww,ww")]
UNSPEC_VSX_CVDPSPN))]
"TARGET_XSCVDPSPN"
"xscvdpspn %x0,%x1"
@ -1302,10 +1341,10 @@
;; since the xsrdpiz instruction does not truncate the value if the floating
;; point value is < LONG_MIN or > LONG_MAX.
(define_insn "*vsx_float_fix_<mode>2"
[(set (match_operand:VSX_DF 0 "vsx_register_operand" "=<VSr>,?wa")
[(set (match_operand:VSX_DF 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(float:VSX_DF
(fix:<VSI>
(match_operand:VSX_DF 1 "vsx_register_operand" "<VSr>,?wa"))))]
(match_operand:VSX_DF 1 "vsx_register_operand" "<VSr>,?<VSa>"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& VECTOR_UNIT_VSX_P (<MODE>mode) && flag_unsafe_math_optimizations
&& !flag_trapping_math && TARGET_FRIZ"
@ -1318,10 +1357,10 @@
;; Build a V2DF/V2DI vector from two scalars
(define_insn "vsx_concat_<mode>"
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?wa")
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(vec_concat:VSX_D
(match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,wa")
(match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")))]
(match_operand:<VS_scalar> 1 "vsx_register_operand" "<VS_64reg>,<VSa>")
(match_operand:<VS_scalar> 2 "vsx_register_operand" "<VS_64reg>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
if (BYTES_BIG_ENDIAN)
@ -1352,18 +1391,18 @@
;; xxpermdi for little endian loads and stores. We need several of
;; these since the form of the PARALLEL differs by mode.
(define_insn "*vsx_xxpermdi2_le_<mode>"
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
(vec_select:VSX_D
(match_operand:VSX_D 1 "vsx_register_operand" "wa")
[(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>")
(vec_select:VSX_LE
(match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>")
(parallel [(const_int 1) (const_int 0)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
"xxpermdi %x0,%x1,%x1,2"
[(set_attr "type" "vecperm")])
(define_insn "*vsx_xxpermdi4_le_<mode>"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
(vec_select:VSX_W
(match_operand:VSX_W 1 "vsx_register_operand" "wa")
(match_operand:VSX_W 1 "vsx_register_operand" "<VSa>")
(parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
@ -1401,16 +1440,16 @@
;; lxvd2x for little endian loads. We need several of
;; these since the form of the PARALLEL differs by mode.
(define_insn "*vsx_lxvd2x2_le_<mode>"
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
(vec_select:VSX_D
(match_operand:VSX_D 1 "memory_operand" "Z")
[(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>")
(vec_select:VSX_LE
(match_operand:VSX_LE 1 "memory_operand" "Z")
(parallel [(const_int 1) (const_int 0)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
"lxvd2x %x0,%y1"
[(set_attr "type" "vecload")])
(define_insn "*vsx_lxvd2x4_le_<mode>"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
(vec_select:VSX_W
(match_operand:VSX_W 1 "memory_operand" "Z")
(parallel [(const_int 2) (const_int 3)
@ -1450,9 +1489,9 @@
;; stxvd2x for little endian stores. We need several of
;; these since the form of the PARALLEL differs by mode.
(define_insn "*vsx_stxvd2x2_le_<mode>"
[(set (match_operand:VSX_D 0 "memory_operand" "=Z")
(vec_select:VSX_D
(match_operand:VSX_D 1 "vsx_register_operand" "wa")
[(set (match_operand:VSX_LE 0 "memory_operand" "=Z")
(vec_select:VSX_LE
(match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>")
(parallel [(const_int 1) (const_int 0)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
"stxvd2x %x1,%y0"
@ -1461,7 +1500,7 @@
(define_insn "*vsx_stxvd2x4_le_<mode>"
[(set (match_operand:VSX_W 0 "memory_operand" "=Z")
(vec_select:VSX_W
(match_operand:VSX_W 1 "vsx_register_operand" "wa")
(match_operand:VSX_W 1 "vsx_register_operand" "<VSa>")
(parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
@ -1513,11 +1552,12 @@
;; Set the element of a V2DI/VD2F mode
(define_insn "vsx_set_<mode>"
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa")
(unspec:VSX_D [(match_operand:VSX_D 1 "vsx_register_operand" "wd,wa")
(match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")
(match_operand:QI 3 "u5bit_cint_operand" "i,i")]
UNSPEC_VSX_SET))]
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?<VSa>")
(unspec:VSX_D
[(match_operand:VSX_D 1 "vsx_register_operand" "wd,<VSa>")
(match_operand:<VS_scalar> 2 "vsx_register_operand" "<VS_64reg>,<VSa>")
(match_operand:QI 3 "u5bit_cint_operand" "i,i")]
UNSPEC_VSX_SET))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
int idx_first = BYTES_BIG_ENDIAN ? 0 : 1;
@ -1582,7 +1622,7 @@
(define_insn_and_split "vsx_extract_v4sf"
[(set (match_operand:SF 0 "vsx_register_operand" "=f,f")
(vec_select:SF
(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
(match_operand:V4SF 1 "vsx_register_operand" "<VSa>,<VSa>")
(parallel [(match_operand:QI 2 "u5bit_cint_operand" "O,i")])))
(clobber (match_scratch:V4SF 3 "=X,0"))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
@ -1606,7 +1646,7 @@
{
if (GET_CODE (op3) == SCRATCH)
op3 = gen_reg_rtx (V4SFmode);
emit_insn (gen_vsx_xxsldwi_v4sf (op3, op1, op1, op2));
emit_insn (gen_vsx_xxsldwi_v4sf (op3, op1, op1, GEN_INT (ele)));
tmp = op3;
}
emit_insn (gen_vsx_xscvspdp_scalar2 (op0, tmp));
@ -1765,9 +1805,9 @@
;; V2DF/V2DI splat
(define_insn "vsx_splat_<mode>"
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?wa,?wa,?wa")
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?<VSa>,?<VSa>,?<VSa>")
(vec_duplicate:VSX_D
(match_operand:<VS_scalar> 1 "splat_input_operand" "ws,f,Z,wa,wa,Z")))]
(match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,f,Z,<VSa>,<VSa>,Z")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
xxpermdi %x0,%x1,%x1,0
@ -1780,10 +1820,10 @@
;; V4SF/V4SI splat
(define_insn "vsx_xxspltw_<mode>"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
(vec_duplicate:VSX_W
(vec_select:<VS_scalar>
(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")
(match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
(parallel
[(match_operand:QI 2 "u5bit_cint_operand" "i,i")]))))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@ -1796,8 +1836,8 @@
[(set_attr "type" "vecperm")])
(define_insn "vsx_xxspltw_<mode>_direct"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")
(unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
(unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
(match_operand:QI 2 "u5bit_cint_operand" "i,i")]
UNSPEC_VSX_XXSPLTW))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@ -1806,11 +1846,11 @@
;; V4SF/V4SI interleave
(define_insn "vsx_xxmrghw_<mode>"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
(vec_select:VSX_W
(vec_concat:<VS_double>
(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")
(match_operand:VSX_W 2 "vsx_register_operand" "wf,wa"))
(match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
(match_operand:VSX_W 2 "vsx_register_operand" "wf,<VSa>"))
(parallel [(const_int 0) (const_int 4)
(const_int 1) (const_int 5)])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@ -1823,11 +1863,11 @@
[(set_attr "type" "vecperm")])
(define_insn "vsx_xxmrglw_<mode>"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
(vec_select:VSX_W
(vec_concat:<VS_double>
(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")
(match_operand:VSX_W 2 "vsx_register_operand" "wf,?wa"))
(match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
(match_operand:VSX_W 2 "vsx_register_operand" "wf,?<VSa>"))
(parallel [(const_int 2) (const_int 6)
(const_int 3) (const_int 7)])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@ -1841,9 +1881,9 @@
;; Shift left double by word immediate
(define_insn "vsx_xxsldwi_<mode>"
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=wa")
(unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "wa")
(match_operand:VSX_L 2 "vsx_register_operand" "wa")
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSa>")
(unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "<VSa>")
(match_operand:VSX_L 2 "vsx_register_operand" "<VSa>")
(match_operand:QI 3 "u5bit_cint_operand" "i")]
UNSPEC_VSX_SLDWI))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@ -1924,7 +1964,7 @@
;; to the top element of the V2DF array without doing an extract.
(define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar"
[(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?wa,ws,?wa")
[(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?ws,ws,?ws")
(vec_select:DF
(VEC_reduc:V2DF
(vec_concat:V2DF

2
external/gpl3/gcc/dist/gcc/config/sh/sh.opt vendored
View File

@ -343,7 +343,7 @@ Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
Cost to assume for a multiply insn
musermode
Target Report RejectNegative Var(TARGET_USERMODE)
Target Var(TARGET_USERMODE)
Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode.
;; We might want to enable this by default for TARGET_HARD_SH4, because

18
external/gpl3/gcc/dist/gcc/config/sh/sync.md vendored
View File

@ -466,6 +466,7 @@
(set (mem:SI (match_dup 1))
(unspec:SI
[(match_operand:SI 2 "arith_operand" "rI08")] UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
@ -484,6 +485,7 @@
(set (mem:QIHI (match_dup 1))
(unspec:QIHI
[(match_operand:QIHI 2 "register_operand" "r")] UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))
(clobber (match_scratch:SI 3 "=&r"))
(clobber (match_scratch:SI 4 "=1"))]
@ -617,6 +619,7 @@
[(FETCHOP:SI (mem:SI (match_dup 1))
(match_operand:SI 2 "<fetchop_predicate>" "<fetchop_constraint>"))]
UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
@ -637,6 +640,7 @@
[(FETCHOP:QIHI (mem:QIHI (match_dup 1))
(match_operand:QIHI 2 "<fetchop_predicate>" "<fetchop_constraint>"))]
UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))
(clobber (match_scratch:SI 3 "=&r"))
(clobber (match_scratch:SI 4 "=1"))]
@ -784,6 +788,7 @@
[(not:SI (and:SI (mem:SI (match_dup 1))
(match_operand:SI 2 "logical_operand" "rK08")))]
UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
@ -805,6 +810,7 @@
[(not:QIHI (and:QIHI (mem:QIHI (match_dup 1))
(match_operand:QIHI 2 "logical_operand" "rK08")))]
UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))
(clobber (match_scratch:SI 3 "=&r"))
(clobber (match_scratch:SI 4 "=1"))]
@ -903,7 +909,7 @@
" and %0,%3" "\n"
" not %3,%3" "\n"
" mov.<bwl> %3,@%1" "\n"
" stc %4,sr";
" ldc %4,sr";
}
[(set_attr "length" "20")])
@ -960,7 +966,8 @@
(set (mem:SI (match_dup 1))
(unspec:SI
[(FETCHOP:SI (mem:SI (match_dup 1)) (match_dup 2))]
UNSPEC_ATOMIC))]
UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
{
@ -980,6 +987,7 @@
(unspec:QIHI
[(FETCHOP:QIHI (mem:QIHI (match_dup 1)) (match_dup 2))]
UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))
(clobber (match_scratch:SI 3 "=&r"))
(clobber (match_scratch:SI 4 "=1"))]
@ -1124,7 +1132,8 @@
(set (mem:SI (match_dup 1))
(unspec:SI
[(not:SI (and:SI (mem:SI (match_dup 1)) (match_dup 2)))]
UNSPEC_ATOMIC))]
UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))]
"TARGET_ATOMIC_HARD_LLCS
|| (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)"
{
@ -1145,6 +1154,7 @@
(unspec:QIHI
[(not:QIHI (and:QIHI (mem:QIHI (match_dup 1)) (match_dup 2)))]
UNSPEC_ATOMIC))
(set (reg:SI T_REG) (const_int 1))
(clobber (reg:SI R0_REG))
(clobber (match_scratch:SI 3 "=&r"))
(clobber (match_scratch:SI 4 "=1"))]
@ -1353,7 +1363,7 @@
" ldc r0,sr" "\n"
" mov.b @%0,r0" "\n"
" mov.b %1,@%0" "\n"
" stc %2,sr" "\n"
" ldc %2,sr" "\n"
" tst r0,r0";
}
[(set_attr "length" "16")])

64
external/gpl3/gcc/dist/gcc/cp/ChangeLog vendored
View File

@ -1,3 +1,67 @@
2014-08-07 Jason Merrill <jason@redhat.com>
PR c++/61959
* semantics.c (cxx_eval_bare_aggregate): Handle POINTER_PLUS_EXPR.
PR c++/58714
* tree.c (stabilize_expr): A stabilized prvalue is an xvalue.
2014-01-27 Jason Merrill <jason@redhat.com>
PR c++/59823
Core DR 1138
* call.c (reference_binding): Pass LOOKUP_NO_TEMP_BIND for
list-initialization. A conversion to rvalue ref that involves
an lvalue-rvalue conversion is bad.
(convert_like_real): Give helpful error message.
2014-01-29 Jason Merrill <jason@redhat.com>
PR c++/59956
* friend.c (do_friend): Pass the TEMPLATE_DECL to add_friend if we
have a friend template in a class template.
* pt.c (tsubst_friend_function): Look through it.
(push_template_decl_real): A friend member template is
primary.
2014-02-21 Jason Merrill <jason@redhat.com>
PR c++/60241
* pt.c (lookup_template_class_1): Update DECL_TEMPLATE_INSTANTIATIONS
of the partial instantiation, not the most general template.
(maybe_process_partial_specialization): Reassign everything on
that list.
2014-03-05 Jason Merrill <jason@redhat.com>
PR c++/60361
* parser.c (cp_parser_template_id): Don't set up a CPP_TEMPLATE_ID
if re-parsing might succeed.
* semantics.c (finish_id_expression): Use of a parameter outside
the function body is a parse error.
2014-06-30 Jason Merrill <jason@redhat.com>
PR c++/61647
* pt.c (type_dependent_expression_p): Check BASELINK_OPTYPE.
PR c++/61539
* pt.c (unify_one_argument): Type/expression mismatch just causes
deduction failure.
PR c++/61500
* tree.c (lvalue_kind): Handle MEMBER_REF and DOTSTAR_EXPR.
2014-06-17 Jason Merrill <jason@redhat.com>
PR c++/60605
* pt.c (check_default_tmpl_args): Check DECL_LOCAL_FUNCTION_P.
2014-06-02 Jason Merrill <jason@redhat.com>
PR c++/61134
* pt.c (pack_deducible_p): Handle canonicalization.
2014-05-22 Release Manager
* GCC 4.8.3 released.

24
external/gpl3/gcc/dist/gcc/cp/call.c vendored
View File

@ -1464,7 +1464,7 @@ reference_binding (tree rto, tree rfrom, tree expr, bool c_cast_p, int flags,
{
maybe_warn_cpp0x (CPP0X_INITIALIZER_LISTS);
conv = implicit_conversion (to, from, expr, c_cast_p,
flags, complain);
flags|LOOKUP_NO_TEMP_BIND, complain);
if (!CLASS_TYPE_P (to)
&& CONSTRUCTOR_NELTS (expr) == 1)
{
@ -1624,9 +1624,9 @@ reference_binding (tree rto, tree rfrom, tree expr, bool c_cast_p, int flags,
/* [dcl.init.ref]
Otherwise, the reference shall be to a non-volatile const type.
Under C++0x, [8.5.3/5 dcl.init.ref] it may also be an rvalue reference */
Otherwise, the reference shall be an lvalue reference to a
non-volatile const type, or the reference shall be an rvalue
reference. */
if (!CP_TYPE_CONST_NON_VOLATILE_P (to) && !TYPE_REF_IS_RVALUE (rto))
return NULL;
@ -1664,7 +1664,16 @@ reference_binding (tree rto, tree rfrom, tree expr, bool c_cast_p, int flags,
/* This reference binding, unlike those above, requires the
creation of a temporary. */
conv->need_temporary_p = true;
conv->rvaluedness_matches_p = TYPE_REF_IS_RVALUE (rto);
if (TYPE_REF_IS_RVALUE (rto))
{
conv->rvaluedness_matches_p = 1;
/* In the second case, if the reference is an rvalue reference and
the second standard conversion sequence of the user-defined
conversion sequence includes an lvalue-to-rvalue conversion, the
program is ill-formed. */
if (conv->user_conv_p && next_conversion (conv)->kind == ck_rvalue)
conv->bad_p = 1;
}
return conv;
}
@ -5811,7 +5820,7 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum,
&& convs->kind != ck_list
&& convs->kind != ck_ambig
&& (convs->kind != ck_ref_bind
|| convs->user_conv_p)
|| (convs->user_conv_p && next_conversion (convs)->bad_p))
&& (convs->kind != ck_rvalue
|| SCALAR_TYPE_P (totype))
&& convs->kind != ck_base)
@ -6110,7 +6119,8 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum,
if (convs->bad_p && !next_conversion (convs)->bad_p)
{
gcc_assert (TYPE_REF_IS_RVALUE (ref_type)
&& real_lvalue_p (expr));
&& (real_lvalue_p (expr)
|| next_conversion(convs)->kind == ck_rvalue));
error_at (loc, "cannot bind %qT lvalue to %qT",
TREE_TYPE (expr), totype);

8
external/gpl3/gcc/dist/gcc/cp/friend.c vendored
View File

@ -502,7 +502,13 @@ do_friend (tree ctype, tree declarator, tree decl,
? current_template_parms
: NULL_TREE);
if (template_member_p && decl && TREE_CODE (decl) == FUNCTION_DECL)
if ((template_member_p
/* Always pull out the TEMPLATE_DECL if we have a friend
template in a class template so that it gets tsubsted
properly later on (59956). tsubst_friend_function knows
how to tell this apart from a member template. */
|| (class_template_depth && friend_depth))
&& decl && TREE_CODE (decl) == FUNCTION_DECL)
decl = DECL_TI_TEMPLATE (decl);
if (decl)

7
external/gpl3/gcc/dist/gcc/cp/parser.c vendored
View File

@ -12831,7 +12831,12 @@ cp_parser_template_id (cp_parser *parser,
the effort required to do the parse, nor will we issue duplicate
error messages about problems during instantiation of the
template. */
if (start_of_id)
if (start_of_id
/* Don't do this if we had a parse error in a declarator; re-parsing
might succeed if a name changes meaning (60361). */
&& !(cp_parser_error_occurred (parser)
&& cp_parser_parsing_tentatively (parser)
&& parser->in_declarator_p))
{
cp_token *token = cp_lexer_token_at (parser->lexer, start_of_id);

47
external/gpl3/gcc/dist/gcc/cp/pt.c vendored
View File

@ -907,11 +907,13 @@ maybe_process_partial_specialization (tree type)
t; t = TREE_CHAIN (t))
{
tree inst = TREE_VALUE (t);
if (CLASSTYPE_TEMPLATE_SPECIALIZATION (inst))
if (CLASSTYPE_TEMPLATE_SPECIALIZATION (inst)
|| !COMPLETE_OR_OPEN_TYPE_P (inst))
{
/* We already have a full specialization of this partial
instantiation. Reassign it to the new member
specialization template. */
instantiation, or a full specialization has been
looked up but not instantiated. Reassign it to the
new member specialization template. */
spec_entry elt;
spec_entry *entry;
void **slot;
@ -930,7 +932,7 @@ maybe_process_partial_specialization (tree type)
*entry = elt;
*slot = entry;
}
else if (COMPLETE_OR_OPEN_TYPE_P (inst))
else
/* But if we've had an implicit instantiation, that's a
problem ([temp.expl.spec]/6). */
error ("specialization %qT after instantiation %qT",
@ -4308,7 +4310,8 @@ check_default_tmpl_args (tree decl, tree parms, bool is_primary,
in the template-parameter-list of the definition of a member of a
class template. */
if (TREE_CODE (CP_DECL_CONTEXT (decl)) == FUNCTION_DECL)
if (TREE_CODE (CP_DECL_CONTEXT (decl)) == FUNCTION_DECL
|| (TREE_CODE (decl) == FUNCTION_DECL && DECL_LOCAL_FUNCTION_P (decl)))
/* You can't have a function template declaration in a local
scope, nor you can you define a member of a class template in a
local scope. */
@ -4572,7 +4575,8 @@ push_template_decl_real (tree decl, bool is_friend)
DECL_CONTEXT (decl) = FROB_CONTEXT (current_namespace);
/* See if this is a primary template. */
if (is_friend && ctx)
if (is_friend && ctx
&& uses_template_parms_level (ctx, processing_template_decl))
/* A friend template that specifies a class context, i.e.
template <typename T> friend void A<T>::f();
is not primary. */
@ -7454,7 +7458,7 @@ lookup_template_class_1 (tree d1, tree arglist, tree in_decl, tree context,
}
/* Let's consider the explicit specialization of a member
of a class template specialization that is implicitely instantiated,
of a class template specialization that is implicitly instantiated,
e.g.:
template<class T>
struct S
@ -7552,9 +7556,9 @@ lookup_template_class_1 (tree d1, tree arglist, tree in_decl, tree context,
/* Note this use of the partial instantiation so we can check it
later in maybe_process_partial_specialization. */
DECL_TEMPLATE_INSTANTIATIONS (templ)
DECL_TEMPLATE_INSTANTIATIONS (found)
= tree_cons (arglist, t,
DECL_TEMPLATE_INSTANTIATIONS (templ));
DECL_TEMPLATE_INSTANTIATIONS (found));
if (TREE_CODE (template_type) == ENUMERAL_TYPE && !is_dependent_type)
/* Now that the type has been registered on the instantiations
@ -8289,10 +8293,17 @@ tsubst_friend_function (tree decl, tree args)
if (COMPLETE_TYPE_P (context))
{
tree fn = new_friend;
/* do_friend adds the TEMPLATE_DECL for any member friend
template even if it isn't a member template, i.e.
template <class T> friend A<T>::f();
Look through it in that case. */
if (TREE_CODE (fn) == TEMPLATE_DECL
&& !PRIMARY_TEMPLATE_P (fn))
fn = DECL_TEMPLATE_RESULT (fn);
/* Check to see that the declaration is really present, and,
possibly obtain an improved declaration. */
tree fn = check_classfn (context,
new_friend, NULL_TREE);
fn = check_classfn (context, fn, NULL_TREE);
if (fn)
new_friend = fn;
@ -14934,7 +14945,7 @@ pack_deducible_p (tree parm, tree fn)
continue;
for (packs = PACK_EXPANSION_PARAMETER_PACKS (type);
packs; packs = TREE_CHAIN (packs))
if (TREE_VALUE (packs) == parm)
if (template_args_equal (TREE_VALUE (packs), parm))
{
/* The template parameter pack is used in a function parameter
pack. If this is the end of the parameter list, the
@ -15502,8 +15513,9 @@ unify_one_argument (tree tparms, tree targs, tree parm, tree arg,
maybe_adjust_types_for_deduction (strict, &parm, &arg, arg_expr);
}
else
gcc_assert ((TYPE_P (parm) || TREE_CODE (parm) == TEMPLATE_DECL)
== (TYPE_P (arg) || TREE_CODE (arg) == TEMPLATE_DECL));
if ((TYPE_P (parm) || TREE_CODE (parm) == TEMPLATE_DECL)
!= (TYPE_P (arg) || TREE_CODE (arg) == TEMPLATE_DECL))
return unify_template_argument_mismatch (explain_p, parm, arg);
/* For deduction from an init-list we need the actual list. */
if (arg_expr && BRACE_ENCLOSED_INITIALIZER_P (arg_expr))
@ -20009,7 +20021,12 @@ type_dependent_expression_p (tree expression)
return true;
if (BASELINK_P (expression))
expression = BASELINK_FUNCTIONS (expression);
{
if (BASELINK_OPTYPE (expression)
&& dependent_type_p (BASELINK_OPTYPE (expression)))
return true;
expression = BASELINK_FUNCTIONS (expression);
}
if (TREE_CODE (expression) == TEMPLATE_ID_EXPR)
{

6
external/gpl3/gcc/dist/gcc/cp/semantics.c vendored
View File

@ -3108,7 +3108,7 @@ finish_id_expression (tree id_expression,
&& DECL_CONTEXT (decl) == NULL_TREE
&& !cp_unevaluated_operand)
{
error ("use of parameter %qD outside function body", decl);
*error_msg = "use of parameter outside function body";
return error_mark_node;
}
}
@ -7296,7 +7296,9 @@ cxx_eval_bare_aggregate (const constexpr_call *call, tree t,
constructor_elt *inner = base_field_constructor_elt (n, ce->index);
inner->value = elt;
}
else if (ce->index && TREE_CODE (ce->index) == NOP_EXPR)
else if (ce->index
&& (TREE_CODE (ce->index) == NOP_EXPR
|| TREE_CODE (ce->index) == POINTER_PLUS_EXPR))
{
/* This is an initializer for an empty base; now that we've
checked that it's constant, we can ignore it. */

14
external/gpl3/gcc/dist/gcc/cp/tree.c vendored
View File

@ -97,6 +97,16 @@ lvalue_kind (const_tree ref)
case IMAGPART_EXPR:
return lvalue_kind (TREE_OPERAND (ref, 0));
case MEMBER_REF:
case DOTSTAR_EXPR:
if (TREE_CODE (ref) == MEMBER_REF)
op1_lvalue_kind = clk_ordinary;
else
op1_lvalue_kind = lvalue_kind (TREE_OPERAND (ref, 0));
if (TYPE_PTRMEMFUNC_P (TREE_TYPE (TREE_OPERAND (ref, 1))))
op1_lvalue_kind = clk_none;
return op1_lvalue_kind;
case COMPONENT_REF:
op1_lvalue_kind = lvalue_kind (TREE_OPERAND (ref, 0));
/* Look at the member designator. */
@ -3738,6 +3748,10 @@ stabilize_expr (tree exp, tree* initp)
{
init_expr = get_target_expr (exp);
exp = TARGET_EXPR_SLOT (init_expr);
if (CLASS_TYPE_P (TREE_TYPE (exp)))
exp = move (exp);
else
exp = rvalue (exp);
}
else
{

10
external/gpl3/gcc/dist/gcc/doc/extend.texi vendored
View File

@ -375,6 +375,8 @@ goto *(&&foo + array[i]);
This is more friendly to code living in shared libraries, as it reduces
the number of dynamic relocations that are needed, and by consequence,
allows the data to be read-only.
This alternative with label differences is not supported for the AVR target,
please use the first approach for AVR programs.
The @code{&&foo} expressions for the same label might have different
values if the containing function is inlined or cloned. If a program
@ -10490,7 +10492,7 @@ used. All of them generate the machine instruction that is part of the
name.
@smallexample
v32qi __builtin_ia32_mpsadbw256 (v32qi,v32qi,v32qi,int)
v32qi __builtin_ia32_mpsadbw256 (v32qi,v32qi,int)
v32qi __builtin_ia32_pabsb256 (v32qi)
v16hi __builtin_ia32_pabsw256 (v16hi)
v8si __builtin_ia32_pabsd256 (v8si)
@ -10725,8 +10727,8 @@ The following built-in functions are available when @option{-mxop} is used.
@smallexample
v2df __builtin_ia32_vfrczpd (v2df)
v4sf __builtin_ia32_vfrczps (v4sf)
v2df __builtin_ia32_vfrczsd (v2df, v2df)
v4sf __builtin_ia32_vfrczss (v4sf, v4sf)
v2df __builtin_ia32_vfrczsd (v2df)
v4sf __builtin_ia32_vfrczss (v4sf)
v4df __builtin_ia32_vfrczpd256 (v4df)
v8sf __builtin_ia32_vfrczps256 (v8sf)
v2di __builtin_ia32_vpcmov (v2di, v2di, v2di)
@ -11855,8 +11857,6 @@ double __builtin_rsqrt (double);
uint64_t __builtin_ppc_get_timebase ();
unsigned long __builtin_ppc_mftb ();
double __builtin_unpack_longdouble (long double, int);
double __builtin_longdouble_dw0 (long double);
double __builtin_longdouble_dw1 (long double);
long double __builtin_pack_longdouble (double, double);
@end smallexample

6
external/gpl3/gcc/dist/gcc/doc/install.texi vendored
View File

@ -2914,12 +2914,6 @@ OpenServer/Unixware}.
@item
Solaris 2 (SPARC, Intel):
@itemize
@item
@uref{http://www.sunfreeware.com/,,Sunfreeware}
@item
@uref{http://www.blastwave.org/,,Blastwave}
@item
@uref{http://www.opencsw.org/,,OpenCSW}

14
external/gpl3/gcc/dist/gcc/doc/md.texi vendored
View File

@ -2081,6 +2081,18 @@ VSX vector register to hold vector float data or NO_REGS.
@item wg
If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
@item wh
Floating point register if direct moves are available, or NO_REGS.
@item wi
FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
@item wj
FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
@item wk
FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
@item wl
Floating point register if the LFIWAX instruction is enabled or NO_REGS.
@ -2112,7 +2124,7 @@ FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
Floating point register if the STFIWX instruction is enabled or NO_REGS.
@item wy
VSX vector register to hold scalar float values or NO_REGS.
FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
@item wz
Floating point register if the LFIWZX instruction is enabled or NO_REGS.

3
external/gpl3/gcc/dist/gcc/doc/sourcebuild.texi vendored
View File

@ -1299,6 +1299,9 @@ Target has 64-bit @code{double}.
@item double64plus
Target has @code{double} that is 64 bits or longer.
@item longdouble128
Target has 128-bit @code{long double}.
@item int32plus
Target has @code{int} that is at 32 bits or longer.

7
external/gpl3/gcc/dist/gcc/doc/tm.texi vendored
View File

@ -3930,6 +3930,13 @@ which.
@c above is overfull. not sure what to do. --mew 5feb93 did
@c something, not sure if it looks good. --mew 10feb93
@defmac INCOMING_REG_PARM_STACK_SPACE (@var{fndecl})
Like @code{REG_PARM_STACK_SPACE}, but for incoming register arguments.
Define this macro if space guaranteed when compiling a function body
is different to space required when making a call, a situation that
can arise with K&R style function definitions.
@end defmac
@defmac OUTGOING_REG_PARM_STACK_SPACE (@var{fntype})
Define this to a nonzero value if it is the responsibility of the
caller to allocate the area reserved for arguments passed in registers

7
external/gpl3/gcc/dist/gcc/doc/tm.texi.in vendored
View File

@ -3898,6 +3898,13 @@ which.
@c above is overfull. not sure what to do. --mew 5feb93 did
@c something, not sure if it looks good. --mew 10feb93
@defmac INCOMING_REG_PARM_STACK_SPACE (@var{fndecl})
Like @code{REG_PARM_STACK_SPACE}, but for incoming register arguments.
Define this macro if space guaranteed when compiling a function body
is different to space required when making a call, a situation that
can arise with K&R style function definitions.
@end defmac
@defmac OUTGOING_REG_PARM_STACK_SPACE (@var{fntype})
Define this to a nonzero value if it is the responsibility of the
caller to allocate the area reserved for arguments passed in registers

2
external/gpl3/gcc/dist/gcc/double-int.c vendored
View File

@ -616,7 +616,7 @@ div_and_round_double (unsigned code, int uns,
== (unsigned HOST_WIDE_INT) htwice)
&& (labs_den <= ltwice)))
{
if (*hquo < 0)
if (quo_neg)
/* quo = quo - 1; */
add_double (*lquo, *hquo,
(HOST_WIDE_INT) -1, (HOST_WIDE_INT) -1, lquo, hquo);

2
external/gpl3/gcc/dist/gcc/emit-rtl.c vendored
View File

@ -263,7 +263,7 @@ mem_attrs_htab_hash (const void *x)
/* Return true if the given memory attributes are equal. */
static bool
bool
mem_attrs_eq_p (const struct mem_attrs *p, const struct mem_attrs *q)
{
return (p->alias == q->alias

3
external/gpl3/gcc/dist/gcc/emit-rtl.h vendored
View File

@ -20,6 +20,9 @@ along with GCC; see the file COPYING3. If not see
#ifndef GCC_EMIT_RTL_H
#define GCC_EMIT_RTL_H
/* Return whether two MEM_ATTRs are equal. */
bool mem_attrs_eq_p (const struct mem_attrs *, const struct mem_attrs *);
/* Set the alias set of MEM to SET. */
extern void set_mem_alias_set (rtx, alias_set_type);

58
external/gpl3/gcc/dist/gcc/fold-const.c vendored
View File

@ -9213,7 +9213,7 @@ fold_comparison (location_t loc, enum tree_code code, tree type,
/* Transform comparisons of the form X +- C1 CMP Y +- C2 to
X CMP Y +- C2 +- C1 for signed X, Y. This is valid if
the resulting offset is smaller in absolute value than the
original one. */
original one and has the same sign. */
if (TYPE_OVERFLOW_UNDEFINED (TREE_TYPE (arg0))
&& (TREE_CODE (arg0) == PLUS_EXPR || TREE_CODE (arg0) == MINUS_EXPR)
&& (TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST
@ -9232,32 +9232,35 @@ fold_comparison (location_t loc, enum tree_code code, tree type,
"a comparison");
/* Put the constant on the side where it doesn't overflow and is
of lower absolute value than before. */
of lower absolute value and of same sign than before. */
cst = int_const_binop (TREE_CODE (arg0) == TREE_CODE (arg1)
? MINUS_EXPR : PLUS_EXPR,
const2, const1);
if (!TREE_OVERFLOW (cst)
&& tree_int_cst_compare (const2, cst) == tree_int_cst_sgn (const2))
&& tree_int_cst_compare (const2, cst) == tree_int_cst_sgn (const2)
&& tree_int_cst_sgn (cst) == tree_int_cst_sgn (const2))
{
fold_overflow_warning (warnmsg, WARN_STRICT_OVERFLOW_COMPARISON);
return fold_build2_loc (loc, code, type,
variable1,
fold_build2_loc (loc,
TREE_CODE (arg1), TREE_TYPE (arg1),
variable2, cst));
variable1,
fold_build2_loc (loc, TREE_CODE (arg1),
TREE_TYPE (arg1),
variable2, cst));
}
cst = int_const_binop (TREE_CODE (arg0) == TREE_CODE (arg1)
? MINUS_EXPR : PLUS_EXPR,
const1, const2);
if (!TREE_OVERFLOW (cst)
&& tree_int_cst_compare (const1, cst) == tree_int_cst_sgn (const1))
&& tree_int_cst_compare (const1, cst) == tree_int_cst_sgn (const1)
&& tree_int_cst_sgn (cst) == tree_int_cst_sgn (const1))
{
fold_overflow_warning (warnmsg, WARN_STRICT_OVERFLOW_COMPARISON);
return fold_build2_loc (loc, code, type,
fold_build2_loc (loc, TREE_CODE (arg0), TREE_TYPE (arg0),
variable1, cst),
variable2);
fold_build2_loc (loc, TREE_CODE (arg0),
TREE_TYPE (arg0),
variable1, cst),
variable2);
}
}
@ -11218,7 +11221,6 @@ fold_binary_loc (location_t loc,
{
double_int c1, c2, c3, msk;
int width = TYPE_PRECISION (type), w;
bool try_simplify = true;
c1 = tree_to_double_int (TREE_OPERAND (arg0, 1));
c2 = tree_to_double_int (arg1);
@ -11255,20 +11257,7 @@ fold_binary_loc (location_t loc,
}
}
/* If X is a tree of the form (Y * K1) & K2, this might conflict
with that optimization from the BIT_AND_EXPR optimizations.
This could end up in an infinite recursion. */
if (TREE_CODE (TREE_OPERAND (arg0, 0)) == MULT_EXPR
&& TREE_CODE (TREE_OPERAND (TREE_OPERAND (arg0, 0), 1))
== INTEGER_CST)
{
tree t = TREE_OPERAND (TREE_OPERAND (arg0, 0), 1);
double_int masked = mask_with_tz (type, c3, tree_to_double_int (t));
try_simplify = (masked != c1);
}
if (try_simplify && c3 != c1)
if (c3 != c1)
return fold_build2_loc (loc, BIT_IOR_EXPR, type,
fold_build2_loc (loc, BIT_AND_EXPR, type,
TREE_OPERAND (arg0, 0),
@ -11658,16 +11647,25 @@ fold_binary_loc (location_t loc,
&& TREE_CODE (arg0) == MULT_EXPR
&& TREE_CODE (TREE_OPERAND (arg0, 1)) == INTEGER_CST)
{
double_int darg1 = tree_to_double_int (arg1);
double_int masked
= mask_with_tz (type, tree_to_double_int (arg1),
= mask_with_tz (type, darg1,
tree_to_double_int (TREE_OPERAND (arg0, 1)));
if (masked.is_zero ())
return omit_two_operands_loc (loc, type, build_zero_cst (type),
arg0, arg1);
else if (masked != tree_to_double_int (arg1))
return fold_build2_loc (loc, code, type, op0,
double_int_to_tree (type, masked));
else if (masked != darg1)
{
/* Avoid the transform if arg1 is a mask of some
mode which allows further optimizations. */
int pop = darg1.popcount ();
if (!(pop >= BITS_PER_UNIT
&& exact_log2 (pop) != -1
&& double_int::mask (pop) == darg1))
return fold_build2_loc (loc, code, type, op0,
double_int_to_tree (type, masked));
}
}
/* For constants M and N, if M == (1LL << cst) - 1 && (N & M) == M,

16
external/gpl3/gcc/dist/gcc/function.c vendored
View File

@ -1354,9 +1354,13 @@ static int cfa_offset;
#define STACK_POINTER_OFFSET 0
#endif
#if defined (REG_PARM_STACK_SPACE) && !defined (INCOMING_REG_PARM_STACK_SPACE)
#define INCOMING_REG_PARM_STACK_SPACE REG_PARM_STACK_SPACE
#endif
/* If not defined, pick an appropriate default for the offset of dynamically
allocated memory depending on the value of ACCUMULATE_OUTGOING_ARGS,
REG_PARM_STACK_SPACE, and OUTGOING_REG_PARM_STACK_SPACE. */
INCOMING_REG_PARM_STACK_SPACE, and OUTGOING_REG_PARM_STACK_SPACE. */
#ifndef STACK_DYNAMIC_OFFSET
@ -1368,12 +1372,12 @@ static int cfa_offset;
`crtl->outgoing_args_size'. Nevertheless, we must allow
for it when allocating stack dynamic objects. */
#if defined(REG_PARM_STACK_SPACE)
#ifdef INCOMING_REG_PARM_STACK_SPACE
#define STACK_DYNAMIC_OFFSET(FNDECL) \
((ACCUMULATE_OUTGOING_ARGS \
? (crtl->outgoing_args_size \
+ (OUTGOING_REG_PARM_STACK_SPACE ((!(FNDECL) ? NULL_TREE : TREE_TYPE (FNDECL))) ? 0 \
: REG_PARM_STACK_SPACE (FNDECL))) \
: INCOMING_REG_PARM_STACK_SPACE (FNDECL))) \
: 0) + (STACK_POINTER_OFFSET))
#else
#define STACK_DYNAMIC_OFFSET(FNDECL) \
@ -2211,8 +2215,9 @@ assign_parms_initialize_all (struct assign_parm_data_all *all)
#endif
all->args_so_far = pack_cumulative_args (&all->args_so_far_v);
#ifdef REG_PARM_STACK_SPACE
all->reg_parm_stack_space = REG_PARM_STACK_SPACE (current_function_decl);
#ifdef INCOMING_REG_PARM_STACK_SPACE
all->reg_parm_stack_space
= INCOMING_REG_PARM_STACK_SPACE (current_function_decl);
#endif
}
@ -4518,6 +4523,7 @@ allocate_struct_function (tree fndecl, bool abstract_p)
/* ??? This could be set on a per-function basis by the front-end
but is this worth the hassle? */
cfun->can_throw_non_call_exceptions = flag_non_call_exceptions;
cfun->can_delete_dead_exceptions = flag_delete_dead_exceptions;
}
}

4
external/gpl3/gcc/dist/gcc/gimple-fold.c vendored
View File

@ -2955,8 +2955,8 @@ fold_ctor_reference (tree type, tree ctor, unsigned HOST_WIDE_INT offset,
result. */
if (!AGGREGATE_TYPE_P (TREE_TYPE (ctor)) && !offset
/* VIEW_CONVERT_EXPR is defined only for matching sizes. */
&& operand_equal_p (TYPE_SIZE (type),
TYPE_SIZE (TREE_TYPE (ctor)), 0))
&& !compare_tree_int (TYPE_SIZE (type), size)
&& !compare_tree_int (TYPE_SIZE (TREE_TYPE (ctor)), size))
{
ret = canonicalize_constructor_val (unshare_expr (ctor), from_decl);
ret = fold_unary (VIEW_CONVERT_EXPR, type, ret);

8
external/gpl3/gcc/dist/gcc/haifa-sched.c vendored
View File

@ -2931,7 +2931,7 @@ advance_one_cycle (void)
{
advance_state (curr_state);
if (sched_verbose >= 6)
fprintf (sched_dump, ";;\tAdvanced a state.\n");
fprintf (sched_dump, ";;\tAdvance the current state.\n");
}
/* Update register pressure after scheduling INSN. */
@ -5964,6 +5964,7 @@ schedule_block (basic_block *target_bb, state_t init_state)
modulo_insns_scheduled = 0;
ls.modulo_epilogue = false;
ls.first_cycle_insn_p = true;
/* Loop until all the insns in BB are scheduled. */
while ((*current_sched_info->schedule_more_p) ())
@ -6034,7 +6035,6 @@ schedule_block (basic_block *target_bb, state_t init_state)
if (must_backtrack)
goto do_backtrack;
ls.first_cycle_insn_p = true;
ls.shadows_only_p = false;
cycle_issued_insns = 0;
ls.can_issue_more = issue_rate;
@ -6321,11 +6321,13 @@ schedule_block (basic_block *target_bb, state_t init_state)
break;
}
}
ls.first_cycle_insn_p = true;
}
if (ls.modulo_epilogue)
success = true;
end_schedule:
advance_one_cycle ();
if (!ls.first_cycle_insn_p)
advance_one_cycle ();
perform_replacements_new_cycle ();
if (modulo_ii > 0)
{

34
external/gpl3/gcc/dist/gcc/ifcvt.c vendored
View File

@ -294,6 +294,28 @@ block_fallthru (basic_block bb)
return (e) ? e->dest : NULL_BLOCK;
}
/* Return true if RTXs A and B can be safely interchanged. */
static bool
rtx_interchangeable_p (const_rtx a, const_rtx b)
{
if (!rtx_equal_p (a, b))
return false;
if (GET_CODE (a) != MEM)
return true;
/* A dead type-unsafe memory reference is legal, but a live type-unsafe memory
reference is not. Interchanging a dead type-unsafe memory reference with
a live type-safe one creates a live type-unsafe memory reference, in other
words, it makes the program illegal.
We check here conservatively whether the two memory references have equal
memory attributes. */
return mem_attrs_eq_p (get_mem_attrs (a), get_mem_attrs (b));
}
/* Go through a bunch of insns, converting them to conditional
execution format if possible. Return TRUE if all of the non-note
@ -1014,6 +1036,9 @@ noce_try_move (struct noce_if_info *if_info)
|| (rtx_equal_p (if_info->a, XEXP (cond, 1))
&& rtx_equal_p (if_info->b, XEXP (cond, 0))))
{
if (!rtx_interchangeable_p (if_info->a, if_info->b))
return FALSE;
y = (code == EQ) ? if_info->a : if_info->b;
/* Avoid generating the move if the source is the destination. */
@ -2483,7 +2508,7 @@ noce_process_if_block (struct noce_if_info *if_info)
if (! insn_b
|| insn_b != last_active_insn (else_bb, FALSE)
|| (set_b = single_set (insn_b)) == NULL_RTX
|| ! rtx_equal_p (x, SET_DEST (set_b)))
|| ! rtx_interchangeable_p (x, SET_DEST (set_b)))
return FALSE;
}
else
@ -2496,7 +2521,7 @@ noce_process_if_block (struct noce_if_info *if_info)
|| BLOCK_FOR_INSN (insn_b) != BLOCK_FOR_INSN (if_info->cond_earliest)
|| !NONJUMP_INSN_P (insn_b)
|| (set_b = single_set (insn_b)) == NULL_RTX
|| ! rtx_equal_p (x, SET_DEST (set_b))
|| ! rtx_interchangeable_p (x, SET_DEST (set_b))
|| ! noce_operand_ok (SET_SRC (set_b))
|| reg_overlap_mentioned_p (x, SET_SRC (set_b))
|| modified_between_p (SET_SRC (set_b), insn_b, jump)
@ -2562,7 +2587,7 @@ noce_process_if_block (struct noce_if_info *if_info)
/* Look and see if A and B are really the same. Avoid creating silly
cmove constructs that no one will fix up later. */
if (rtx_equal_p (a, b))
if (rtx_interchangeable_p (a, b))
{
/* If we have an INSN_B, we don't have to create any new rtl. Just
move the instruction that we already have. If we don't have an
@ -4246,6 +4271,9 @@ dead_or_predicable (basic_block test_bb, basic_block merge_bb,
old_dest = JUMP_LABEL (jump);
if (other_bb != new_dest)
{
if (!any_condjump_p (jump))
goto cancel;
if (JUMP_P (BB_END (dest_edge->src)))
new_dest_label = JUMP_LABEL (BB_END (dest_edge->src));
else if (new_dest == EXIT_BLOCK_PTR)

28
external/gpl3/gcc/dist/gcc/ipa-cp.c vendored
View File

@ -447,6 +447,8 @@ determine_versionability (struct cgraph_node *node)
else if (!opt_for_fn (node->symbol.decl, optimize)
|| !opt_for_fn (node->symbol.decl, flag_ipa_cp))
reason = "non-optimized function";
else if (node->tm_clone)
reason = "transactional memory clone";
if (reason && dump_file && !node->alias && !node->thunk.thunk_p)
fprintf (dump_file, "Function %s/%i is not versionable, reason: %s.\n",
@ -2902,6 +2904,11 @@ intersect_aggregates_with_edge (struct cgraph_edge *cs, int index,
intersect_with_agg_replacements (cs->caller, src_idx,
&inter, 0);
}
else
{
inter.release ();
return vNULL;
}
}
else
{
@ -2917,6 +2924,11 @@ intersect_aggregates_with_edge (struct cgraph_edge *cs, int index,
else
intersect_with_plats (src_plats, &inter, 0);
}
else
{
inter.release ();
return vNULL;
}
}
}
else if (jfunc->type == IPA_JF_ANCESTOR
@ -3000,7 +3012,8 @@ find_aggregate_values_for_callers_subset (struct cgraph_node *node,
vec<cgraph_edge_p> callers)
{
struct ipa_node_params *dest_info = IPA_NODE_REF (node);
struct ipa_agg_replacement_value *res = NULL;
struct ipa_agg_replacement_value *res;
struct ipa_agg_replacement_value **tail = &res;
struct cgraph_edge *cs;
int i, j, count = ipa_get_param_count (dest_info);
@ -3044,14 +3057,15 @@ find_aggregate_values_for_callers_subset (struct cgraph_node *node,
v->offset = item->offset;
v->value = item->value;
v->by_ref = plats->aggs_by_ref;
v->next = res;
res = v;
*tail = v;
tail = &v->next;
}
next_param:
if (inter.exists ())
inter.release ();
}
*tail = NULL;
return res;
}
@ -3060,7 +3074,8 @@ find_aggregate_values_for_callers_subset (struct cgraph_node *node,
static struct ipa_agg_replacement_value *
known_aggs_to_agg_replacement_list (vec<ipa_agg_jump_function_t> known_aggs)
{
struct ipa_agg_replacement_value *res = NULL;
struct ipa_agg_replacement_value *res;
struct ipa_agg_replacement_value **tail = &res;
struct ipa_agg_jump_function *aggjf;
struct ipa_agg_jf_item *item;
int i, j;
@ -3074,9 +3089,10 @@ known_aggs_to_agg_replacement_list (vec<ipa_agg_jump_function_t> known_aggs)
v->offset = item->offset;
v->value = item->value;
v->by_ref = aggjf->by_ref;
v->next = res;
res = v;
*tail = v;
tail = &v->next;
}
*tail = NULL;
return res;
}

1
external/gpl3/gcc/dist/gcc/omp-low.c vendored
View File

@ -1586,7 +1586,6 @@ create_omp_child_function (omp_context *ctx, bool task_copy)
TREE_STATIC (decl) = 1;
TREE_USED (decl) = 1;
DECL_ARTIFICIAL (decl) = 1;
DECL_NAMELESS (decl) = 1;
DECL_IGNORED_P (decl) = 0;
TREE_PUBLIC (decl) = 0;
DECL_UNINLINABLE (decl) = 1;

12
external/gpl3/gcc/dist/gcc/regcprop.c vendored
View File

@ -1039,7 +1039,17 @@ copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd)
but instead among CLOBBERs on the CALL_INSN, we could wrongly
assume the value in it is still live. */
if (ksvd.ignore_set_reg)
note_stores (PATTERN (insn), kill_clobbered_value, vd);
{
note_stores (PATTERN (insn), kill_clobbered_value, vd);
for (exp = CALL_INSN_FUNCTION_USAGE (insn);
exp;
exp = XEXP (exp, 1))
{
rtx x = XEXP (exp, 0);
if (GET_CODE (x) == CLOBBER)
kill_value (SET_DEST (x), vd);
}
}
}
/* Notice stores. */

3
external/gpl3/gcc/dist/gcc/sched-deps.c vendored
View File

@ -2744,7 +2744,8 @@ sched_analyze_2 (struct deps_desc *deps, rtx x, rtx insn)
Consider for instance a volatile asm that changes the fpu rounding
mode. An insn should not be moved across this even if it only uses
pseudo-regs because it might give an incorrectly rounded result. */
if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
if ((code != ASM_OPERANDS || MEM_VOLATILE_P (x))
&& !DEBUG_INSN_P (insn))
reg_pending_barrier = TRUE_BARRIER;
/* For all ASM_OPERANDS, we must traverse the vector of input operands.

56
external/gpl3/gcc/dist/gcc/sel-sched-ir.c vendored
View File

@ -162,7 +162,7 @@ static void create_initial_data_sets (basic_block);
static void free_av_set (basic_block);
static void invalidate_av_set (basic_block);
static void extend_insn_data (void);
static void sel_init_new_insn (insn_t, int);
static void sel_init_new_insn (insn_t, int, int = -1);
static void finish_insns (void);
/* Various list functions. */
@ -4011,9 +4011,10 @@ get_seqno_by_succs (rtx insn)
return seqno;
}
/* Compute seqno for INSN by its preds or succs. */
/* Compute seqno for INSN by its preds or succs. Use OLD_SEQNO to compute
seqno in corner cases. */
static int
get_seqno_for_a_jump (insn_t insn)
get_seqno_for_a_jump (insn_t insn, int old_seqno)
{
int seqno;
@ -4069,8 +4070,16 @@ get_seqno_for_a_jump (insn_t insn)
if (seqno < 0)
seqno = get_seqno_by_succs (insn);
gcc_assert (seqno >= 0);
if (seqno < 0)
{
/* The only case where this could be here legally is that the only
unscheduled insn was a conditional jump that got removed and turned
into this unconditional one. Initialize from the old seqno
of that jump passed down to here. */
seqno = old_seqno;
}
gcc_assert (seqno >= 0);
return seqno;
}
@ -4250,22 +4259,24 @@ init_insn_data (insn_t insn)
}
/* This is used to initialize spurious jumps generated by
sel_redirect_edge (). */
sel_redirect_edge (). OLD_SEQNO is used for initializing seqnos
in corner cases within get_seqno_for_a_jump. */
static void
init_simplejump_data (insn_t insn)
init_simplejump_data (insn_t insn, int old_seqno)
{
init_expr (INSN_EXPR (insn), vinsn_create (insn, false), 0,
REG_BR_PROB_BASE, 0, 0, 0, 0, 0, 0,
vNULL, true, false, false,
false, true);
INSN_SEQNO (insn) = get_seqno_for_a_jump (insn);
INSN_SEQNO (insn) = get_seqno_for_a_jump (insn, old_seqno);
init_first_time_insn_data (insn);
}
/* Perform deferred initialization of insns. This is used to process
a new jump that may be created by redirect_edge. */
void
sel_init_new_insn (insn_t insn, int flags)
a new jump that may be created by redirect_edge. OLD_SEQNO is used
for initializing simplejumps in init_simplejump_data. */
static void
sel_init_new_insn (insn_t insn, int flags, int old_seqno)
{
/* We create data structures for bb when the first insn is emitted in it. */
if (INSN_P (insn)
@ -4292,7 +4303,7 @@ sel_init_new_insn (insn_t insn, int flags)
if (flags & INSN_INIT_TODO_SIMPLEJUMP)
{
extend_insn_data ();
init_simplejump_data (insn);
init_simplejump_data (insn, old_seqno);
}
gcc_assert (CONTAINING_RGN (BLOCK_NUM (insn))
@ -5578,14 +5589,14 @@ sel_merge_blocks (basic_block a, basic_block b)
}
/* A wrapper for redirect_edge_and_branch_force, which also initializes
data structures for possibly created bb and insns. Returns the newly
added bb or NULL, when a bb was not needed. */
data structures for possibly created bb and insns. */
void
sel_redirect_edge_and_branch_force (edge e, basic_block to)
{
basic_block jump_bb, src, orig_dest = e->dest;
int prev_max_uid;
rtx jump;
int old_seqno = -1;
/* This function is now used only for bookkeeping code creation, where
we'll never get the single pred of orig_dest block and thus will not
@ -5594,8 +5605,13 @@ sel_redirect_edge_and_branch_force (edge e, basic_block to)
&& !single_pred_p (orig_dest));
src = e->src;
prev_max_uid = get_max_uid ();
jump_bb = redirect_edge_and_branch_force (e, to);
/* Compute and pass old_seqno down to sel_init_new_insn only for the case
when the conditional jump being redirected may become unconditional. */
if (any_condjump_p (BB_END (src))
&& INSN_SEQNO (BB_END (src)) >= 0)
old_seqno = INSN_SEQNO (BB_END (src));
jump_bb = redirect_edge_and_branch_force (e, to);
if (jump_bb != NULL)
sel_add_bb (jump_bb);
@ -5607,7 +5623,8 @@ sel_redirect_edge_and_branch_force (edge e, basic_block to)
jump = find_new_jump (src, jump_bb, prev_max_uid);
if (jump)
sel_init_new_insn (jump, INSN_INIT_TODO_LUID | INSN_INIT_TODO_SIMPLEJUMP);
sel_init_new_insn (jump, INSN_INIT_TODO_LUID | INSN_INIT_TODO_SIMPLEJUMP,
old_seqno);
set_immediate_dominator (CDI_DOMINATORS, to,
recompute_dominator (CDI_DOMINATORS, to));
set_immediate_dominator (CDI_DOMINATORS, orig_dest,
@ -5626,6 +5643,7 @@ sel_redirect_edge_and_branch (edge e, basic_block to)
edge redirected;
bool recompute_toporder_p = false;
bool maybe_unreachable = single_pred_p (orig_dest);
int old_seqno = -1;
latch_edge_p = (pipelining_p
&& current_loop_nest
@ -5634,6 +5652,12 @@ sel_redirect_edge_and_branch (edge e, basic_block to)
src = e->src;
prev_max_uid = get_max_uid ();
/* Compute and pass old_seqno down to sel_init_new_insn only for the case
when the conditional jump being redirected may become unconditional. */
if (any_condjump_p (BB_END (src))
&& INSN_SEQNO (BB_END (src)) >= 0)
old_seqno = INSN_SEQNO (BB_END (src));
redirected = redirect_edge_and_branch (e, to);
gcc_assert (redirected && !last_added_blocks.exists ());
@ -5654,7 +5678,7 @@ sel_redirect_edge_and_branch (edge e, basic_block to)
jump = find_new_jump (src, NULL, prev_max_uid);
if (jump)
sel_init_new_insn (jump, INSN_INIT_TODO_LUID | INSN_INIT_TODO_SIMPLEJUMP);
sel_init_new_insn (jump, INSN_INIT_TODO_LUID | INSN_INIT_TODO_SIMPLEJUMP, old_seqno);
/* Only update dominator info when we don't have unreachable blocks.
Otherwise we'll update in maybe_tidy_empty_bb. */

13
external/gpl3/gcc/dist/gcc/toplev.c vendored
View File

@ -1036,16 +1036,19 @@ output_stack_usage (void)
if (warn_stack_usage >= 0)
{
const location_t loc = DECL_SOURCE_LOCATION (current_function_decl);
if (stack_usage_kind == DYNAMIC)
warning (OPT_Wstack_usage_, "stack usage might be unbounded");
warning_at (loc, OPT_Wstack_usage_, "stack usage might be unbounded");
else if (stack_usage > warn_stack_usage)
{
if (stack_usage_kind == DYNAMIC_BOUNDED)
warning (OPT_Wstack_usage_, "stack usage might be %wd bytes",
stack_usage);
warning_at (loc,
OPT_Wstack_usage_, "stack usage might be %wd bytes",
stack_usage);
else
warning (OPT_Wstack_usage_, "stack usage is %wd bytes",
stack_usage);
warning_at (loc, OPT_Wstack_usage_, "stack usage is %wd bytes",
stack_usage);
}
}
}

15
external/gpl3/gcc/dist/gcc/tree-cfgcleanup.c vendored
View File

@ -498,7 +498,20 @@ fixup_noreturn_call (gimple stmt)
/* First split basic block if stmt is not last. */
if (stmt != gsi_stmt (gsi_last_bb (bb)))
split_block (bb, stmt);
{
if (stmt == gsi_stmt (gsi_last_nondebug_bb (bb)))
{
/* Don't split if there are only debug stmts
after stmt, that can result in -fcompare-debug
failures. Remove the debug stmts instead,
they should be all unreachable anyway. */
gimple_stmt_iterator gsi = gsi_for_stmt (stmt);
for (gsi_next (&gsi); !gsi_end_p (gsi); )
gsi_remove (&gsi, true);
}
else
split_block (bb, stmt);
}
changed |= remove_fallthru_edge (bb->succs);

5
external/gpl3/gcc/dist/gcc/tree-sra.c vendored
View File

@ -1030,6 +1030,11 @@ build_access_from_expr_1 (tree expr, gimple stmt, bool write)
"component.");
return NULL;
}
if (TREE_THIS_VOLATILE (expr))
{
disqualify_base_of_expr (expr, "part of a volatile reference.");
return NULL;
}
switch (TREE_CODE (expr))
{

7
external/gpl3/gcc/dist/gcc/tree-ssa-ifcombine.c vendored
View File

@ -105,7 +105,11 @@ bb_no_side_effects_p (basic_block bb)
{
gimple stmt = gsi_stmt (gsi);
if (is_gimple_debug (stmt))
continue;
if (gimple_has_side_effects (stmt)
|| gimple_could_trap_p (stmt)
|| gimple_vuse (stmt))
return false;
}
@ -197,7 +201,8 @@ recognize_single_bit_test (gimple cond, tree *name, tree *bit, bool inv)
while (is_gimple_assign (stmt)
&& ((CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (stmt))
&& (TYPE_PRECISION (TREE_TYPE (gimple_assign_lhs (stmt)))
<= TYPE_PRECISION (TREE_TYPE (gimple_assign_rhs1 (stmt)))))
<= TYPE_PRECISION (TREE_TYPE (gimple_assign_rhs1 (stmt))))
&& TREE_CODE (gimple_assign_rhs1 (stmt)) == SSA_NAME)
|| gimple_assign_ssa_name_copy_p (stmt)))
stmt = SSA_NAME_DEF_STMT (gimple_assign_rhs1 (stmt));

79
external/gpl3/gcc/dist/gcc/tree-ssa-math-opts.c vendored
View File

@ -1537,7 +1537,7 @@ struct gimple_opt_pass pass_cse_sincos =
struct symbolic_number {
unsigned HOST_WIDEST_INT n;
int size;
tree type;
};
/* Perform a SHIFT or ROTATE operation by COUNT bits on symbolic
@ -1549,13 +1549,15 @@ do_shift_rotate (enum tree_code code,
struct symbolic_number *n,
int count)
{
int bitsize = TYPE_PRECISION (n->type);
if (count % 8 != 0)
return false;
/* Zero out the extra bits of N in order to avoid them being shifted
into the significant bits. */
if (n->size < (int)sizeof (HOST_WIDEST_INT))
n->n &= ((unsigned HOST_WIDEST_INT)1 << (n->size * BITS_PER_UNIT)) - 1;
if (bitsize < 8 * (int)sizeof (HOST_WIDEST_INT))
n->n &= ((unsigned HOST_WIDEST_INT)1 << bitsize) - 1;
switch (code)
{
@ -1563,20 +1565,24 @@ do_shift_rotate (enum tree_code code,
n->n <<= count;
break;
case RSHIFT_EXPR:
/* Arithmetic shift of signed type: result is dependent on the value. */
if (!TYPE_UNSIGNED (n->type)
&& (n->n & ((unsigned HOST_WIDEST_INT) 0xff << (bitsize - 8))))
return false;
n->n >>= count;
break;
case LROTATE_EXPR:
n->n = (n->n << count) | (n->n >> ((n->size * BITS_PER_UNIT) - count));
n->n = (n->n << count) | (n->n >> (bitsize - count));
break;
case RROTATE_EXPR:
n->n = (n->n >> count) | (n->n << ((n->size * BITS_PER_UNIT) - count));
n->n = (n->n >> count) | (n->n << (bitsize - count));
break;
default:
return false;
}
/* Zero unused bits for size. */
if (n->size < (int)sizeof (HOST_WIDEST_INT))
n->n &= ((unsigned HOST_WIDEST_INT)1 << (n->size * BITS_PER_UNIT)) - 1;
if (bitsize < 8 * (int)sizeof (HOST_WIDEST_INT))
n->n &= ((unsigned HOST_WIDEST_INT)1 << bitsize) - 1;
return true;
}
@ -1593,7 +1599,7 @@ verify_symbolic_number_p (struct symbolic_number *n, gimple stmt)
if (TREE_CODE (lhs_type) != INTEGER_TYPE)
return false;
if (TYPE_PRECISION (lhs_type) != n->size * BITS_PER_UNIT)
if (TYPE_PRECISION (lhs_type) != TYPE_PRECISION (n->type))
return false;
return true;
@ -1650,20 +1656,25 @@ find_bswap_1 (gimple stmt, struct symbolic_number *n, int limit)
to initialize the symbolic number. */
if (!source_expr1)
{
int size;
/* Set up the symbolic number N by setting each byte to a
value between 1 and the byte size of rhs1. The highest
order byte is set to n->size and the lowest order
byte to 1. */
n->size = TYPE_PRECISION (TREE_TYPE (rhs1));
if (n->size % BITS_PER_UNIT != 0)
n->type = TREE_TYPE (rhs1);
size = TYPE_PRECISION (n->type);
if (size % BITS_PER_UNIT != 0)
return NULL_TREE;
n->size /= BITS_PER_UNIT;
if (size > HOST_BITS_PER_WIDEST_INT)
return NULL_TREE;
size /= BITS_PER_UNIT;
n->n = (sizeof (HOST_WIDEST_INT) < 8 ? 0 :
(unsigned HOST_WIDEST_INT)0x08070605 << 32 | 0x04030201);
if (n->size < (int)sizeof (HOST_WIDEST_INT))
if (size < (int)sizeof (HOST_WIDEST_INT))
n->n &= ((unsigned HOST_WIDEST_INT)1 <<
(n->size * BITS_PER_UNIT)) - 1;
(size * BITS_PER_UNIT)) - 1;
source_expr1 = rhs1;
}
@ -1672,12 +1683,12 @@ find_bswap_1 (gimple stmt, struct symbolic_number *n, int limit)
{
case BIT_AND_EXPR:
{
int i;
int i, size = TYPE_PRECISION (n->type) / BITS_PER_UNIT;
unsigned HOST_WIDEST_INT val = widest_int_cst_value (rhs2);
unsigned HOST_WIDEST_INT tmp = val;
/* Only constants masking full bytes are allowed. */
for (i = 0; i < n->size; i++, tmp >>= BITS_PER_UNIT)
for (i = 0; i < size; i++, tmp >>= BITS_PER_UNIT)
if ((tmp & 0xff) != 0 && (tmp & 0xff) != 0xff)
return NULL_TREE;
@ -1693,11 +1704,23 @@ find_bswap_1 (gimple stmt, struct symbolic_number *n, int limit)
break;
CASE_CONVERT:
{
int type_size;
int type_size, old_type_size;
tree type;
type_size = TYPE_PRECISION (gimple_expr_type (stmt));
type = gimple_expr_type (stmt);
type_size = TYPE_PRECISION (type);
if (type_size % BITS_PER_UNIT != 0)
return NULL_TREE;
if (type_size > (int) HOST_BITS_PER_WIDEST_INT)
return NULL_TREE;
/* Sign extension: result is dependent on the value. */
old_type_size = TYPE_PRECISION (n->type);
if (!TYPE_UNSIGNED (n->type)
&& type_size > old_type_size
&& n->n &
((unsigned HOST_WIDEST_INT) 0xff << (old_type_size - 8)))
return NULL_TREE;
if (type_size / BITS_PER_UNIT < (int)(sizeof (HOST_WIDEST_INT)))
{
@ -1705,7 +1728,7 @@ find_bswap_1 (gimple stmt, struct symbolic_number *n, int limit)
belonging to the target type. */
n->n &= ((unsigned HOST_WIDEST_INT)1 << type_size) - 1;
}
n->size = type_size / BITS_PER_UNIT;
n->type = type;
}
break;
default:
@ -1718,7 +1741,7 @@ find_bswap_1 (gimple stmt, struct symbolic_number *n, int limit)
if (rhs_class == GIMPLE_BINARY_RHS)
{
int i;
int i, size;
struct symbolic_number n1, n2;
unsigned HOST_WIDEST_INT mask;
tree source_expr2;
@ -1742,11 +1765,12 @@ find_bswap_1 (gimple stmt, struct symbolic_number *n, int limit)
source_expr2 = find_bswap_1 (rhs2_stmt, &n2, limit - 1);
if (source_expr1 != source_expr2
|| n1.size != n2.size)
|| TYPE_PRECISION (n1.type) != TYPE_PRECISION (n2.type))
return NULL_TREE;
n->size = n1.size;
for (i = 0, mask = 0xff; i < n->size; i++, mask <<= BITS_PER_UNIT)
n->type = n1.type;
size = TYPE_PRECISION (n->type) / BITS_PER_UNIT;
for (i = 0, mask = 0xff; i < size; i++, mask <<= BITS_PER_UNIT)
{
unsigned HOST_WIDEST_INT masked1, masked2;
@ -1785,7 +1809,7 @@ find_bswap (gimple stmt)
struct symbolic_number n;
tree source_expr;
int limit;
int limit, bitsize;
/* The last parameter determines the depth search limit. It usually
correlates directly to the number of bytes to be touched. We
@ -1800,13 +1824,14 @@ find_bswap (gimple stmt)
return NULL_TREE;
/* Zero out the extra bits of N and CMP. */
if (n.size < (int)sizeof (HOST_WIDEST_INT))
bitsize = TYPE_PRECISION (n.type);
if (bitsize < 8 * (int)sizeof (HOST_WIDEST_INT))
{
unsigned HOST_WIDEST_INT mask =
((unsigned HOST_WIDEST_INT)1 << (n.size * BITS_PER_UNIT)) - 1;
((unsigned HOST_WIDEST_INT)1 << bitsize) - 1;
n.n &= mask;
cmp >>= (sizeof (HOST_WIDEST_INT) - n.size) * BITS_PER_UNIT;
cmp >>= sizeof (HOST_WIDEST_INT) * BITS_PER_UNIT - bitsize;
}
/* A complete byte swap should make the symbolic number to start
@ -1828,7 +1853,7 @@ execute_optimize_bswap (void)
bool changed = false;
tree bswap16_type = NULL_TREE, bswap32_type = NULL_TREE, bswap64_type = NULL_TREE;
if (BITS_PER_UNIT != 8)
if (BITS_PER_UNIT != 8 || CHAR_BIT != 8)
return 0;
if (sizeof (HOST_WIDEST_INT) < 8)

91
external/gpl3/gcc/dist/gcc/tree-ssa-sccvn.c vendored
View File

@ -3015,33 +3015,12 @@ visit_phi (gimple phi)
/* If all value numbered to the same value, the phi node has that
value. */
if (allsame)
{
if (is_gimple_min_invariant (sameval))
{
VN_INFO (PHI_RESULT (phi))->has_constants = true;
VN_INFO (PHI_RESULT (phi))->expr = sameval;
}
else
{
VN_INFO (PHI_RESULT (phi))->has_constants = false;
VN_INFO (PHI_RESULT (phi))->expr = sameval;
}
if (TREE_CODE (sameval) == SSA_NAME)
return visit_copy (PHI_RESULT (phi), sameval);
return set_ssa_val_to (PHI_RESULT (phi), sameval);
}
return set_ssa_val_to (PHI_RESULT (phi), sameval);
/* Otherwise, see if it is equivalent to a phi node in this block. */
result = vn_phi_lookup (phi);
if (result)
{
if (TREE_CODE (result) == SSA_NAME)
changed = visit_copy (PHI_RESULT (phi), result);
else
changed = set_ssa_val_to (PHI_RESULT (phi), result);
}
changed = set_ssa_val_to (PHI_RESULT (phi), result);
else
{
vn_phi_insert (phi, PHI_RESULT (phi));
@ -3142,24 +3121,18 @@ simplify_binary_expression (gimple stmt)
catch those with constants. The goal here is to simultaneously
combine constants between expressions, but avoid infinite
expansion of expressions during simplification. */
if (TREE_CODE (op0) == SSA_NAME)
{
if (VN_INFO (op0)->has_constants
op0 = vn_valueize (op0);
if (TREE_CODE (op0) == SSA_NAME
&& (VN_INFO (op0)->has_constants
|| TREE_CODE_CLASS (code) == tcc_comparison
|| code == COMPLEX_EXPR)
op0 = valueize_expr (vn_get_expr_for (op0));
else
op0 = vn_valueize (op0);
}
|| code == COMPLEX_EXPR))
op0 = valueize_expr (vn_get_expr_for (op0));
if (TREE_CODE (op1) == SSA_NAME)
{
if (VN_INFO (op1)->has_constants
|| code == COMPLEX_EXPR)
op1 = valueize_expr (vn_get_expr_for (op1));
else
op1 = vn_valueize (op1);
}
op1 = vn_valueize (op1);
if (TREE_CODE (op1) == SSA_NAME
&& (VN_INFO (op1)->has_constants
|| code == COMPLEX_EXPR))
op1 = valueize_expr (vn_get_expr_for (op1));
/* Pointer plus constant can be represented as invariant address.
Do so to allow further propatation, see also tree forwprop. */
@ -3217,27 +3190,31 @@ simplify_unary_expression (gimple stmt)
return NULL_TREE;
orig_op0 = op0;
if (VN_INFO (op0)->has_constants)
op0 = valueize_expr (vn_get_expr_for (op0));
else if (CONVERT_EXPR_CODE_P (code)
|| code == REALPART_EXPR
|| code == IMAGPART_EXPR
|| code == VIEW_CONVERT_EXPR
|| code == BIT_FIELD_REF)
op0 = vn_valueize (op0);
if (TREE_CODE (op0) == SSA_NAME)
{
/* We want to do tree-combining on conversion-like expressions.
Make sure we feed only SSA_NAMEs or constants to fold though. */
tree tem = valueize_expr (vn_get_expr_for (op0));
if (UNARY_CLASS_P (tem)
|| BINARY_CLASS_P (tem)
|| TREE_CODE (tem) == VIEW_CONVERT_EXPR
|| TREE_CODE (tem) == SSA_NAME
|| TREE_CODE (tem) == CONSTRUCTOR
|| is_gimple_min_invariant (tem))
op0 = tem;
if (VN_INFO (op0)->has_constants)
op0 = valueize_expr (vn_get_expr_for (op0));
else if (CONVERT_EXPR_CODE_P (code)
|| code == REALPART_EXPR
|| code == IMAGPART_EXPR
|| code == VIEW_CONVERT_EXPR
|| code == BIT_FIELD_REF)
{
/* We want to do tree-combining on conversion-like expressions.
Make sure we feed only SSA_NAMEs or constants to fold though. */
tree tem = valueize_expr (vn_get_expr_for (op0));
if (UNARY_CLASS_P (tem)
|| BINARY_CLASS_P (tem)
|| TREE_CODE (tem) == VIEW_CONVERT_EXPR
|| TREE_CODE (tem) == SSA_NAME
|| TREE_CODE (tem) == CONSTRUCTOR
|| is_gimple_min_invariant (tem))
op0 = tem;
}
}
/* Avoid folding if nothing changed, but remember the expression. */
/* Avoid folding if nothing changed. */
if (op0 == orig_op0)
return NULL_TREE;

23
external/gpl3/gcc/dist/gcc/tree-ssa-tail-merge.c vendored
View File

@ -1060,6 +1060,24 @@ set_cluster (basic_block bb1, basic_block bb2)
gcc_unreachable ();
}
/* Return true if gimple operands T1 and T2 have the same value. */
static bool
gimple_operand_equal_value_p (tree t1, tree t2)
{
if (t1 == t2)
return true;
if (t1 == NULL_TREE
|| t2 == NULL_TREE)
return false;
if (operand_equal_p (t1, t2, 0))
return true;
return gvn_uses_equal (t1, t2);
}
/* Return true if gimple statements S1 and S2 are equal. Gimple_bb (s1) and
gimple_bb (s2) are members of SAME_SUCC. */
@ -1122,8 +1140,9 @@ gimple_equal_p (same_succ same_succ, gimple s1, gimple s2)
lhs2 = gimple_get_lhs (s2);
if (TREE_CODE (lhs1) != SSA_NAME
&& TREE_CODE (lhs2) != SSA_NAME)
return (vn_valueize (gimple_vdef (s1))
== vn_valueize (gimple_vdef (s2)));
return (operand_equal_p (lhs1, lhs2, 0)
&& gimple_operand_equal_value_p (gimple_assign_rhs1 (s1),
gimple_assign_rhs1 (s2)));
else if (TREE_CODE (lhs1) == SSA_NAME
&& TREE_CODE (lhs2) == SSA_NAME)
return vn_valueize (lhs1) == vn_valueize (lhs2);

28
external/gpl3/gcc/dist/gcc/tree-vect-data-refs.c vendored
View File

@ -3553,6 +3553,9 @@ vect_get_new_vect_var (tree type, enum vect_var_kind var_kind, const char *name)
is as follows:
if LOOP=i_loop: &in (relative to i_loop)
if LOOP=j_loop: &in+i*2B (relative to j_loop)
BYTE_OFFSET: Optional, defaulted to NULL. If supplied, it is added to the
initial address. Unlike OFFSET, which is number of elements to
be added, BYTE_OFFSET is measured in bytes.
Output:
1. Return an SSA_NAME whose value is the address of the memory location of
@ -3566,7 +3569,8 @@ tree
vect_create_addr_base_for_vector_ref (gimple stmt,
gimple_seq *new_stmt_list,
tree offset,
struct loop *loop)
struct loop *loop,
tree byte_offset)
{
stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info);
@ -3628,6 +3632,16 @@ vect_create_addr_base_for_vector_ref (gimple stmt,
base_offset = force_gimple_operand (base_offset, &seq, false, tmp);
gimple_seq_add_seq (new_stmt_list, seq);
}
if (byte_offset)
{
tree tmp = create_tmp_var (sizetype, "offset");
byte_offset = fold_convert (sizetype, byte_offset);
base_offset = fold_build2 (PLUS_EXPR, sizetype,
base_offset, byte_offset);
base_offset = force_gimple_operand (base_offset, &seq, false, tmp);
gimple_seq_add_seq (new_stmt_list, seq);
}
/* base + base_offset */
if (loop_vinfo)
@ -3692,6 +3706,10 @@ vect_create_addr_base_for_vector_ref (gimple stmt,
5. BSI: location where the new stmts are to be placed if there is no loop
6. ONLY_INIT: indicate if ap is to be updated in the loop, or remain
pointing to the initial address.
7. BYTE_OFFSET (optional, defaults to NULL): a byte offset to be added
to the initial address accessed by the data-ref in STMT. This is
similar to OFFSET, but OFFSET is counted in elements, while BYTE_OFFSET
in bytes.
Output:
1. Declare a new ptr to vector_type, and have it point to the base of the
@ -3705,6 +3723,8 @@ vect_create_addr_base_for_vector_ref (gimple stmt,
initial_address = &a[init];
if OFFSET is supplied:
initial_address = &a[init + OFFSET];
if BYTE_OFFSET is supplied:
initial_address = &a[init] + BYTE_OFFSET;
Return the initial_address in INITIAL_ADDRESS.
@ -3722,7 +3742,7 @@ tree
vect_create_data_ref_ptr (gimple stmt, tree aggr_type, struct loop *at_loop,
tree offset, tree *initial_address,
gimple_stmt_iterator *gsi, gimple *ptr_incr,
bool only_init, bool *inv_p)
bool only_init, bool *inv_p, tree byte_offset)
{
const char *base_name;
stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
@ -3881,10 +3901,10 @@ vect_create_data_ref_ptr (gimple stmt, tree aggr_type, struct loop *at_loop,
/* (2) Calculate the initial address of the aggregate-pointer, and set
the aggregate-pointer to point to it before the loop. */
/* Create: (&(base[init_val+offset]) in the loop preheader. */
/* Create: (&(base[init_val+offset]+byte_offset) in the loop preheader. */
new_temp = vect_create_addr_base_for_vector_ref (stmt, &new_stmt_list,
offset, loop);
offset, loop, byte_offset);
if (new_stmt_list)
{
if (pe)

3
external/gpl3/gcc/dist/gcc/tree-vect-loop.c vendored
View File

@ -2205,7 +2205,8 @@ vect_is_simple_reduction_1 (loop_vec_info loop_info, gimple phi,
}
def1 = SSA_NAME_DEF_STMT (op1);
if (flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
if (gimple_bb (def1)
&& flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
&& loop->inner
&& flow_bb_inside_loop_p (loop->inner, gimple_bb (def1))
&& is_gimple_assign (def1))

2
external/gpl3/gcc/dist/gcc/tree-vect-patterns.c vendored
View File

@ -395,7 +395,7 @@ vect_recog_dot_prod_pattern (vec<gimple> *stmts, tree *type_in,
|| !promotion)
return NULL;
oprnd00 = gimple_assign_rhs1 (def_stmt);
if (!type_conversion_p (oprnd0, stmt, true, &half_type1, &def_stmt,
if (!type_conversion_p (oprnd1, stmt, true, &half_type1, &def_stmt,
&promotion)
|| !promotion)
return NULL;

5
external/gpl3/gcc/dist/gcc/tree-vect-slp.c vendored
View File

@ -1837,7 +1837,10 @@ vect_detect_hybrid_slp_stmts (slp_tree node)
&& (stmt_vinfo = vinfo_for_stmt (use_stmt))
&& !STMT_SLP_TYPE (stmt_vinfo)
&& (STMT_VINFO_RELEVANT (stmt_vinfo)
|| VECTORIZABLE_CYCLE_DEF (STMT_VINFO_DEF_TYPE (stmt_vinfo)))
|| VECTORIZABLE_CYCLE_DEF (STMT_VINFO_DEF_TYPE (stmt_vinfo))
|| (STMT_VINFO_IN_PATTERN_P (stmt_vinfo)
&& STMT_VINFO_RELATED_STMT (stmt_vinfo)
&& !STMT_SLP_TYPE (vinfo_for_stmt (STMT_VINFO_RELATED_STMT (stmt_vinfo)))))
&& !(gimple_code (use_stmt) == GIMPLE_PHI
&& STMT_VINFO_DEF_TYPE (stmt_vinfo)
== vect_reduction_def))

7
external/gpl3/gcc/dist/gcc/tree-vect-stmts.c vendored
View File

@ -4319,6 +4319,7 @@ vectorizable_load (gimple stmt, gimple_stmt_iterator *gsi, gimple *vec_stmt,
int i, j, group_size;
tree msq = NULL_TREE, lsq;
tree offset = NULL_TREE;
tree byte_offset = NULL_TREE;
tree realignment_token = NULL_TREE;
gimple phi = NULL;
vec<tree> dr_chain = vNULL;
@ -4934,7 +4935,8 @@ vectorizable_load (gimple stmt, gimple_stmt_iterator *gsi, gimple *vec_stmt,
if (alignment_support_scheme == dr_explicit_realign_optimized)
{
phi = SSA_NAME_DEF_STMT (msq);
offset = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1);
byte_offset = size_binop (MINUS_EXPR, TYPE_SIZE_UNIT (vectype),
size_one_node);
}
}
else
@ -4955,7 +4957,8 @@ vectorizable_load (gimple stmt, gimple_stmt_iterator *gsi, gimple *vec_stmt,
if (j == 0)
dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type, at_loop,
offset, &dummy, gsi,
&ptr_incr, false, &inv_p);
&ptr_incr, false, &inv_p,
byte_offset);
else
dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
TYPE_SIZE_UNIT (aggr_type));

10
external/gpl3/gcc/dist/gcc/tree-vectorizer.h vendored
View File

@ -324,9 +324,9 @@ typedef struct _loop_vec_info {
#define LOOP_VINFO_OPERANDS_SWAPPED(L) (L)->operands_swapped
#define LOOP_REQUIRES_VERSIONING_FOR_ALIGNMENT(L) \
(L)->may_misalign_stmts.length () > 0
((L)->may_misalign_stmts.length () > 0)
#define LOOP_REQUIRES_VERSIONING_FOR_ALIAS(L) \
(L)->may_alias_ddrs.length () > 0
((L)->may_alias_ddrs.length () > 0)
#define NITERS_KNOWN_P(n) \
(host_integerp ((n),0) \
@ -931,7 +931,8 @@ extern tree vect_check_gather (gimple, loop_vec_info, tree *, tree *,
extern bool vect_analyze_data_refs (loop_vec_info, bb_vec_info, int *);
extern tree vect_create_data_ref_ptr (gimple, tree, struct loop *, tree,
tree *, gimple_stmt_iterator *,
gimple *, bool, bool *);
gimple *, bool, bool *,
tree = NULL_TREE);
extern tree bump_vector_ptr (tree, gimple, gimple_stmt_iterator *, gimple, tree);
extern tree vect_create_destination_var (tree, tree);
extern bool vect_grouped_store_supported (tree, unsigned HOST_WIDE_INT);
@ -949,7 +950,8 @@ extern void vect_record_grouped_load_vectors (gimple, vec<tree> );
extern int vect_get_place_in_interleaving_chain (gimple, gimple);
extern tree vect_get_new_vect_var (tree, enum vect_var_kind, const char *);
extern tree vect_create_addr_base_for_vector_ref (gimple, gimple_seq *,
tree, struct loop *);
tree, struct loop *,
tree = NULL_TREE);
/* In tree-vect-loop.c. */
/* FORNOW: Used in tree-parloops.c. */

5
external/gpl3/gcc/dist/libgcc/ChangeLog vendored
View File

@ -1,3 +1,8 @@
2014-09-18 Joseph Myers <joseph@codesourcery.com>
* config/i386/sfp-machine.h (FP_TRAPPING_EXCEPTIONS): Treat clear
bits not set bits as indicating trapping exceptions.
2014-05-22 Release Manager
* GCC 4.8.3 released.

2
external/gpl3/gcc/dist/libgcc/config/i386/sfp-machine.h vendored
View File

@ -59,7 +59,7 @@ void __sfp_handle_exceptions (int);
__sfp_handle_exceptions (_fex); \
} while (0);
#define FP_TRAPPING_EXCEPTIONS ((_fcw >> FP_EX_SHIFT) & FP_EX_ALL)
#define FP_TRAPPING_EXCEPTIONS ((~_fcw >> FP_EX_SHIFT) & FP_EX_ALL)
#define FP_ROUNDMODE (_fcw & FP_RND_MASK)
#endif

13
external/gpl3/gcc/dist/libobjc/ChangeLog vendored
View File

@ -1,3 +1,16 @@
2014-07-27 Ulrich Weigand <uweigand@de.ibm.com>
PR libobjc/61920
* encoding.c (rs6000_special_adjust_field_align_p): Use definition
that matches the 4.8 branch ABI.
2014-07-27 Alan Modra <amodra@gmail.com>
Matthias Klose <doko@ubuntu.com>
PR libobjc/61920
* encoding.c: Define rs6000_special_adjust_field_align_p.
2014-05-22 Release Manager
* GCC 4.8.3 released.

81
external/gpl3/gcc/dist/libstdc++-v3/ChangeLog vendored
View File

@ -1,3 +1,84 @@
2014-10-03 Jonathan Wakely <jwakely@redhat.com>
PR libstdc++/63449
* doc/xml/manual/containers.xml: Remove outdated section. Update
std::list notes.
* doc/html/*: Regenerate.
2014-10-01 Jonathan Wakely <jwakely@redhat.com>
* doc/xml/manual/status_cxx2011.xml: Corrections.
* doc/html/manual/status.html: Regenerate.
2014-08-28 Samuel Bronson <naesten@gmail.com>
Backport r212453 from trunk
2014-07-11 Samuel Bronson <naesten@gmail.com>
Matthias Klose <doko@ubuntu.com>
PR libstdc++/58962
* python/libstdcxx/v6/printers.py: Port to Python 2+3
(imap): New compat function.
(izip): Likewise.
(Iterator): New mixin to allow writing iterators in Python 3 style
regardless of which version we're running on.
[Python3] (long) New compat alias for "int".
* testsuite/lib/gdb-test.exp: Port to Python 2+3 (print syntax)
Backport r210625 from trunk
2014-05-19 Jonathan Wakely <jwakely@redhat.com>
* python/libstdcxx/v6/printers.py: Use Python3 raise syntax.
2014-08-26 John David Anglin <danglin@gcc.gnu.org>
* config/abi/post/hppa-linux-gnu/baseline_symbols.txt: Update.
2014-08-26 Jonathan Wakely <jwakely@redhat.com>
* doc/xml/manual/status_cxx2011.xml: Correct status table.
* doc/html/manual/*: Regenerate.
2014-08-04 Jonathan Wakely <jwakely@redhat.com>
Backported from mainline
2014-07-29 Jonathan Wakely <jwakely@redhat.com>
PR libstdc++/61946
* include/ext/rope (rope::rope(char_producer<_CharT>*, size_t, bool,
const allocator_type&)): Pass non-const allocator to
_S_new_RopeFunction.
* testsuite/ext/rope/61946.cc: New.
2014-08-04 Zifei Tong <zifeitong@gmail.com>
* libsupc++/atexit_thread.cc (HAVE___CXA_THREAD_ATEXIT_IMPL): Add
_GLIBCXX_ prefix to macro.
2014-06-03 Jonathan Wakely <jwakely@redhat.com>
Backport from mainline
2014-04-15 Jonathan Wakely <jwakely@redhat.com>
PR libstdc++/60734
* include/bits/stl_tree.h (_Rb_tree::_M_end): Fix invalid cast.
Backport from mainline
2014-05-16 Jonathan Wakely <jwakely@redhat.com>
PR libstdc++/60966
* include/std/future (__future_base::_State_baseV2::_M_set_result):
Signal condition variable after call_once returns.
(__future_base::_State_baseV2::_M_do_set): Do not signal here.
(promise::set_value, promise::set_exception): Increment the reference
count on the shared state until the function returns.
* testsuite/30_threads/promise/60966.cc: New.
2014-05-29 Jonathan Wakely <jwakely@redhat.com>
* include/tr2/bool_set: Use UTF-8 for accented characters.
* scripts/run_doxygen: Handle Doxygen 1.8.x change.
2014-05-22 Release Manager
* GCC 4.8.3 released.

17
external/gpl3/gcc/dist/libstdc++-v3/config/abi/post/hppa-linux-gnu/baseline_symbols.txt vendored
View File

@ -400,6 +400,7 @@ FUNC:_ZNKSt15basic_streambufIwSt11char_traitsIwEE5pbaseEv@@GLIBCXX_3.4
FUNC:_ZNKSt15basic_streambufIwSt11char_traitsIwEE6getlocEv@@GLIBCXX_3.4
FUNC:_ZNKSt15basic_stringbufIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4
FUNC:_ZNKSt15basic_stringbufIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4
FUNC:_ZNKSt17bad_function_call4whatEv@@GLIBCXX_3.4.18
FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX_3.4
FUNC:_ZNKSt18basic_stringstreamIcSt11char_traitsIcESaIcEE5rdbufEv@@GLIBCXX_3.4
FUNC:_ZNKSt18basic_stringstreamIwSt11char_traitsIwESaIwEE3strEv@@GLIBCXX_3.4
@ -587,6 +588,8 @@ FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt
FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewm@@GLIBCXX_3.4
FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewx@@GLIBCXX_3.4
FUNC:_ZNKSt7num_putIwSt19ostreambuf_iteratorIwSt11char_traitsIwEEE6do_putES3_RSt8ios_basewy@@GLIBCXX_3.4
FUNC:_ZNKSt8__detail20_Prime_rehash_policy11_M_next_bktEj@@GLIBCXX_3.4.18
FUNC:_ZNKSt8__detail20_Prime_rehash_policy14_M_need_rehashEjjj@@GLIBCXX_3.4.18
FUNC:_ZNKSt8bad_cast4whatEv@@GLIBCXX_3.4.9
FUNC:_ZNKSt8ios_base7failure4whatEv@@GLIBCXX_3.4
FUNC:_ZNKSt8messagesIcE18_M_convert_to_charERKSs@@GLIBCXX_3.4
@ -1204,6 +1207,7 @@ FUNC:_ZNSt11range_errorD2Ev@@GLIBCXX_3.4.15
FUNC:_ZNSt11regex_errorD0Ev@@GLIBCXX_3.4.15
FUNC:_ZNSt11regex_errorD1Ev@@GLIBCXX_3.4.15
FUNC:_ZNSt11regex_errorD2Ev@@GLIBCXX_3.4.15
FUNC:_ZNSt11this_thread11__sleep_forENSt6chrono8durationIxSt5ratioILx1ELx1EEEENS1_IxS2_ILx1ELx1000000000EEEE@@GLIBCXX_3.4.18
FUNC:_ZNSt12__basic_fileIcE2fdEv@@GLIBCXX_3.4
FUNC:_ZNSt12__basic_fileIcE4fileEv@@GLIBCXX_3.4.1
FUNC:_ZNSt12__basic_fileIcE4openEPKcSt13_Ios_Openmodei@@GLIBCXX_3.4
@ -1471,6 +1475,11 @@ FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEs@@GLIBCXX_3.4
FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEt@@GLIBCXX_3.4
FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEx@@GLIBCXX_3.4
FUNC:_ZNSt13basic_ostreamIwSt11char_traitsIwEElsEy@@GLIBCXX_3.4
FUNC:_ZNSt13random_device14_M_init_pretr1ERKSs@@GLIBCXX_3.4.18
FUNC:_ZNSt13random_device16_M_getval_pretr1Ev@@GLIBCXX_3.4.18
FUNC:_ZNSt13random_device7_M_finiEv@@GLIBCXX_3.4.18
FUNC:_ZNSt13random_device7_M_initERKSs@@GLIBCXX_3.4.18
FUNC:_ZNSt13random_device9_M_getvalEv@@GLIBCXX_3.4.18
FUNC:_ZNSt13runtime_errorC1ERKSs@@GLIBCXX_3.4
FUNC:_ZNSt13runtime_errorC2ERKSs@@GLIBCXX_3.4
FUNC:_ZNSt13runtime_errorD0Ev@@GLIBCXX_3.4
@ -1900,6 +1909,8 @@ FUNC:_ZNSt6__norm15_List_node_base7reverseEv@@GLIBCXX_3.4.9
FUNC:_ZNSt6__norm15_List_node_base8transferEPS0_S1_@@GLIBCXX_3.4.9
FUNC:_ZNSt6__norm15_List_node_base9_M_unhookEv@@GLIBCXX_3.4.14
FUNC:_ZNSt6chrono12system_clock3nowEv@@GLIBCXX_3.4.11
FUNC:_ZNSt6chrono3_V212steady_clock3nowEv@@GLIBCXX_3.4.19
FUNC:_ZNSt6chrono3_V212system_clock3nowEv@@GLIBCXX_3.4.19
FUNC:_ZNSt6gslice8_IndexerC1EjRKSt8valarrayIjES4_@@GLIBCXX_3.4
FUNC:_ZNSt6gslice8_IndexerC2EjRKSt8valarrayIjES4_@@GLIBCXX_3.4
FUNC:_ZNSt6locale11_M_coalesceERKS_S1_i@@GLIBCXX_3.4
@ -2436,6 +2447,7 @@ FUNC:__cxa_guard_acquire@@CXXABI_1.3
FUNC:__cxa_guard_release@@CXXABI_1.3
FUNC:__cxa_pure_virtual@@CXXABI_1.3
FUNC:__cxa_rethrow@@CXXABI_1.3
FUNC:__cxa_thread_atexit@@CXXABI_1.3.7
FUNC:__cxa_throw@@CXXABI_1.3
FUNC:__cxa_tm_cleanup@@CXXABI_TM_1
FUNC:__cxa_vec_cctor@@CXXABI_1.3
@ -2482,6 +2494,7 @@ OBJECT:0:CXXABI_1.3.3
OBJECT:0:CXXABI_1.3.4
OBJECT:0:CXXABI_1.3.5
OBJECT:0:CXXABI_1.3.6
OBJECT:0:CXXABI_1.3.7
OBJECT:0:CXXABI_TM_1
OBJECT:0:GLIBCXX_3.4
OBJECT:0:GLIBCXX_3.4.1
@ -2493,6 +2506,8 @@ OBJECT:0:GLIBCXX_3.4.14
OBJECT:0:GLIBCXX_3.4.15
OBJECT:0:GLIBCXX_3.4.16
OBJECT:0:GLIBCXX_3.4.17
OBJECT:0:GLIBCXX_3.4.18
OBJECT:0:GLIBCXX_3.4.19
OBJECT:0:GLIBCXX_3.4.2
OBJECT:0:GLIBCXX_3.4.3
OBJECT:0:GLIBCXX_3.4.4
@ -2992,6 +3007,8 @@ OBJECT:1:_ZNSt21__numeric_limits_base9is_iec559E@@GLIBCXX_3.4
OBJECT:1:_ZNSt21__numeric_limits_base9is_moduloE@@GLIBCXX_3.4
OBJECT:1:_ZNSt21__numeric_limits_base9is_signedE@@GLIBCXX_3.4
OBJECT:1:_ZNSt6chrono12system_clock12is_monotonicE@@GLIBCXX_3.4.11
OBJECT:1:_ZNSt6chrono3_V212steady_clock9is_steadyE@@GLIBCXX_3.4.19
OBJECT:1:_ZNSt6chrono3_V212system_clock9is_steadyE@@GLIBCXX_3.4.19
OBJECT:1:_ZSt10adopt_lock@@GLIBCXX_3.4.11
OBJECT:1:_ZSt10defer_lock@@GLIBCXX_3.4.11
OBJECT:1:_ZSt11try_to_lock@@GLIBCXX_3.4.11

4
external/gpl3/gcc/dist/libstdc++-v3/doc/html/index.html vendored
View File

@ -43,7 +43,7 @@
</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="manual/localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="manual/localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="manual/facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="manual/facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="manual/facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="manual/facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="manual/facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="manual/facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/containers.html">9.
Containers
</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="manual/containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="manual/associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="manual/associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="manual/associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="manual/associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="manual/unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="manual/unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/iterators.html">10.
</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="manual/associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="manual/associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="manual/associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="manual/associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="manual/unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="manual/unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="manual/containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="manual/containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/iterators.html">10.
Iterators
</a></span></dt><dd><dl><dt><span class="section"><a href="manual/iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="manual/iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="manual/iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="manual/algorithms.html">11.
@ -162,4 +162,4 @@ Support for C++11 dialect.
</a></span></dt><dt><span class="appendix"><a href="manual/appendix_gpl.html">D.
<acronym class="acronym">GNU</acronym> General Public License version 3
</a></span></dt><dt><span class="appendix"><a href="manual/appendix_gfdl.html">E. GNU Free Documentation License</a></span></dt></dl></dd></dl></dd><dt><span class="book"><a href="bk02.html"></a></span></dt><dd><dl><dt><span class="article"><a href="api.html">The GNU C++ Library API Reference</a></span></dt></dl></dd><dt><span class="book"><a href="bk03.html"></a></span></dt><dd><dl><dt><span class="article"><a href="faq.html">Frequently Asked Questions</a></span></dt></dl></dd></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"> </td><td width="20%" align="center"> </td><td width="40%" align="right" valign="top"> The GNU C++ Library Manual</td></tr></table></div></body></html>
</a></span></dt><dt><span class="appendix"><a href="manual/appendix_gfdl.html">E. GNU Free Documentation License</a></span></dt></dl></dd></dl></dd><dt><span class="book"><a href="bk02.html"></a></span></dt><dd><dl><dt><span class="article"><a href="api.html">The GNU C++ Library API Reference</a></span></dt></dl></dd><dt><span class="book"><a href="bk03.html"></a></span></dt><dd><dl><dt><span class="article"><a href="faq.html">Frequently Asked Questions</a></span></dt></dl></dd></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="manual/index.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"> </td><td width="20%" align="center"> </td><td width="40%" align="right" valign="top"> The GNU C++ Library Manual</td></tr></table></div></body></html>

6
external/gpl3/gcc/dist/libstdc++-v3/doc/html/manual/abi.html vendored
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@ -96,7 +96,7 @@ compatible.
definitions, where the version definition is the maximum for a
particular release. Labels are cumulative. If a particular release
is not listed, it has the same version labels as the preceding
release.</p><p>This corresponds to the mapfile: gcc/libgcc-std.ver</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: GCC_3.0</p></li><li class="listitem"><p>GCC 3.3.0: GCC_3.3</p></li><li class="listitem"><p>GCC 3.3.1: GCC_3.3.1</p></li><li class="listitem"><p>GCC 3.3.2: GCC_3.3.2</p></li><li class="listitem"><p>GCC 3.3.4: GCC_3.3.4</p></li><li class="listitem"><p>GCC 3.4.0: GCC_3.4</p></li><li class="listitem"><p>GCC 3.4.2: GCC_3.4.2</p></li><li class="listitem"><p>GCC 3.4.4: GCC_3.4.4</p></li><li class="listitem"><p>GCC 4.0.0: GCC_4.0.0</p></li><li class="listitem"><p>GCC 4.1.0: GCC_4.1.0</p></li><li class="listitem"><p>GCC 4.2.0: GCC_4.2.0</p></li><li class="listitem"><p>GCC 4.3.0: GCC_4.3.0</p></li><li class="listitem"><p>GCC 4.4.0: GCC_4.4.0</p></li><li class="listitem"><p>GCC 4.5.0: GCC_4.5.0</p></li><li class="listitem"><p>GCC 4.6.0: GCC_4.6.0</p></li><li class="listitem"><p>GCC 4.7.0: GCC_4.7.0</p></li></ul></div></li><li class="listitem"><p>
release.</p><p>This corresponds to the mapfile: gcc/libgcc-std.ver</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: GCC_3.0</p></li><li class="listitem"><p>GCC 3.3.0: GCC_3.3</p></li><li class="listitem"><p>GCC 3.3.1: GCC_3.3.1</p></li><li class="listitem"><p>GCC 3.3.2: GCC_3.3.2</p></li><li class="listitem"><p>GCC 3.3.4: GCC_3.3.4</p></li><li class="listitem"><p>GCC 3.4.0: GCC_3.4</p></li><li class="listitem"><p>GCC 3.4.2: GCC_3.4.2</p></li><li class="listitem"><p>GCC 3.4.4: GCC_3.4.4</p></li><li class="listitem"><p>GCC 4.0.0: GCC_4.0.0</p></li><li class="listitem"><p>GCC 4.1.0: GCC_4.1.0</p></li><li class="listitem"><p>GCC 4.2.0: GCC_4.2.0</p></li><li class="listitem"><p>GCC 4.3.0: GCC_4.3.0</p></li><li class="listitem"><p>GCC 4.4.0: GCC_4.4.0</p></li><li class="listitem"><p>GCC 4.5.0: GCC_4.5.0</p></li><li class="listitem"><p>GCC 4.6.0: GCC_4.6.0</p></li><li class="listitem"><p>GCC 4.7.0: GCC_4.7.0</p></li><li class="listitem"><p>GCC 4.8.0: GCC_4.8.0</p></li></ul></div></li><li class="listitem"><p>
Release versioning on the libstdc++.so binary, implemented in
the same way as the libgcc_s.so binary above. Listed is the
filename: <code class="constant">DT_SONAME</code> can be deduced from
@ -111,7 +111,7 @@ compatible.
has the same filename and <code class="constant">DT_SONAME</code> as the
preceding release.
</p><p>It is versioned as follows:
</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: libstdc++.so.3.0.0</p></li><li class="listitem"><p>GCC 3.0.1: libstdc++.so.3.0.1</p></li><li class="listitem"><p>GCC 3.0.2: libstdc++.so.3.0.2</p></li><li class="listitem"><p>GCC 3.0.3: libstdc++.so.3.0.2 (See Note 1)</p></li><li class="listitem"><p>GCC 3.0.4: libstdc++.so.3.0.4</p></li><li class="listitem"><p>GCC 3.1.0: libstdc++.so.4.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.1.1: libstdc++.so.4.0.1</p></li><li class="listitem"><p>GCC 3.2.0: libstdc++.so.5.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.2.1: libstdc++.so.5.0.1</p></li><li class="listitem"><p>GCC 3.2.2: libstdc++.so.5.0.2</p></li><li class="listitem"><p>GCC 3.2.3: libstdc++.so.5.0.3 (See Note 2)</p></li><li class="listitem"><p>GCC 3.3.0: libstdc++.so.5.0.4</p></li><li class="listitem"><p>GCC 3.3.1: libstdc++.so.5.0.5</p></li><li class="listitem"><p>GCC 3.4.0: libstdc++.so.6.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.4.1: libstdc++.so.6.0.1</p></li><li class="listitem"><p>GCC 3.4.2: libstdc++.so.6.0.2</p></li><li class="listitem"><p>GCC 3.4.3: libstdc++.so.6.0.3</p></li><li class="listitem"><p>GCC 4.0.0: libstdc++.so.6.0.4</p></li><li class="listitem"><p>GCC 4.0.1: libstdc++.so.6.0.5</p></li><li class="listitem"><p>GCC 4.0.2: libstdc++.so.6.0.6</p></li><li class="listitem"><p>GCC 4.0.3: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.0: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.1: libstdc++.so.6.0.8</p></li><li class="listitem"><p>GCC 4.2.0: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.2.1: libstdc++.so.6.0.9 (See Note 3)</p></li><li class="listitem"><p>GCC 4.2.2: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.3.0: libstdc++.so.6.0.10</p></li><li class="listitem"><p>GCC 4.4.0: libstdc++.so.6.0.11</p></li><li class="listitem"><p>GCC 4.4.1: libstdc++.so.6.0.12</p></li><li class="listitem"><p>GCC 4.4.2: libstdc++.so.6.0.13</p></li><li class="listitem"><p>GCC 4.5.0: libstdc++.so.6.0.14</p></li><li class="listitem"><p>GCC 4.6.0: libstdc++.so.6.0.15</p></li><li class="listitem"><p>GCC 4.6.1: libstdc++.so.6.0.16</p></li><li class="listitem"><p>GCC 4.7.0: libstdc++.so.6.0.17</p></li><li class="listitem"><p>GCC 4.8.0: libstdc++.so.6.0.18</p></li></ul></div><p>
</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: libstdc++.so.3.0.0</p></li><li class="listitem"><p>GCC 3.0.1: libstdc++.so.3.0.1</p></li><li class="listitem"><p>GCC 3.0.2: libstdc++.so.3.0.2</p></li><li class="listitem"><p>GCC 3.0.3: libstdc++.so.3.0.2 (See Note 1)</p></li><li class="listitem"><p>GCC 3.0.4: libstdc++.so.3.0.4</p></li><li class="listitem"><p>GCC 3.1.0: libstdc++.so.4.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.1.1: libstdc++.so.4.0.1</p></li><li class="listitem"><p>GCC 3.2.0: libstdc++.so.5.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.2.1: libstdc++.so.5.0.1</p></li><li class="listitem"><p>GCC 3.2.2: libstdc++.so.5.0.2</p></li><li class="listitem"><p>GCC 3.2.3: libstdc++.so.5.0.3 (See Note 2)</p></li><li class="listitem"><p>GCC 3.3.0: libstdc++.so.5.0.4</p></li><li class="listitem"><p>GCC 3.3.1: libstdc++.so.5.0.5</p></li><li class="listitem"><p>GCC 3.4.0: libstdc++.so.6.0.0 <span class="emphasis"><em>(Incompatible with previous)</em></span></p></li><li class="listitem"><p>GCC 3.4.1: libstdc++.so.6.0.1</p></li><li class="listitem"><p>GCC 3.4.2: libstdc++.so.6.0.2</p></li><li class="listitem"><p>GCC 3.4.3: libstdc++.so.6.0.3</p></li><li class="listitem"><p>GCC 4.0.0: libstdc++.so.6.0.4</p></li><li class="listitem"><p>GCC 4.0.1: libstdc++.so.6.0.5</p></li><li class="listitem"><p>GCC 4.0.2: libstdc++.so.6.0.6</p></li><li class="listitem"><p>GCC 4.0.3: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.0: libstdc++.so.6.0.7</p></li><li class="listitem"><p>GCC 4.1.1: libstdc++.so.6.0.8</p></li><li class="listitem"><p>GCC 4.2.0: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.2.1: libstdc++.so.6.0.9 (See Note 3)</p></li><li class="listitem"><p>GCC 4.2.2: libstdc++.so.6.0.9</p></li><li class="listitem"><p>GCC 4.3.0: libstdc++.so.6.0.10</p></li><li class="listitem"><p>GCC 4.4.0: libstdc++.so.6.0.11</p></li><li class="listitem"><p>GCC 4.4.1: libstdc++.so.6.0.12</p></li><li class="listitem"><p>GCC 4.4.2: libstdc++.so.6.0.13</p></li><li class="listitem"><p>GCC 4.5.0: libstdc++.so.6.0.14</p></li><li class="listitem"><p>GCC 4.6.0: libstdc++.so.6.0.15</p></li><li class="listitem"><p>GCC 4.6.1: libstdc++.so.6.0.16</p></li><li class="listitem"><p>GCC 4.7.0: libstdc++.so.6.0.17</p></li><li class="listitem"><p>GCC 4.8.0: libstdc++.so.6.0.18</p></li><li class="listitem"><p>GCC 4.8.3: libstdc++.so.6.0.19</p></li></ul></div><p>
Note 1: Error should be libstdc++.so.3.0.3.
</p><p>
Note 2: Not strictly required.
@ -129,7 +129,7 @@ compatible.
GLIBCPP_3.2 for symbols that were introduced in the GCC 3.2.0
release.) If a particular release is not listed, it has the same
version labels as the preceding release.
</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.1: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.2: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.3: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.4: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.1.0: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.1.1: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.2.0: GLIBCPP_3.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.1: GLIBCPP_3.2.1, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.2: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.3: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.3.0: GLIBCPP_3.2.2, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.1: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.2: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.3: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.4.0: GLIBCXX_3.4, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.1: GLIBCXX_3.4.1, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.2: GLIBCXX_3.4.2</p></li><li class="listitem"><p>GCC 3.4.3: GLIBCXX_3.4.3</p></li><li class="listitem"><p>GCC 4.0.0: GLIBCXX_3.4.4, CXXABI_1.3.1</p></li><li class="listitem"><p>GCC 4.0.1: GLIBCXX_3.4.5</p></li><li class="listitem"><p>GCC 4.0.2: GLIBCXX_3.4.6</p></li><li class="listitem"><p>GCC 4.0.3: GLIBCXX_3.4.7</p></li><li class="listitem"><p>GCC 4.1.1: GLIBCXX_3.4.8</p></li><li class="listitem"><p>GCC 4.2.0: GLIBCXX_3.4.9</p></li><li class="listitem"><p>GCC 4.3.0: GLIBCXX_3.4.10, CXXABI_1.3.2</p></li><li class="listitem"><p>GCC 4.4.0: GLIBCXX_3.4.11, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.1: GLIBCXX_3.4.12, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.2: GLIBCXX_3.4.13, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.5.0: GLIBCXX_3.4.14, CXXABI_1.3.4</p></li><li class="listitem"><p>GCC 4.6.0: GLIBCXX_3.4.15, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.6.1: GLIBCXX_3.4.16, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.7.0: GLIBCXX_3.4.17, CXXABI_1.3.6</p></li><li class="listitem"><p>GCC 4.8.0: GLIBCXX_3.4.18, CXXABI_1.3.7</p></li></ul></div></li><li class="listitem"><p>Incremental bumping of a compiler pre-defined macro,
</p><div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem"><p>GCC 3.0.0: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.1: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.2: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.3: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.0.4: (Error, not versioned)</p></li><li class="listitem"><p>GCC 3.1.0: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.1.1: GLIBCPP_3.1, CXXABI_1</p></li><li class="listitem"><p>GCC 3.2.0: GLIBCPP_3.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.1: GLIBCPP_3.2.1, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.2: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.2.3: GLIBCPP_3.2.2, CXXABI_1.2</p></li><li class="listitem"><p>GCC 3.3.0: GLIBCPP_3.2.2, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.1: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.2: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.3.3: GLIBCPP_3.2.3, CXXABI_1.2.1</p></li><li class="listitem"><p>GCC 3.4.0: GLIBCXX_3.4, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.1: GLIBCXX_3.4.1, CXXABI_1.3</p></li><li class="listitem"><p>GCC 3.4.2: GLIBCXX_3.4.2</p></li><li class="listitem"><p>GCC 3.4.3: GLIBCXX_3.4.3</p></li><li class="listitem"><p>GCC 4.0.0: GLIBCXX_3.4.4, CXXABI_1.3.1</p></li><li class="listitem"><p>GCC 4.0.1: GLIBCXX_3.4.5</p></li><li class="listitem"><p>GCC 4.0.2: GLIBCXX_3.4.6</p></li><li class="listitem"><p>GCC 4.0.3: GLIBCXX_3.4.7</p></li><li class="listitem"><p>GCC 4.1.1: GLIBCXX_3.4.8</p></li><li class="listitem"><p>GCC 4.2.0: GLIBCXX_3.4.9</p></li><li class="listitem"><p>GCC 4.3.0: GLIBCXX_3.4.10, CXXABI_1.3.2</p></li><li class="listitem"><p>GCC 4.4.0: GLIBCXX_3.4.11, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.1: GLIBCXX_3.4.12, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.4.2: GLIBCXX_3.4.13, CXXABI_1.3.3</p></li><li class="listitem"><p>GCC 4.5.0: GLIBCXX_3.4.14, CXXABI_1.3.4</p></li><li class="listitem"><p>GCC 4.6.0: GLIBCXX_3.4.15, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.6.1: GLIBCXX_3.4.16, CXXABI_1.3.5</p></li><li class="listitem"><p>GCC 4.7.0: GLIBCXX_3.4.17, CXXABI_1.3.6</p></li><li class="listitem"><p>GCC 4.8.0: GLIBCXX_3.4.18, CXXABI_1.3.7</p></li><li class="listitem"><p>GCC 4.8.3: GLIBCXX_3.4.19, CXXABI_1.3.7</p></li></ul></div></li><li class="listitem"><p>Incremental bumping of a compiler pre-defined macro,
__GXX_ABI_VERSION. This macro is defined as the version of the
compiler v3 ABI, with g++ 3.0 being version 100. This macro will
be automatically defined whenever g++ is used (the curious can

19
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@ -7,9 +7,10 @@
</th><td width="20%" align="right"> <a accesskey="n" href="associative.html">Next</a></td></tr></table><hr /></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a id="std.containers"></a>Chapter 9. 
Containers
<a id="idm269999493408" class="indexterm"></a>
</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.sequences"></a>Sequences</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.list"></a>list</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.list.size"></a>list::size() is O(n)</h4></div></div></div><p>
Yes it is, and that's okay. This is a decision that we preserved
when we imported SGI's STL implementation. The following is
</h2></div></div></div><div class="toc"><p><strong>Table of Contents</strong></p><dl class="toc"><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a id="std.containers.sequences"></a>Sequences</h2></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.list"></a>list</h3></div></div></div><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.list.size"></a>list::size() is O(n)</h4></div></div></div><p>
Yes it is, and that was okay until the 2011 edition of the C++ standard.
In future GCC will change it to O(1) but O(N) was a decision that we
preserved when we imported SGI's STL implementation. The following is
quoted from <a class="link" href="http://www.sgi.com/tech/stl/FAQ.html" target="_top">their FAQ</a>:
</p><div class="blockquote"><blockquote class="blockquote"><p>
The size() member function, for list and slist, takes time
@ -41,14 +42,4 @@
</p><pre class="programlisting">
if (L.empty())
...
</pre></blockquote></div></div></div><div class="section"><div class="titlepage"><div><div><h3 class="title"><a id="containers.sequences.vector"></a>vector</h3></div></div></div><p>
</p><div class="section"><div class="titlepage"><div><div><h4 class="title"><a id="sequences.vector.management"></a>Space Overhead Management</h4></div></div></div><p>
In <a class="link" href="http://gcc.gnu.org/ml/libstdc++/2002-04/msg00105.html" target="_top">this
message to the list</a>, Daniel Kostecky announced work on an
alternate form of <code class="code">std::vector</code> that would support
hints on the number of elements to be over-allocated. The design
was also described, along with possible implementation choices.
</p><p>
The first two alpha releases were announced <a class="link" href="http://gcc.gnu.org/ml/libstdc++/2002-07/msg00048.html" target="_top">here</a>
and <a class="link" href="http://gcc.gnu.org/ml/libstdc++/2002-07/msg00111.html" target="_top">here</a>.
</p></div></div></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="facets.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="std_contents.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="associative.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Facets </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Associative</td></tr></table></div></body></html>
</pre></blockquote></div></div></div></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="facets.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="std_contents.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="associative.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Facets </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Associative</td></tr></table></div></body></html>

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@ -24,7 +24,7 @@
</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.
Containers
</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10.
</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10.
Iterators
</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="algorithms.html">11.
@ -160,4 +160,4 @@ Support for C++11 dialect.
</a></dt></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="../index.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="intro.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">The GNU C++ Library </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Part I. 
Introduction
</td></tr></table></div></body></html>
</td></tr></table></div></body></html>

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@ -21,7 +21,7 @@
</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales">Locales</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#std.localization.locales.locale">locale</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locales.locale.req">Requirements</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.design">Design</a></span></dt><dt><span class="section"><a href="localization.html#locales.locale.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="localization.html#locale.impl.c">Interacting with "C" locales</a></span></dt></dl></dd><dt><span class="section"><a href="localization.html#locales.locale.future">Future</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="facets.html">Facets</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#std.localization.facet.ctype">ctype</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.ctype.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#idm269999753024">Specializations</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.ctype.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#std.localization.facet.codecvt">codecvt</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.codecvt.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.design">Design</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#codecvt.design.wchar_t_size"><span class="type">wchar_t</span> Size</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.unicode">Support for Unicode</a></span></dt><dt><span class="section"><a href="facets.html#codecvt.design.issues">Other Issues</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.codecvt.impl">Implementation</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.codecvt.future">Future</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#manual.localization.facet.messages">messages</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#facet.messages.req">Requirements</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.design">Design</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.impl">Implementation</a></span></dt><dd><dl><dt><span class="section"><a href="facets.html#messages.impl.models">Models</a></span></dt><dt><span class="section"><a href="facets.html#messages.impl.gnu">The GNU Model</a></span></dt></dl></dd><dt><span class="section"><a href="facets.html#facet.messages.use">Use</a></span></dt><dt><span class="section"><a href="facets.html#facet.messages.future">Future</a></span></dt></dl></dd></dl></dd></dl></dd><dt><span class="chapter"><a href="containers.html">9.
Containers
</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd><dt><span class="section"><a href="containers.html#containers.sequences.vector">vector</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.vector.management">Space Overhead Management</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10.
</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#std.containers.sequences">Sequences</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#containers.sequences.list">list</a></span></dt><dd><dl><dt><span class="section"><a href="containers.html#sequences.list.size">list::size() is O(n)</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="associative.html">Associative</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#containers.associative.insert_hints">Insertion Hints</a></span></dt><dt><span class="section"><a href="associative.html#containers.associative.bitset">bitset</a></span></dt><dd><dl><dt><span class="section"><a href="associative.html#associative.bitset.size_variable">Size Variable</a></span></dt><dt><span class="section"><a href="associative.html#associative.bitset.type_string">Type String</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="unordered_associative.html">Unordered Associative</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.hash">Hash Code</a></span></dt><dd><dl><dt><span class="section"><a href="unordered_associative.html#containers.unordered.cache">Hash Code Caching Policy</a></span></dt></dl></dd></dl></dd><dt><span class="section"><a href="containers_and_c.html">Interacting with C</a></span></dt><dd><dl><dt><span class="section"><a href="containers_and_c.html#containers.c.vs_array">Containers vs. Arrays</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="iterators.html">10.
Iterators
</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#std.iterators.predefined">Predefined</a></span></dt><dd><dl><dt><span class="section"><a href="iterators.html#iterators.predefined.vs_pointers">Iterators vs. Pointers</a></span></dt><dt><span class="section"><a href="iterators.html#iterators.predefined.end">One Past the End</a></span></dt></dl></dd></dl></dd><dt><span class="chapter"><a href="algorithms.html">11.
@ -42,4 +42,4 @@
</a></span></dt><dd><dl><dt><span class="section"><a href="concurrency.html#std.concurrency.api">API Reference</a></span></dt></dl></dd></dl></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="debug.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="index.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="support.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Debugging Support </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home</a></td><td width="40%" align="right" valign="top"> Chapter 4. 
Support
</td></tr></table></div></body></html>
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@ -25,8 +25,9 @@
<section xml:id="sequences.list.size" xreflabel="list::size() is O(n)"><info><title>list::size() is O(n)</title></info>
<para>
Yes it is, and that's okay. This is a decision that we preserved
when we imported SGI's STL implementation. The following is
Yes it is, and that was okay until the 2011 edition of the C++ standard.
In future GCC will change it to O(1) but O(N) was a decision that we
preserved when we imported SGI's STL implementation. The following is
quoted from <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://www.sgi.com/tech/stl/FAQ.html">their FAQ</link>:
</para>
<blockquote>
@ -72,26 +73,6 @@
</section>
</section>
<section xml:id="containers.sequences.vector" xreflabel="vector"><info><title>vector</title></info>
<?dbhtml filename="vector.html"?>
<para>
</para>
<section xml:id="sequences.vector.management" xreflabel="Space Overhead Management"><info><title>Space Overhead Management</title></info>
<para>
In <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/ml/libstdc++/2002-04/msg00105.html">this
message to the list</link>, Daniel Kostecky announced work on an
alternate form of <code>std::vector</code> that would support
hints on the number of elements to be over-allocated. The design
was also described, along with possible implementation choices.
</para>
<para>
The first two alpha releases were announced <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/ml/libstdc++/2002-07/msg00048.html">here</link>
and <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://gcc.gnu.org/ml/libstdc++/2002-07/msg00111.html">here</link>.
</para>
</section></section>
</section>
<!-- Sect1 02 : Associative -->

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@ -226,10 +226,12 @@ particular release.
<entry/>
</row>
<row>
<?dbhtml bgcolor="#B0B0B0" ?>
<entry>18.8.6</entry>
<entry><code>nested_exception</code></entry>
<entry>Y</entry>
<entry/>
<entry>Partial</entry>
<entry>Follows an earlier C++0x draft, not the final specification.
</entry>
</row>
<row>
<entry>18.9</entry>
@ -612,10 +614,11 @@ particular release.
<entry/>
</row>
<row>
<?dbhtml bgcolor="#B0B0B0" ?>
<entry>20.6.12.4</entry>
<entry><code>uninitialized_fill_n</code></entry>
<entry>Y</entry>
<entry/>
<entry>Partial</entry>
<entry>Returns <code>void</code>.</entry>
</row>
<row>
<entry>20.6.13</entry>
@ -1119,10 +1122,13 @@ particular release.
<entry/>
</row>
<row>
<?dbhtml bgcolor="#B0B0B0" ?>
<entry>21.4</entry>
<entry>Class template <code>basic_string</code></entry>
<entry>Y</entry>
<entry/>
<entry>Partial</entry>
<entry>Non-conforming Copy-On-Write implementation.
Missing <code>getline</code> overloads for rvalue streams.
</entry>
</row>
<row>
<entry>21.5</entry>
@ -1190,10 +1196,11 @@ particular release.
<entry/>
</row>
<row>
<?dbhtml bgcolor="#B0B0B0" ?>
<entry>22.3.3.1</entry>
<entry>Character classification</entry>
<entry>Y</entry>
<entry/>
<entry>Partial</entry>
<entry>Missing <code>isblank</code>.</entry>
</row>
<row>
<entry>22.3.3.2</entry>
@ -1272,16 +1279,18 @@ particular release.
<entry/>
</row>
<row>
<?dbhtml bgcolor="#B0B0B0" ?>
<entry>22.4.5.1</entry>
<entry>Class template <code>time_get</code></entry>
<entry>Y</entry>
<entry/>
<entry>Partial</entry>
<entry>Missing <code>get</code> and <code>do_get</code></entry>
</row>
<row>
<?dbhtml bgcolor="#B0B0B0" ?>
<entry>22.4.5.2</entry>
<entry>Class template <code>time_get_byname</code></entry>
<entry>Y</entry>
<entry/>
<entry>Partial</entry>
<entry>Likewise</entry>
</row>
<row>
<entry>22.4.5.3</entry>
@ -1434,8 +1443,10 @@ particular release.
<entry>23.3.5</entry>
<entry>Class template <code>list</code></entry>
<entry>Partial</entry>
<entry><code>insert</code> and <code>erase</code> members do not
take <code>const_iterator</code> arguments (N2350).</entry>
<entry>O(N) size.
<code>insert</code> and <code>erase</code> members do not
take <code>const_iterator</code> arguments (N2350).
</entry>
</row>
<row>
<?dbhtml bgcolor="#B0B0B0" ?>
@ -1650,10 +1661,11 @@ particular release.
<entry/>
</row>
<row>
<?dbhtml bgcolor="#B0B0B0" ?>
<entry>25.3</entry>
<entry>Mutating sequence operations</entry>
<entry>Y</entry>
<entry/>
<entry>Partial</entry>
<entry><code>rotate</code> returns <code>void</code>.</entry>
</row>
<row>
<entry>25.4</entry>
@ -2060,10 +2072,13 @@ particular release.
<entry/>
</row>
<row>
<?dbhtml bgcolor="#B0B0B0" ?>
<entry>26.8</entry>
<entry>C Library</entry>
<entry>Y</entry>
<entry/>
<entry>Partial</entry>
<entry><code>&lt;ctgmath&gt;</code> doesn't include
<code>&lt;ccomplex&gt;</code>
</entry>
</row>
<row>
<entry>
@ -2143,6 +2158,7 @@ particular release.
Missing move and swap operations on <code>basic_ios</code>.
Missing <code>io_errc</code> and <code>iostream_category</code>.
<code>ios_base::failure</code> is not derived from <code>system_error</code>.
Missing <code>ios_base::hexfloat</code>.
</entry>
</row>
<row>

4
external/gpl3/gcc/dist/libstdc++-v3/include/bits/stl_tree.h vendored
View File

@ -510,11 +510,11 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
_Link_type
_M_end()
{ return static_cast<_Link_type>(&this->_M_impl._M_header); }
{ return reinterpret_cast<_Link_type>(&this->_M_impl._M_header); }
_Const_Link_type
_M_end() const
{ return static_cast<_Const_Link_type>(&this->_M_impl._M_header); }
{ return reinterpret_cast<_Const_Link_type>(&this->_M_impl._M_header); }
static const_reference
_S_value(_Const_Link_type __x)

28
external/gpl3/gcc/dist/libstdc++-v3/include/std/future vendored
View File

@ -351,12 +351,14 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
void
_M_set_result(function<_Ptr_type()> __res, bool __ignore_failure = false)
{
bool __set = __ignore_failure;
bool __set = false;
// all calls to this function are serialized,
// side-effects of invoking __res only happen once
call_once(_M_once, &_State_base::_M_do_set, this, ref(__res),
ref(__set));
if (!__set)
if (__set)
_M_cond.notify_all();
else if (!__ignore_failure)
__throw_future_error(int(future_errc::promise_already_satisfied));
}
@ -471,7 +473,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
lock_guard<mutex> __lock(_M_mutex);
_M_result.swap(__res);
}
_M_cond.notify_all();
__set = true;
}
@ -983,22 +984,25 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
void
set_value(const _Res& __r)
{
auto __future = _M_future;
auto __setter = _State::__setter(this, __r);
_M_future->_M_set_result(std::move(__setter));
__future->_M_set_result(std::move(__setter));
}
void
set_value(_Res&& __r)
{
auto __future = _M_future;
auto __setter = _State::__setter(this, std::move(__r));
_M_future->_M_set_result(std::move(__setter));
__future->_M_set_result(std::move(__setter));
}
void
set_exception(exception_ptr __p)
{
auto __future = _M_future;
auto __setter = _State::__setter(__p, this);
_M_future->_M_set_result(std::move(__setter));
__future->_M_set_result(std::move(__setter));
}
};
@ -1081,15 +1085,17 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
void
set_value(_Res& __r)
{
auto __future = _M_future;
auto __setter = _State::__setter(this, __r);
_M_future->_M_set_result(std::move(__setter));
__future->_M_set_result(std::move(__setter));
}
void
set_exception(exception_ptr __p)
{
auto __future = _M_future;
auto __setter = _State::__setter(__p, this);
_M_future->_M_set_result(std::move(__setter));
__future->_M_set_result(std::move(__setter));
}
};
@ -1166,8 +1172,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
void
set_exception(exception_ptr __p)
{
auto __future = _M_future;
auto __setter = _State::__setter(__p, this);
_M_future->_M_set_result(std::move(__setter));
__future->_M_set_result(std::move(__setter));
}
};
@ -1193,8 +1200,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
inline void
promise<void>::set_value()
{
auto __future = _M_future;
auto __setter = _State::__setter(this);
_M_future->_M_set_result(std::move(__setter));
__future->_M_set_result(std::move(__setter));
}

2
external/gpl3/gcc/dist/libstdc++-v3/include/tr2/bool_set vendored
View File

@ -44,7 +44,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
* bool_set
*
* See N2136, Bool_set: multi-valued logic
* by Hervé Brönnimann, Guillaume Melquiond, Sylvain Pion.
* by Hervé Brönnimann, Guillaume Melquiond, Sylvain Pion.
*
* The implicit conversion to bool is slippery! I may use the new
* explicit conversion. This has been specialized in the language

6
external/gpl3/gcc/dist/libstdc++-v3/libsupc++/atexit_thread.cc vendored
View File

@ -26,7 +26,7 @@
#include <new>
#include "bits/gthr.h"
#if HAVE___CXA_THREAD_ATEXIT_IMPL
#if _GLIBCXX_HAVE___CXA_THREAD_ATEXIT_IMPL
extern "C" int __cxa_thread_atexit_impl (void (*func) (void *),
void *arg, void *d);
@ -38,7 +38,7 @@ __cxxabiv1::__cxa_thread_atexit (void (*dtor)(void *),
return __cxa_thread_atexit_impl (dtor, obj, dso_handle);
}
#else /* HAVE___CXA_THREAD_ATEXIT_IMPL */
#else /* _GLIBCXX_HAVE___CXA_THREAD_ATEXIT_IMPL */
namespace {
// One element in a singly-linked stack of cleanups.
@ -142,4 +142,4 @@ __cxxabiv1::__cxa_thread_atexit (void (*dtor)(void *), void *obj, void */*dso_ha
return 0;
}
#endif /* HAVE___CXA_THREAD_ATEXIT_IMPL */
#endif /* _GLIBCXX_HAVE___CXA_THREAD_ATEXIT_IMPL */

108
external/gpl3/gcc/dist/libstdc++-v3/python/libstdcxx/v6/printers.py vendored
View File

@ -1,4 +1,4 @@
# Pretty-printers for libstc++.
# Pretty-printers for libstdc++.
# Copyright (C) 2008-2013 Free Software Foundation, Inc.
@ -18,6 +18,50 @@
import gdb
import itertools
import re
import sys
### Python 2 + Python 3 compatibility code
# Resources about compatibility:
#
# * <http://pythonhosted.org/six/>: Documentation of the "six" module
# FIXME: The handling of e.g. std::basic_string (at least on char)
# probably needs updating to work with Python 3's new string rules.
#
# In particular, Python 3 has a separate type (called byte) for
# bytestrings, and a special b"" syntax for the byte literals; the old
# str() type has been redefined to always store Unicode text.
#
# We probably can't do much about this until this GDB PR is addressed:
# <https://sourceware.org/bugzilla/show_bug.cgi?id=17138>
if sys.version_info[0] > 2:
### Python 3 stuff
Iterator = object
# Python 3 folds these into the normal functions.
imap = map
izip = zip
# Also, int subsumes long
long = int
else:
### Python 2 stuff
class Iterator:
"""Compatibility mixin for iterators
Instead of writing next() methods for iterators, write
__next__() methods and use this mixin to make them work in
Python 2 as well as Python 3.
Idea stolen from the "six" documentation:
<http://pythonhosted.org/six/#six.Iterator>
"""
def next(self):
return self.__next__()
# In Python 2, we still need these from itertools
from itertools import imap, izip
# Try to use the new-style pretty-printing if available.
_use_gdb_pp = True
@ -51,7 +95,7 @@ def find_type(orig, name):
# anything fancier here.
field = typ.fields()[0]
if not field.is_base_class:
raise ValueError, "Cannot find type %s::%s" % (str(orig), name)
raise ValueError("Cannot find type %s::%s" % (str(orig), name))
typ = field.type
class SharedPointerPrinter:
@ -87,7 +131,7 @@ class UniquePointerPrinter:
class StdListPrinter:
"Print a std::list"
class _iterator:
class _iterator(Iterator):
def __init__(self, nodetype, head):
self.nodetype = nodetype
self.base = head['_M_next']
@ -97,7 +141,7 @@ class StdListPrinter:
def __iter__(self):
return self
def next(self):
def __next__(self):
if self.base == self.head:
raise StopIteration
elt = self.base.cast(self.nodetype).dereference()
@ -135,7 +179,7 @@ class StdListIteratorPrinter:
class StdSlistPrinter:
"Print a __gnu_cxx::slist"
class _iterator:
class _iterator(Iterator):
def __init__(self, nodetype, head):
self.nodetype = nodetype
self.base = head['_M_head']['_M_next']
@ -144,7 +188,7 @@ class StdSlistPrinter:
def __iter__(self):
return self
def next(self):
def __next__(self):
if self.base == 0:
raise StopIteration
elt = self.base.cast(self.nodetype).dereference()
@ -180,7 +224,7 @@ class StdSlistIteratorPrinter:
class StdVectorPrinter:
"Print a std::vector"
class _iterator:
class _iterator(Iterator):
def __init__ (self, start, finish, bitvec):
self.bitvec = bitvec
if bitvec:
@ -198,7 +242,7 @@ class StdVectorPrinter:
def __iter__(self):
return self
def next(self):
def __next__(self):
count = self.count
self.count = self.count + 1
if self.bitvec:
@ -265,7 +309,7 @@ class StdVectorIteratorPrinter:
class StdTuplePrinter:
"Print a std::tuple"
class _iterator:
class _iterator(Iterator):
def __init__ (self, head):
self.head = head
@ -276,20 +320,20 @@ class StdTuplePrinter:
# Set the actual head to the first pair.
self.head = self.head.cast (nodes[0].type)
elif len (nodes) != 0:
raise ValueError, "Top of tuple tree does not consist of a single node."
raise ValueError("Top of tuple tree does not consist of a single node.")
self.count = 0
def __iter__ (self):
return self
def next (self):
def __next__ (self):
nodes = self.head.type.fields ()
# Check for further recursions in the inheritance tree.
if len (nodes) == 0:
raise StopIteration
# Check that this iteration has an expected structure.
if len (nodes) != 2:
raise ValueError, "Cannot parse more than 2 nodes in a tuple tree."
raise ValueError("Cannot parse more than 2 nodes in a tuple tree.")
# - Left node is the next recursion parent.
# - Right node is the actual class contained in the tuple.
@ -341,7 +385,7 @@ class StdStackOrQueuePrinter:
return self.visualizer.display_hint ()
return None
class RbtreeIterator:
class RbtreeIterator(Iterator):
def __init__(self, rbtree):
self.size = rbtree['_M_t']['_M_impl']['_M_node_count']
self.node = rbtree['_M_t']['_M_impl']['_M_header']['_M_left']
@ -353,7 +397,7 @@ class RbtreeIterator:
def __len__(self):
return int (self.size)
def next(self):
def __next__(self):
if self.count == self.size:
raise StopIteration
result = self.node
@ -405,7 +449,7 @@ class StdMapPrinter:
"Print a std::map or std::multimap"
# Turn an RbtreeIterator into a pretty-print iterator.
class _iter:
class _iter(Iterator):
def __init__(self, rbiter, type):
self.rbiter = rbiter
self.count = 0
@ -414,9 +458,9 @@ class StdMapPrinter:
def __iter__(self):
return self
def next(self):
def __next__(self):
if self.count % 2 == 0:
n = self.rbiter.next()
n = next(self.rbiter)
n = n.cast(self.type).dereference()['_M_value_field']
self.pair = n
item = n['first']
@ -447,7 +491,7 @@ class StdSetPrinter:
"Print a std::set or std::multiset"
# Turn an RbtreeIterator into a pretty-print iterator.
class _iter:
class _iter(Iterator):
def __init__(self, rbiter, type):
self.rbiter = rbiter
self.count = 0
@ -456,8 +500,8 @@ class StdSetPrinter:
def __iter__(self):
return self
def next(self):
item = self.rbiter.next()
def __next__(self):
item = next(self.rbiter)
item = item.cast(self.type).dereference()['_M_value_field']
# FIXME: this is weird ... what to do?
# Maybe a 'set' display hint?
@ -522,7 +566,7 @@ class StdBitsetPrinter:
class StdDequePrinter:
"Print a std::deque"
class _iter:
class _iter(Iterator):
def __init__(self, node, start, end, last, buffer_size):
self.node = node
self.p = start
@ -534,7 +578,7 @@ class StdDequePrinter:
def __iter__(self):
return self
def next(self):
def __next__(self):
if self.p == self.last:
raise StopIteration
@ -619,7 +663,7 @@ class StdStringPrinter:
def display_hint (self):
return 'string'
class Tr1HashtableIterator:
class Tr1HashtableIterator(Iterator):
def __init__ (self, hash):
self.node = hash['_M_bbegin']['_M_node']['_M_nxt']
self.node_type = find_type(hash.type, '__node_type').pointer()
@ -627,7 +671,7 @@ class Tr1HashtableIterator:
def __iter__ (self):
return self
def next (self):
def __next__ (self):
if self.node == 0:
raise StopIteration
node = self.node.cast(self.node_type)
@ -655,8 +699,8 @@ class Tr1UnorderedSetPrinter:
return '[%d]' % i
def children (self):
counter = itertools.imap (self.format_count, itertools.count())
return itertools.izip (counter, Tr1HashtableIterator (self.hashtable()))
counter = imap (self.format_count, itertools.count())
return izip (counter, Tr1HashtableIterator (self.hashtable()))
class Tr1UnorderedMapPrinter:
"Print a tr1::unordered_map"
@ -688,11 +732,11 @@ class Tr1UnorderedMapPrinter:
return '[%d]' % i
def children (self):
counter = itertools.imap (self.format_count, itertools.count())
counter = imap (self.format_count, itertools.count())
# Map over the hash table and flatten the result.
data = self.flatten (itertools.imap (self.format_one, Tr1HashtableIterator (self.hashtable())))
data = self.flatten (imap (self.format_one, Tr1HashtableIterator (self.hashtable())))
# Zip the two iterators together.
return itertools.izip (counter, data)
return izip (counter, data)
def display_hint (self):
return 'map'
@ -700,7 +744,7 @@ class Tr1UnorderedMapPrinter:
class StdForwardListPrinter:
"Print a std::forward_list"
class _iterator:
class _iterator(Iterator):
def __init__(self, nodetype, head):
self.nodetype = nodetype
self.base = head['_M_next']
@ -709,7 +753,7 @@ class StdForwardListPrinter:
def __iter__(self):
return self
def next(self):
def __next__(self):
if self.base == 0:
raise StopIteration
elt = self.base.cast(self.nodetype).dereference()
@ -764,7 +808,7 @@ class Printer(object):
# A small sanity check.
# FIXME
if not self.compiled_rx.match(name + '<>'):
raise ValueError, 'libstdc++ programming error: "%s" does not match' % name
raise ValueError('libstdc++ programming error: "%s" does not match' % name)
printer = RxPrinter(name, function)
self.subprinters.append(printer)
self.lookup[name] = printer

11
external/gpl3/gcc/dist/libstdc++-v3/scripts/run_doxygen vendored
View File

@ -193,8 +193,15 @@ fi
if $do_latex; then
cd ${outdir}/${mode}
# Also drop in the header file and style sheet
doxygen -w latex header.tex doxygen.sty
# Grrr, Doxygen 1.8.x changed the -w latex options.
need_footer=`doxygen -h | sed -n -e '/-w latex/s=.*footer.*=true=p'`
# Also drop in the header file (maybe footer file) and style sheet
if $need_footer; then
doxygen -w latex header.tex footer.tex doxygen.sty
else
doxygen -w latex header.tex doxygen.sty
fi
echo ::
echo :: LaTeX pages begin with