Add ram size to struct properties, and pass it to the bus independant part.
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7777f61cbe
commit
cce4838c1f
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@ -1,4 +1,4 @@
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/* $NetBSD: siop_pci_common.c,v 1.2 2000/05/25 10:10:56 bouyer Exp $ */
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/* $NetBSD: siop_pci_common.c,v 1.3 2000/10/23 14:57:23 bouyer Exp $ */
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/*
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* Copyright (c) 2000 Manuel Bouyer.
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@ -57,31 +57,31 @@ const struct siop_product_desc siop_products[] = {
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0x00,
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"Symbios Logic 53c810 (fast scsi)",
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SF_PCI_RL | SF_CHIP_LS,
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4, 8, 3, 250
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4, 8, 3, 250, 0
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},
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{ PCI_PRODUCT_SYMBIOS_810,
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0x10,
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"Symbios Logic 53c810a (fast scsi)",
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SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS,
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4, 8, 3, 250
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4, 8, 3, 250, 0
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},
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{ PCI_PRODUCT_SYMBIOS_815,
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0x00,
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"Symbios Logic 53c815 (fast scsi)",
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SF_PCI_RL | SF_PCI_BOF,
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4, 8, 3, 250
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4, 8, 3, 250, 0
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},
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{ PCI_PRODUCT_SYMBIOS_820,
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0x00,
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"Symbios Logic 53c820 (fast wide scsi)",
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SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE,
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4, 8, 3, 250
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4, 8, 3, 250, 0
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},
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{ PCI_PRODUCT_SYMBIOS_825,
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0x00,
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"Symbios Logic 53c825 (fast wide scsi)",
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SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE,
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4, 8, 3, 250
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4, 8, 3, 250, 0
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},
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{ PCI_PRODUCT_SYMBIOS_825,
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0x10,
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@ -89,7 +89,7 @@ const struct siop_product_desc siop_products[] = {
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_WIDE,
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7, 8, 3, 250
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7, 8, 3, 250, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_860,
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0x00,
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@ -97,7 +97,7 @@ const struct siop_product_desc siop_products[] = {
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_PF | SF_CHIP_LS |
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SF_BUS_ULTRA,
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4, 8, 5, 125
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4, 8, 5, 125, 0
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},
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{ PCI_PRODUCT_SYMBIOS_875,
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0x00,
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@ -105,7 +105,7 @@ const struct siop_product_desc siop_products[] = {
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125
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7, 16, 5, 125, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_875,
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0x02,
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@ -114,7 +114,7 @@ const struct siop_product_desc siop_products[] = {
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125
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7, 16, 5, 125, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_875J,
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0x00,
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@ -123,7 +123,7 @@ const struct siop_product_desc siop_products[] = {
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125
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7, 16, 5, 125, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_885,
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0x00,
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@ -132,7 +132,7 @@ const struct siop_product_desc siop_products[] = {
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125
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7, 16, 5, 125, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_895,
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0x00,
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@ -141,7 +141,7 @@ const struct siop_product_desc siop_products[] = {
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA2 | SF_BUS_WIDE,
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7, 31, 7, 62
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7, 31, 7, 62, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_896,
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0x00,
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@ -150,13 +150,13 @@ const struct siop_product_desc siop_products[] = {
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA2 | SF_BUS_WIDE,
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7, 31, 7, 62
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7, 31, 7, 62, 8192
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},
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{ 0,
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0x00,
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NULL,
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0x00,
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0, 0, 0, 0
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0, 0, 0, 0, 0
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},
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};
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@ -205,6 +205,7 @@ siop_pci_attach_common(sc, pa)
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sc->siop.maxoff = sc->sc_pp->maxoff;
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sc->siop.clock_div = sc->sc_pp->clock_div;
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sc->siop.clock_period = sc->sc_pp->clock_period;
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sc->siop.ram_size = sc->sc_pp->ram_size;
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sc->siop.sc_reset = siop_pci_reset;
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printf(": %s\n", sc->sc_pp->name);
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@ -1,4 +1,4 @@
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/* $NetBSD: siop_pci_common.h,v 1.1 2000/05/15 07:53:18 bouyer Exp $ */
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/* $NetBSD: siop_pci_common.h,v 1.2 2000/10/23 14:57:23 bouyer Exp $ */
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/*
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* Copyright (c) 2000 Manuel Bouyer.
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@ -41,6 +41,7 @@ struct siop_product_desc {
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u_int8_t maxoff; /* maximum supported offset */
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u_int8_t clock_div; /* clock divider to use for async. logic */
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u_int8_t clock_period; /* clock period (ns * 10) */
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int ram_size; /* size of RAM, if appropriate */
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};
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const struct siop_product_desc * siop_lookup_product __P((u_int32_t, int));
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