Remove scsi96 driver.
This commit is contained in:
briggs
parent
a7d76c0112
commit
cca82e59db
@ -1,435 +0,0 @@
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/* $NetBSD: scsi96.c,v 1.21 1996/10/13 03:21:29 christos Exp $ */
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/*
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* Copyright (C) 1994 Allen K. Briggs
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* WARNING! This is a non-working driver at the moment!
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* That means it does not work! Contact Allen Briggs
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* (briggs@mail.vt.edu) for current status of this driver.
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*/
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#include <sys/types.h>
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#include <sys/malloc.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/device.h>
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#include <scsi/scsi_all.h>
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#include <scsi/scsi_debug.h>
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#include <scsi/scsiconf.h>
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#include <machine/scsi96reg.h>
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#include <machine/viareg.h>
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/* Support for the NCR 53C96 SCSI processor--primarily for '040 Macs. */
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#ifndef DDB
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#define Debugger() panic("Should call Debugger here (mac/dev/scsi96.c).")
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#endif
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extern vm_offset_t SCSIBase;
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static volatile unsigned char *ncr53c96base =
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(volatile unsigned char *) 0xF000; /* Offset from IOBase */
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struct ncr53c96_softc {
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struct device sc_dev;
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void *reg_base;
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int adapter_target;
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struct scsi_link sc_link;
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};
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#define WAIT_FOR(reg, val) { \
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int timeo=100000; \
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while (!(reg & val)) { \
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if (!(--timeo)) { \
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printf("scsi96: WAIT_FOR timeout.\n"); \
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goto have_error; \
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} \
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} \
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}
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static void ncr53c96_minphys(struct buf * bp);
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static int ncr53c96_scsi_cmd(struct scsi_xfer * xs);
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static int ncr53c96_show_scsi_cmd(struct scsi_xfer * xs);
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static int ncr53c96_reset_target(int adapter, int target);
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static int ncr53c96_poll(int adapter, int timeout);
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static int ncr53c96_send_cmd(struct scsi_xfer * xs);
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struct scsi_adapter ncr53c96_switch = {
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ncr53c96_scsi_cmd, /* scsi_cmd() */
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ncr53c96_minphys, /* scsi_minphys() */
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0, /* open_target_lu() */
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0, /* close_target_lu() */
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};
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/* This is copied from julian's bt driver */
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/* "so we have a default dev struct for our link struct." */
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struct scsi_device ncr53c96_dev = {
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NULL, /* Use default error handler. */
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NULL, /* have a queue, served by this (?) */
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NULL, /* have no async handler. */
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NULL, /* Use default "done" routine. */
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};
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static int ncr96probe __P((struct device *, void *, void *));
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static void ncr96attach __P((struct device *, struct device *, void *));
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struct cfattach ncr96scsi_ca = {
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sizeof(struct ncr53c96_softc), ncr96probe, ncr96attach
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};
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struct cfdriver ncr96scsi_cd = {
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NULL, "ncr96scsi", DV_DULL, NULL, 0
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};
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static int
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ncr96probe(parent, match, aux)
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struct device *parent;
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void *match;
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void *aux;
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{
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static int probed = 0;
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return 0;
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if (!mac68k_machine.scsi96) {
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return 0;
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}
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if (!probed) {
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probed = 1;
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ncr53c96base += SCSIBase;
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}
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return 1;
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}
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static void
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ncr96attach(parent, dev, aux)
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struct device *parent, *dev;
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void *aux;
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{
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int unit = dev->dv_unit;
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struct ncr53c96_softc *ncr53c96;
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ncr53c96 = (struct ncr53c96_softc *) dev;
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ncr53c96->sc_link.channel = SCSI_CHANNEL_ONLY_ONE;
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ncr53c96->sc_link.scsibus = unit;
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ncr53c96->sc_link.adapter_target = 7;
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ncr53c96->sc_link.adapter = &ncr53c96_switch;
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ncr53c96->sc_link.device = &ncr53c96_dev;
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ncr53c96->sc_link.openings = 1;
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#ifdef SCSIDEBUG
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ncr53c96->sc_link.flags = SDEV_DB1 | SDEV_DB2 /* | SDEV_DB3 | SDEV_DB4 */ ;
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#endif
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printf("\n");
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config_found(dev, &(ncr53c96->sc_link), scsiprint);
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/*
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* Enable IRQ and DRQ interrupts.
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via_reg(VIA2, vIER) = (V2IF_IRQ | V2IF_SCSIDRQ | V2IF_SCSIIRQ);
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*/
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}
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#define MIN_PHYS 65536 /* BARF!!!! */
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static void
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ncr53c96_minphys(struct buf * bp)
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{
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if (bp->b_bcount > MIN_PHYS) {
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printf("Uh-oh... ncr53c96_minphys setting bp->b_bcount "
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"= %x.\n", MIN_PHYS);
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bp->b_bcount = MIN_PHYS;
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}
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minphys(bp);
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}
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#undef MIN_PHYS
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static int
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ncr53c96_scsi_cmd(struct scsi_xfer * xs)
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{
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int flags, s, r;
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flags = xs->flags;
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if (xs->bp)
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flags |= (SCSI_NOSLEEP);
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if (flags & ITSDONE) {
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printf("Already done?");
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xs->flags &= ~ITSDONE;
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}
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if (!(flags & INUSE)) {
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printf("Not in use?");
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xs->flags |= INUSE;
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}
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if (flags & SCSI_RESET) {
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printf("flags & SCSIRESET.\n");
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if (!(flags & SCSI_NOSLEEP)) {
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s = splbio();
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ncr53c96_reset_target(xs->sc_link->scsibus,
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xs->sc_link->target);
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splx(s);
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return (SUCCESSFULLY_QUEUED);
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} else {
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ncr53c96_reset_target(xs->sc_link->scsibus,
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xs->sc_link->target);
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if (ncr53c96_poll(xs->sc_link->scsibus, xs->timeout)) {
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return (COMPLETE);
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}
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return (COMPLETE);
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}
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}
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/*
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* OK. Now that that's over with, let's pack up that
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* SCSI puppy and send it off. If we can, we'll just
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* queue and go; otherwise, we'll wait for the command
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* to finish.
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if ( ! ( flags & SCSI_NOSLEEP ) ) {
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s = splbio();
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ncr53c96_send_cmd(xs);
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splx(s);
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return(SUCCESSFULLY_QUEUED);
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}
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*/
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r = ncr53c96_send_cmd(xs);
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xs->flags |= ITSDONE;
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scsi_done(xs);
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switch (r) {
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case COMPLETE:
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case SUCCESSFULLY_QUEUED:
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r = SUCCESSFULLY_QUEUED;
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if (xs->flags & SCSI_POLL)
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r = COMPLETE;
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break;
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default:
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break;
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}
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return r;
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/*
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do {
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if (ncr53c96_poll(xs->sc_link->scsibus, xs->timeout)) {
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if ( ! ( xs->flags & SCSI_SILENT ) )
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printf("cmd fail.\n");
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cmd_cleanup
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xs->error = XS_DRIVER_STUFFUP;
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splx(s);
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}
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} while ( ! ( xs->flags & ITSDONE ) );
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*/
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}
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static int
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ncr53c96_show_scsi_cmd(struct scsi_xfer * xs)
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{
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u_char *b = (u_char *) xs->cmd;
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int i = 0;
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if (!(xs->flags & SCSI_RESET)) {
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printf("ncr53c96(%d:%d:%d)-",
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xs->sc_link->scsibus, xs->sc_link->target,
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xs->sc_link->lun);
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while (i < xs->cmdlen) {
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if (i)
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printf(",");
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printf("%x", b[i++]);
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}
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printf("-\n");
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} else {
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printf("ncr53c96(%d:%d:%d)-RESET-\n",
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xs->sc_link->scsibus, xs->sc_link->target,
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xs->sc_link->lun);
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}
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return 0;
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}
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/*
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* Actual chip control.
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*/
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extern void ncr53c96_intr __P((int));
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extern void
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ncr53c96_intr(int adapter)
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{
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}
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extern int ncr53c96_irq_intr __P((void));
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extern int
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ncr53c96_irq_intr(void)
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{
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printf("irq\n");
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return 1;
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}
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extern int ncr53c96_drq_intr __P((void));
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extern int
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ncr53c96_drq_intr(void)
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{
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printf("drq\n");
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return 1;
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}
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static int
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ncr53c96_reset_target(int adapter, int target)
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{
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return 0;
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}
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static int
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ncr53c96_poll(int adapter, int timeout)
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{
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return 0;
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}
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static int
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do_send_cmd(struct scsi_xfer * xs)
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{
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struct ncr53c96regs *ncr = (struct ncr53c96regs *) ncr53c96base;
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u_char *cmd;
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int i, stat, is, intr;
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int msg, phase;
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xs->resid = 0;
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i = (int) ncr->statreg; /* clear interrupts */
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ncr->cmdreg = NCR96_CMD_CLRFIFO; /* and fifo */
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cmd = (u_char *) xs->cmd;
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for (i = 0; i < xs->cmdlen; i++)
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ncr->fifo = *cmd++;
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ncr->tcreg_lsb = xs->cmdlen;
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ncr->tcreg_msb = 0;
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ncr->stimreg = 122; /* XXX */
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ncr->sdidreg = xs->sc_link->target;
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/* ncr->ctrlreg1 = 0x47; from the mac -- inherited*/
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ncr->cmdreg = NCR96_CMD_SEL;
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WAIT_FOR(ncr->statreg, NCR96_STAT_INT);
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stat = ncr->statreg;
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is = ncr->isreg;
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intr = ncr->instreg;
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if ((is & 0x07) != 0x4 || intr != 0x18) {
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if ((is & 0x7) != 0x0 || intr != 0x20) {
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printf("scsi96: stat = 0x%x, is = 0x%x, intr = 0x%x\n",
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stat, is, intr);
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}
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goto have_error;
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}
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printf("scsi96: before loop: stat = 0x%x, is = 0x%x, intr = 0x%x, "
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"datalen = %d\n", stat, is, intr, xs->datalen);
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phase = ncr->statreg & NCR96_STAT_PHASE;
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if (((phase == 0x01) || (phase == 0x00)) && xs->datalen) {
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printf("data = %p, datalen = 0x%x.\n", xs->data, xs->datalen);
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stat = ncr->statreg;
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is = ncr->isreg;
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intr = ncr->instreg;
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printf("entering info xfer...stat = 0x%x, is = 0x%x, intr = 0x%x\n",
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stat, is, intr);
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ncr->tcreg_lsb = (xs->datalen & 0xff);
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ncr->tcreg_msb = (xs->datalen >> 8) & 0xff;
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ncr->cmdreg = 0x80 | NCR96_CMD_INFOXFER;
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printf("rem... %d.\n", ncr->tcreg_lsb | (ncr->tcreg_msb << 8));
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i = 0;
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while (i < xs->datalen) {
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int d, stat;
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WAIT_FOR(ncr->statreg, NCR96_STAT_INT);
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stat = ncr->statreg;
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for (d = 1000000; d && !(via_reg(VIA2, vIFR) & 0x01); d--);
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if (d <= 0)
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printf("read timeout.\n");
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d = ncr->fifostatereg & NCR96_CF_MASK;
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while (d--) {
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xs->data[i++] = ncr->fifo;
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printf("0x%x,", xs->data[i - 1]);
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}
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intr = ncr->instreg;
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printf("\nin loop. stat = 0x%x, intr = 0x%x",
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stat, intr);
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printf("rem... %d.\n", ncr->tcreg_lsb | (ncr->tcreg_msb << 8));
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}
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/* } else {
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WAIT_FOR(ncr->statreg, NCR96_STAT_INT); */
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}
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stat = ncr->statreg;
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is = ncr->isreg;
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intr = ncr->instreg;
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printf("past loop...stat = 0x%x, is = 0x%x, intr = 0x%x\n",
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stat, is, intr);
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ncr->cmdreg = NCR96_CMD_ICCS;
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WAIT_FOR(ncr->statreg, NCR96_STAT_INT);
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stat = ncr->statreg;
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is = ncr->isreg;
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intr = ncr->instreg;
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xs->status = ncr->fifo;
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msg = ncr->fifo;
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ncr->cmdreg = NCR96_CMD_MSGACC;
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WAIT_FOR(ncr->statreg, NCR96_STAT_INT);
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stat = ncr->statreg;
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is = ncr->isreg;
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intr = ncr->instreg;
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if (intr == 0x20 && stat == 0x90)
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return COMPLETE;
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have_error:
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xs->error = XS_DRIVER_STUFFUP;
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return COMPLETE;
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}
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static int
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ncr53c96_send_cmd(struct scsi_xfer * xs)
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{
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int r = COMPLETE;
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if (xs->sc_link->target >= 5)
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ncr53c96_show_scsi_cmd(xs);
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switch (xs->cmd->opcode) {
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case 0: /* TUN */
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case 0x12: /* INQUIRY */
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r = do_send_cmd(xs);
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default:
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xs->error = XS_DRIVER_STUFFUP;
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r = COMPLETE;
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}
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return r;
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}
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@ -1,173 +0,0 @@
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/* $NetBSD: scsi96reg.h,v 1.5 1996/05/05 06:18:02 briggs Exp $ */
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/*
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* Copyright (C) 1994 Allen K. Briggs
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SCSI96REG_MACHINE_
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#define _SCSI96REG_MACHINE_
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typedef volatile unsigned char v_uchar;
|
||||
|
||||
#define PAD(x) u_char x [15];
|
||||
struct ncr53c96regs {
|
||||
v_uchar tcreg_lsb; /* r == ctc, w == stc */
|
||||
PAD(pad0);
|
||||
v_uchar tcreg_msb; /* r == ctc, w == stc */
|
||||
PAD(pad1);
|
||||
v_uchar fifo; /* fifo reg */
|
||||
PAD(pad2);
|
||||
v_uchar cmdreg; /* command reg */
|
||||
PAD(pad3);
|
||||
v_uchar statreg; /* status reg */
|
||||
#define sdidreg statreg
|
||||
PAD(pad4);
|
||||
v_uchar instreg; /* interrupt status reg */
|
||||
#define stimreg instreg
|
||||
PAD(pad5);
|
||||
v_uchar isreg; /* internal state reg */
|
||||
PAD(pad6);
|
||||
v_uchar fifostatereg; /* fifo state reg */
|
||||
PAD(pad7);
|
||||
v_uchar ctrlreg1; /* control register 1 */
|
||||
PAD(pad8);
|
||||
v_uchar clkfactorreg; /* clock factor register */
|
||||
PAD(pad9);
|
||||
v_uchar ftmreg; /* forced test mode register */
|
||||
PAD(pad10);
|
||||
v_uchar ctrlreg2; /* control register 2 */
|
||||
PAD(pad11);
|
||||
v_uchar ctrlreg3; /* control register 3 */
|
||||
PAD(pad12);
|
||||
v_uchar unused1; /* unknown */
|
||||
PAD(pad13);
|
||||
v_uchar unused2; /* unknown */
|
||||
PAD(pad14);
|
||||
v_uchar dareg; /* data alignment register */
|
||||
PAD(pad15);
|
||||
};
|
||||
#undef PAD
|
||||
|
||||
#define NCR96_CTCREG 0x0 /* Current transfer count. R */
|
||||
/* 16 bits, LSB first. */
|
||||
#define NCR96_STCREG 0x0 /* Short transfer count. W */
|
||||
/* 16 bits, LSB first. */
|
||||
#define NCR96_FFREG 0x2 /* FIFO register. R/W */
|
||||
|
||||
#define NCR96_CMDREG 0x3 /* Command register. R/W */
|
||||
#define NCR96_DMA 0x80 /* This flag means to use DMA mode. */
|
||||
/* Initiator Commands */
|
||||
#define NCR96_CMD_INFOXFER 0x10 /* Information Transfer. */
|
||||
#define NCR96_CMD_ICCS 0x11 /* Initiator Cmd Complete steps. */
|
||||
#define NCR96_CMD_MSGACC 0x12 /* Message Accepted. */
|
||||
#define NCR96_CMD_TPB 0x18 /* Transfer pad bytes. */
|
||||
#define NCR96_CMD_SETATN 0x1A /* Set ATN */
|
||||
#define NCR96_CMD_RESETATN 0x1B /* Reset ATN */
|
||||
/* Target Commands -- skipped. */
|
||||
/* Idle State Commands. */
|
||||
#define NCR96_CMD_RESEL 0x40 /* Reselect steps */
|
||||
#define NCR96_CMD_SEL 0x41 /* Select without ATN steps */
|
||||
#define NCR96_CMD_SELATN 0x42 /* Select with ATN steps */
|
||||
#define NCR96_CMD_SELATNS 0x43 /* Select with ATN and stop steps */
|
||||
#define NCR96_CMD_ENSEL 0x44 /* Enable selection/reselection */
|
||||
#define NCR96_CMD_DISSEL 0x45 /* Disable selection/reselection */
|
||||
#define NCR96_CMD_SELATN3 0x46 /* Select with ATN3 */
|
||||
/* General Commands. */
|
||||
#define NCR96_CMD_NOOP 0x00 /* No Operation */
|
||||
#define NCR96_CMD_CLRFIFO 0x01 /* Clear FIFO */
|
||||
#define NCR96_CMD_RESETDEV 0x02 /* Reset Device */
|
||||
#define NCR96_CMD_RESETBUS 0x03 /* Reset SCSI Bus */
|
||||
|
||||
#define NCR96_STATREG 0x4 /* Status register. R */
|
||||
#define NCR96_STAT_INT 0x80 /* Interrupt */
|
||||
#define NCR96_STAT_IOE 0x40 /* Illegal Operation Error */
|
||||
#define NCR96_STAT_PE 0x20 /* Parity Error */
|
||||
#define NCR96_STAT_CTZ 0x10 /* Count To Zero */
|
||||
#define NCR96_STAT_GCV 0x08 /* Group Code Valid */
|
||||
#define NCR96_STAT_PHASE 0x07 /* Mask for SCSI Phase */
|
||||
#define NCR96_STAT_MSG 0x04 /* Message */
|
||||
#define NCR96_STAT_CD 0x02 /* Command/Data */
|
||||
#define NCR96_STAT_IO 0x01 /* Input/Output */
|
||||
|
||||
#define NCR96_SDIDREG 0x4 /* SCSI Dest. ID register. W */
|
||||
#define NCR96_SDID_MASK 0x07 /* Mask for Dest. ID */
|
||||
|
||||
#define NCR96_INSTREG 0x5 /* Interrupt status register. R */
|
||||
#define NCR96_ISR_SRST 0x80 /* SCSI Reset */
|
||||
#define NCR96_ISR_INVAL 0x40 /* Invalid Command */
|
||||
#define NCR96_ISR_DISCONN 0x20 /* Disconnected */
|
||||
#define NCR96_ISR_SREQ 0x10 /* Service Request */
|
||||
#define NCR96_ISR_SO 0x08 /* Successful Operation */
|
||||
#define NCR96_ISR_RESEL 0x04 /* Relected */
|
||||
#define NCR96_ISR_SELATN 0x02 /* Selected with ATN */
|
||||
#define NCR96_ISR_SEL 0x01 /* Selected */
|
||||
|
||||
#define NCR96_STIMREG 0x5 /* SCSI Timeout register. W */
|
||||
|
||||
#define NCR96_ISREG 0x6 /* Internal state register. R */
|
||||
#define NCR96_IS_MASK 0x0f /* Mask for non-reserved fields. */
|
||||
|
||||
#define NCR96_STPREG 0x6 /* Synch. Trans. per. register. W */
|
||||
#define NCR96_STP_MASK 0x1f /* Mask for non-reserved fields. */
|
||||
|
||||
#define NCR96_CFISREG 0x7 /* Current FIFO/i.s. register. R */
|
||||
#define NCR96_CF_MASK 0x1f /* Mask for current FIFO count. */
|
||||
|
||||
#define NCR96_SOFREG 0x7 /* Synch. Offset register. W */
|
||||
#define NCR96_SOF_MASK 0x0f /* Mask for non-reserved fields. */
|
||||
|
||||
#define NCR96_CNTLREG1 0x8 /* Control register one. R/W */
|
||||
#define NCR96_C1_ETM 0x80 /* Extended Timing mode */
|
||||
#define NCR96_C1_DISR 0x40 /* Disable interrupt on SCSI Reset */
|
||||
#define NCR96_C1_PTE 0x20 /* Parity Test Enable */
|
||||
#define NCR96_C1_PERE 0x10 /* Parity Error Reporting Enable */
|
||||
#define NCR96_C1_STE 0x08 /* Self Test Enable */
|
||||
#define NCR96_C1_SCSIID_MSK 0x07 /* Chip SCSI ID Mask */
|
||||
|
||||
#define NCR96_CLKFREG 0x9 /* Clock Factor register. W */
|
||||
#define NCR96_CLKF_MASK 0x07 /* Mask for non-reserved fields */
|
||||
|
||||
#define NCR96_FTMREG 0xA /* Forced Test Mode register. W */
|
||||
#define NCR96_FTM_MASK 0x07 /* Mask for non-reserved fields */
|
||||
|
||||
#define NCR96_CNTLREG2 0xB /* Control register two. R/W */
|
||||
#define NCR96_C2_DAE 0x80 /* Data alignment enable */
|
||||
#define NCR96_C2_LSP 0x40 /* Latch SCSI Phase */
|
||||
#define NCR96_C2_SBO 0x20 /* Select Byte Order */
|
||||
#define NCR96_C2_TSDR 0x10 /* Tri-state DMA request */
|
||||
#define NCR96_C2_S2FE 0x08 /* SCSI-2 Features Enable */
|
||||
#define NCR96_C2_ACDPE 0x04 /* Abort on Cmd/Data parity error */
|
||||
#define NCR96_C2_PGRP 0x02 /* Pass through/gen register parity */
|
||||
#define NCR96_C2_PGDP 0x01 /* Pass through/gen data parity */
|
||||
|
||||
#define NCR96_CNTLREG3 0xC /* Control register three. R/W */
|
||||
#define NCR96_C3_LBTM 0x04 /* Last byte transfer mode */
|
||||
#define NCR96_C3_MDM 0x02 /* Modity DMA mode */
|
||||
#define NCR96_C3_BS8 0x01 /* Burst Size 8 */
|
||||
|
||||
#define NCR96_DALREG 0xF /* Data alignment register. W */
|
||||
|
||||
#endif /* _SCSI96REG_MACHINE_ */
|
||||
Loading…
Reference in New Issue
Block a user