Add a driver for NXP PCA954x / PCA984x I2C switch / mux controllers.
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thorpej
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c182aecfbc
commit
cc55c171bf
@ -1,4 +1,4 @@
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# $NetBSD: files.i2c,v 1.113 2020/12/28 20:29:57 thorpej Exp $
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# $NetBSD: files.i2c,v 1.114 2020/12/29 01:47:51 thorpej Exp $
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obsolete defflag opt_i2cbus.h I2C_SCAN
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define i2cbus { }
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@ -370,6 +370,11 @@ device anxedp: edid, videomode, drmkms, drmkms_i2c
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attach anxedp at iic
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file dev/i2c/anxedp.c anxedp
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# NXP PCA954x / PCA984x I2C switch / mux controllers
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device pcaiicmux: i2cbus, i2cmux
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attach pcaiicmux at iic
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file dev/i2c/pcai2cmux.c pcaiicmux
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# NXP PCA9685 16-channel, 12-bit PWM Fm+ LED controller
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device pcapwm: pwm
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attach pcapwm at iic
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354
sys/dev/i2c/pcai2cmux.c
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354
sys/dev/i2c/pcai2cmux.c
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/* $NetBSD: pcai2cmux.c,v 1.1 2020/12/29 01:47:51 thorpej Exp $ */
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/*-
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* Copyright (c) 2020 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pcai2cmux.c,v 1.1 2020/12/29 01:47:51 thorpej Exp $");
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/*
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* Driver for NXP PCA954x / PCA984x I2C switches and multiplexers.
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*
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* There are two flavors of this device:
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*
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* - Multiplexers, which connect the upstream bus to one downstream bus
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* at a time.
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*
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* - Switches, which can connect the upstream bus to one or more downstream
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* busses at a time (which is useful when using an all-call address for
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* a large array of PCA9685 LED controllers, for example).
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*
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* Alas, the device tree bindings don't have anything specifically for
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* switches, so we treat the switch variants as basic multiplexers,
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* only enabling one downstream bus at a time.
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*
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* Note that some versions of these chips also have interrupt mux
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* capability. XXX We do not support this yet.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <dev/fdt/fdtvar.h>
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#include <dev/i2c/i2cmuxvar.h>
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/* There are a maximum of 8 busses supported. */
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#define PCAIICMUX_MAX_BUSSES 8
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struct pcaiicmux_type {
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unsigned int nchannels; /* # of downstream channels */
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uint8_t enable_bit; /* if 0, chip is switch type */
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};
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static const struct pcaiicmux_type mux2_type = {
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.nchannels = 2,
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.enable_bit = __BIT(2),
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};
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static const struct pcaiicmux_type switch2_type = {
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.nchannels = 2,
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.enable_bit = 0,
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};
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static const struct pcaiicmux_type mux4_type = {
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.nchannels = 4,
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.enable_bit = __BIT(2),
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};
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static const struct pcaiicmux_type switch4_type = {
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.nchannels = 4,
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.enable_bit = 0,
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};
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static const struct pcaiicmux_type mux8_type = {
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.nchannels = 8,
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.enable_bit = __BIT(3),
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};
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static const struct pcaiicmux_type switch8_type = {
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.nchannels = 8,
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.enable_bit = 0,
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};
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static const struct device_compatible_entry compat_data[] = {
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/* PCA9540 - 2 channel i2c mux */
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{ .compat = "nxp,pca9540",
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.data = (uintptr_t)&mux2_type },
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/* PCA9542 - 2 channel i2c mux with interrupts */
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{ .compat = "nxp,pca9542",
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.data = (uintptr_t)&mux2_type },
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/* PCA9543 - 2 channel i2c switch with interrupts */
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{ .compat = "nxp,pca9543",
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.data = (uintptr_t)&switch2_type },
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/* PCA9544 - 4 channel i2c mux with interrupts */
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{ .compat = "nxp,pca9544",
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.data = (uintptr_t)&mux4_type },
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/* PCA9545 - 4 channel i2c switch with interrupts */
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{ .compat = "nxp,pca9545",
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.data = (uintptr_t)&switch4_type },
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/* PCA9546 - 4 channel i2c switch */
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{ .compat = "nxp,pca9546",
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.data = (uintptr_t)&switch4_type },
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/* PCA9547 - 8 channel i2c mux */
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{ .compat = "nxp,pca9547",
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.data = (uintptr_t)&mux8_type },
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/* PCA9548 - 8 channel i2c switch */
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{ .compat = "nxp,pca9548",
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.data = (uintptr_t)&switch8_type },
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/* PCA9846 - 4 channel i2c switch */
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{ .compat = "nxp,pca9846",
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.data = (uintptr_t)&switch4_type },
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/* PCA9847 - 8 channel i2c mux */
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{ .compat = "nxp,pca9847",
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.data = (uintptr_t)&mux8_type },
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/* PCA9848 - 8 channel i2c switch */
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{ .compat = "nxp,pca9848",
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.data = (uintptr_t)&switch8_type },
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/* PCA9849 - 4 channel i2c mux */
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{ .compat = "nxp,pca9849",
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.data = (uintptr_t)&mux4_type },
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{ NULL }
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};
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struct pcaiicmux_softc {
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struct iicmux_softc sc_iicmux;
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i2c_addr_t sc_addr;
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int sc_cur_value;
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const struct pcaiicmux_type *sc_type;
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struct fdtbus_gpio_pin *sc_reset_gpio;
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bool sc_idle_disconnect;
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struct pcaiicmux_bus_info {
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uint8_t enable_value;
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} sc_bus_info[PCAIICMUX_MAX_BUSSES];
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};
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static int
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pcaiicmux_write(struct pcaiicmux_softc * const sc, uint8_t const val,
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int const flags)
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{
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if ((int)val == sc->sc_cur_value) {
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return 0;
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}
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sc->sc_cur_value = (int)val;
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int const error =
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iic_smbus_send_byte(sc->sc_iicmux.sc_i2c_parent, sc->sc_addr, val,
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flags & ~I2C_F_SPEED);
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if (error) {
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sc->sc_cur_value = -1;
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}
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return error;
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}
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/*****************************************************************************/
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static void *
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pcaiicmux_get_mux_info(struct iicmux_softc * const iicmux)
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{
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return container_of(iicmux, struct pcaiicmux_softc, sc_iicmux);
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}
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static void *
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pcaiicmux_get_bus_info(struct iicmux_bus * const bus)
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{
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struct iicmux_softc * const iicmux = bus->mux;
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struct pcaiicmux_softc * const sc = iicmux->sc_mux_data;
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bus_addr_t addr;
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int error;
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if (bus->busidx >= sc->sc_type->nchannels) {
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aprint_error_dev(iicmux->sc_dev,
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"device tree error: bus index %d out of range\n",
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bus->busidx);
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return NULL;
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}
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struct pcaiicmux_bus_info * const bus_info =
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&sc->sc_bus_info[bus->busidx];
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error = fdtbus_get_reg(bus->phandle, 0, &addr, NULL);
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if (error) {
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aprint_error_dev(iicmux->sc_dev,
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"unable to get reg property for bus %d\n", bus->busidx);
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return NULL;
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}
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if (addr >= sc->sc_type->nchannels) {
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aprint_error_dev(iicmux->sc_dev,
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"device tree error: reg property %llu out of range\n",
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(unsigned long long)addr);
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return NULL;
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}
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/*
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* If it's a mux type, the enable value is the channel number
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* (from the reg property) OR'd with the enable bit.
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*
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* If it's a switch type, the enable value is 1 << channel number
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* (from the reg property).
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*/
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if (sc->sc_type->enable_bit) {
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bus_info->enable_value =
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(uint8_t)addr | sc->sc_type->enable_bit;
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} else {
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bus_info->enable_value = 1 << addr;
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}
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return bus_info;
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}
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static int
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pcaiicmux_acquire_bus(struct iicmux_bus * const bus, int const flags)
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{
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struct pcaiicmux_softc * const sc = bus->mux->sc_mux_data;
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struct pcaiicmux_bus_info * const bus_info = bus->bus_data;
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return pcaiicmux_write(sc, bus_info->enable_value, flags);
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}
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static void
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pcaiicmux_release_bus(struct iicmux_bus * const bus, int const flags)
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{
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struct pcaiicmux_softc * const sc = bus->mux->sc_mux_data;
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if (sc->sc_idle_disconnect) {
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(void) pcaiicmux_write(sc, 0, flags);
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}
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}
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static const struct iicmux_config pcaiicmux_config = {
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.desc = "PCA954x",
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.get_mux_info = pcaiicmux_get_mux_info,
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.get_bus_info = pcaiicmux_get_bus_info,
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.acquire_bus = pcaiicmux_acquire_bus,
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.release_bus = pcaiicmux_release_bus,
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};
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/*****************************************************************************/
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static const struct pcaiicmux_type *
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pcaiicmux_type_by_compat(const struct i2c_attach_args * const ia)
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{
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const struct pcaiicmux_type *type = NULL;
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const struct device_compatible_entry *dce;
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if (iic_compatible_match(ia, compat_data, &dce))
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type = (void *)dce->data;
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return type;
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}
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static int
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pcaiicmux_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct i2c_attach_args * const ia = aux;
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int match_result;
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if (iic_use_direct_match(ia, cf, compat_data, &match_result)) {
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return match_result;
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}
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/* This device is direct-config only. */
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return 0;
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}
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static void
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pcaiicmux_attach(device_t parent, device_t self, void *aux)
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{
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struct pcaiicmux_softc * const sc = device_private(self);
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struct i2c_attach_args * const ia = aux;
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const int phandle = (int)ia->ia_cookie;
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int error;
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sc->sc_iicmux.sc_dev = self;
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sc->sc_iicmux.sc_phandle = phandle;
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sc->sc_iicmux.sc_config = &pcaiicmux_config;
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sc->sc_iicmux.sc_i2c_parent = ia->ia_tag;
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sc->sc_addr = ia->ia_addr;
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sc->sc_type = pcaiicmux_type_by_compat(ia);
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KASSERT(sc->sc_type != NULL);
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aprint_naive("\n");
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aprint_normal(": PCA954x I2C %s\n",
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sc->sc_type->enable_bit ? "mux" : "switch");
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if (of_hasprop(phandle, "i2c-mux-idle-disconnect")) {
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sc->sc_idle_disconnect = true;
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}
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/* Reset the mux if a reset GPIO is specified. */
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sc->sc_reset_gpio =
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fdtbus_gpio_acquire(phandle, "reset-gpios", GPIO_PIN_OUTPUT);
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if (sc->sc_reset_gpio) {
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fdtbus_gpio_write(sc->sc_reset_gpio, 1);
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delay(10);
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fdtbus_gpio_write(sc->sc_reset_gpio, 0);
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delay(10);
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}
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/* Force the mux into a disconnected state. */
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sc->sc_cur_value = -1;
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error = iic_acquire_bus(ia->ia_tag, 0);
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if (error) {
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aprint_error_dev(self, "failed to acquire I2C bus\n");
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return;
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}
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error = pcaiicmux_write(sc, 0, 0);
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iic_release_bus(ia->ia_tag, 0);
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if (error) {
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aprint_error_dev(self,
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"failed to set mux to disconnected state\n");
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return;
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}
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iicmux_attach(&sc->sc_iicmux);
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}
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CFATTACH_DECL_NEW(pcaiicmux, sizeof(struct pcaiicmux_softc),
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pcaiicmux_match, pcaiicmux_attach, NULL, NULL);
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