PCI I/O address fixup routine.
When BIOS don't asign PCI I/O address space to device,
allocate it without conflict and write to PCI configuration header.
This commit is contained in:
uch
parent
e3c3882828
commit
cc30f00dd3
372
sys/arch/i386/pci/pci_addr_fixup.c
Normal file
372
sys/arch/i386/pci/pci_addr_fixup.c
Normal file
@ -0,0 +1,372 @@
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/* $NetBSD: pci_addr_fixup.c,v 1.1 2000/04/28 17:19:10 uch Exp $ */
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/*-
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* Copyright (c) 2000 UCHIYAMA Yasushi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_pcibios.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <i386/pci/pcibios.h>
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#include <i386/pci/pci_addr_fixup.h>
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#ifdef PCIBIOSVERBOSE
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int pcibiosverbose = 1;
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#define DPRINTF(arg) if (pcibiosverbose) printf arg;
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#define DPRINTFN(n, arg) if (pcibiosverbose > (n)) printf arg;
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#else
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#define DPRINTF(arg)
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#define DPRINTFN(n, arg)
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#endif
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struct pciaddr {
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struct extent *extent_mem;
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struct extent *extent_port;
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bus_addr_t mem_alloc_start;
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bus_addr_t port_alloc_start;
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int nbogus;
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} pciaddr;
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typedef int (*pciaddr_resource_manage_func_t)
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(pci_chipset_tag_t, pcitag_t, int, struct extent *, int,
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bus_addr_t *, bus_size_t);
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void pciaddr_resource_manage __P((pci_chipset_tag_t, pcitag_t,
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pciaddr_resource_manage_func_t));
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void pciaddr_resource_reserve __P((pci_chipset_tag_t, pcitag_t));
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int pciaddr_do_resource_reserve __P((pci_chipset_tag_t, pcitag_t, int,
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struct extent *, int, bus_addr_t *,
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bus_size_t));
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void pciaddr_resource_allocate __P((pci_chipset_tag_t, pcitag_t));
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int pciaddr_do_resource_allocate __P((pci_chipset_tag_t, pcitag_t, int,
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struct extent *, int, bus_addr_t *,
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bus_size_t));
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bus_addr_t pciaddr_ioaddr __P((u_int32_t));
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void pciaddr_print_devid __P((pci_chipset_tag_t, pcitag_t));
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#define PCIADDR_MEM_START 0x0
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#define PCIADDR_MEM_END 0xffffffff
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#define PCIADDR_PORT_START 0x0
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#define PCIADDR_PORT_END 0xffff
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/* for ISA devices */
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#define PCIADDR_ISAPORT_RESERVE 0x5800 /* empirical value */
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#define PCIADDR_ISAMEM_RESERVE (16 * 1024 * 1024)
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void
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pci_addr_fixup(pc, bus)
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pci_chipset_tag_t pc;
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int bus;
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{
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extern paddr_t avail_end;
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#ifdef PCIBIOSVERBOSE
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const char *verbose_header =
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"[%s]-----------------------\n"
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" device vendor product\n"
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" register space address size mask\n"
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"--------------------------------------------\n";
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const char *verbose_footer =
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"--------------------------[%3d devices bogus]\n";
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#endif
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const struct {
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bus_addr_t start;
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bus_size_t size;
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char *name;
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} system_reserve [] = {
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{ 0xfec00000, 0x100000, "I/O APIC" },
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{ 0xfee00000, 0x100000, "Local APIC" },
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{ 0xfffe0000, 0x20000, "BIOS PROM" },
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{ 0, 0, 0 }, /* terminator */
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}, *srp;
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paddr_t start;
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int error;
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pciaddr.extent_mem = extent_create("PCI I/O memory addresses",
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PCIADDR_MEM_START,
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PCIADDR_MEM_END,
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M_DEVBUF, 0, 0, EX_NOWAIT);
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KASSERT(pciaddr.extent_mem);
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pciaddr.extent_port = extent_create("PCI I/O port addresses",
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PCIADDR_PORT_START,
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PCIADDR_PORT_END,
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M_DEVBUF, 0, 0, EX_NOWAIT);
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KASSERT(pciaddr.extent_port);
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/*
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* 1. check & reserve system BIOS setting.
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*/
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DPRINTF((verbose_header, "System BIOS Setting"));
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pci_device_foreach(pc, bus, pciaddr_resource_reserve);
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DPRINTF((verbose_footer, pciaddr.nbogus));
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/*
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* 2. reserve non-PCI area.
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*/
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for (srp = system_reserve; srp->size; srp++) {
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error = extent_alloc_region(pciaddr.extent_mem, srp->start,
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srp->size,
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EX_NOWAIT| EX_MALLOCOK);
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if (error != 0) {
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printf("WARNING: can't reserve area for %s.\n",
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srp->name);
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}
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}
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/*
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* 3. determine allocation space
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*/
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start = i386_round_page(avail_end + 1);
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if (start < PCIADDR_ISAMEM_RESERVE)
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start = PCIADDR_ISAMEM_RESERVE;
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pciaddr.mem_alloc_start = (start + 0x100000 + 1) & ~(0x100000 - 1);
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pciaddr.port_alloc_start = PCIADDR_ISAPORT_RESERVE;
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DPRINTF((" Physical memory end: 0x%08x\n PCI memory mapped I/O "
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"space start: 0x%08x\n", (unsigned)avail_end,
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(unsigned)pciaddr.mem_alloc_start));
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/*
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* 4. do fixup
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*/
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DPRINTF((verbose_header, "PCIBIOS fixup stage"));
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pciaddr.nbogus = 0;
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pci_device_foreach(pc, bus, pciaddr_resource_allocate);
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DPRINTF((verbose_footer, pciaddr.nbogus));
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extent_destroy(pciaddr.extent_mem);
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extent_destroy(pciaddr.extent_port);
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}
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void
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pciaddr_resource_reserve(pc, tag)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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{
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#ifdef PCIBIOSVERBOSE
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pciaddr_print_devid(pc, tag);
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#endif
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pciaddr_resource_manage(pc, tag, pciaddr_do_resource_reserve);
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}
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void
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pciaddr_resource_allocate(pc, tag)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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{
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#ifdef PCIBIOSVERBOSE
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pciaddr_print_devid(pc, tag);
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#endif
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pciaddr_resource_manage(pc, tag, pciaddr_do_resource_allocate);
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}
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void
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pciaddr_resource_manage(pc, tag, func)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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pciaddr_resource_manage_func_t func;
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{
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struct extent *ex;
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pcireg_t val, mask, mask2;
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bus_addr_t addr;
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bus_size_t size;
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int error, useport, usemem, mapreg, type, reg_start, reg_end;
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val = pci_conf_read(pc, tag, PCI_BHLC_REG);
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switch (PCI_HDRTYPE_TYPE(val)) {
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default:
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printf("WARNING: unknown PCI device header.");
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pciaddr.nbogus++;
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return;
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case 0:
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reg_start = PCI_MAPREG_START;
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reg_end = PCI_MAPREG_END;
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break;
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case 1: /* PCI-PCI bridge */
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reg_start = PCI_MAPREG_START;
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reg_end = PCI_MAPREG_PPB_END;
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break;
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case 2: /* PCI-CardBus bridge */
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reg_start = PCI_MAPREG_START;
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reg_end = PCI_MAPREG_PCB_END;
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break;
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}
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error = useport = usemem = 0;
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for (mapreg = reg_start; mapreg < reg_end; mapreg += 4) {
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/* inquire PCI device bus space requirement */
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val = pci_conf_read(pc, tag, mapreg);
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pci_conf_write(pc, tag, mapreg, ~0);
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mask = pci_conf_read(pc, tag, mapreg);
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pci_conf_write(pc, tag, mapreg, 0);
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mask2 = pci_conf_read(pc, tag, mapreg);
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pci_conf_write(pc, tag, mapreg, val);
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type = PCI_MAPREG_TYPE(val);
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if (type == PCI_MAPREG_TYPE_MEM) {
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size = PCI_MAPREG_MEM_SIZE(mask);
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ex = pciaddr.extent_mem;
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} else {
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size = PCI_MAPREG_IO_SIZE(mask);
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ex = pciaddr.extent_port;
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}
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addr = pciaddr_ioaddr(val);
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if (!size) /* unused register */
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continue;
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if (type == PCI_MAPREG_TYPE_MEM)
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++usemem;
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else
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++useport;
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/* reservation/allocation phase */
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error += (*func) (pc, tag, mapreg, ex, type, &addr, size);
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DPRINTF(("\n\t%02xh %s 0x%08x 0x%08x %x",
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mapreg, type ? "port" : "mem ",
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(unsigned int)addr, (unsigned int)size, mask2));
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}
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/* enable/disable PCI device */
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val = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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if (error == 0)
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val |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
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PCI_COMMAND_MASTER_ENABLE);
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else
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val &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
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PCI_COMMAND_MASTER_ENABLE);
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pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, val);
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if (error)
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pciaddr.nbogus++;
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DPRINTF(("\n\t\t[%s]\n", error ? "NG" : "OK"));
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}
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int
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pciaddr_do_resource_allocate(pc, tag, mapreg, ex, type, addr, size)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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struct extent *ex;
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int mapreg, type;
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bus_addr_t *addr;
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bus_size_t size;
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{
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bus_addr_t start;
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int error;
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if (*addr) /* no need to allocate */
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return (0);
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start = type == PCI_MAPREG_TYPE_MEM ? pciaddr.mem_alloc_start
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: pciaddr.port_alloc_start;
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if (start < ex->ex_start || start + size >= ex->ex_end) {
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DPRINTF(("No available resources. fixup failed\n"));
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return (1);
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}
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error = extent_alloc_subregion(ex, start, start + size, size, size,
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0, EX_FAST|EX_NOWAIT|EX_MALLOCOK,
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addr);
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if (error) {
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DPRINTF(("No available resources. fixup failed\n"));
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return (1);
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}
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/* write new address to PCI device configuration header */
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pci_conf_write(pc, tag, mapreg, *addr);
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/* check */
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#ifndef PCIBIOSVERBOSE
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printf("pci_addr_fixup: ");
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pciaddr_print_devid(pc, tag);
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#endif
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if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) {
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pci_conf_write(pc, tag, mapreg, 0); /* clear */
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printf("fixup failed. (new address=%#x)\n", (unsigned)*addr);
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return (1);
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}
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#ifndef PCIBIOSVERBOSE
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printf("new address 0x%08x\n", (unsigned)*addr);
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#endif
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return (0);
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}
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int
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pciaddr_do_resource_reserve(pc, tag, mapreg, ex, type, addr, size)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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struct extent *ex;
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int type, mapreg;
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bus_addr_t *addr;
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bus_size_t size;
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{
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int error;
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if (*addr == 0)
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return (1);
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error = extent_alloc_region(ex, *addr, size, EX_NOWAIT| EX_MALLOCOK);
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if (error) {
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DPRINTF(("Resource conflict.\n"));
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pci_conf_write(pc, tag, mapreg, 0); /* clear */
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return (1);
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}
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return (0);
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}
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bus_addr_t
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pciaddr_ioaddr(val)
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u_int32_t val;
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{
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return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM)
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? PCI_MAPREG_MEM_ADDR(val)
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: PCI_MAPREG_IO_ADDR(val));
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}
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void
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pciaddr_print_devid(pc, tag)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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{
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int bus, device, function;
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pcireg_t id;
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id = pci_conf_read(pc, tag, PCI_ID_REG);
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pci_decompose_tag(pc, tag, &bus, &device, &function);
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printf("%03d:%02d:%d 0x%04x 0x%04x ", bus, device, function,
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PCI_VENDOR(id), PCI_PRODUCT(id));
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}
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29
sys/arch/i386/pci/pci_addr_fixup.h
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29
sys/arch/i386/pci/pci_addr_fixup.h
Normal file
@ -0,0 +1,29 @@
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/* $NetBSD: pci_addr_fixup.h,v 1.1 2000/04/28 17:19:10 uch Exp $ */
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/*-
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* Copyright (c) 2000 UCHIYAMA Yasushi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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void pci_addr_fixup __P((pci_chipset_tag_t, int));
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