implement 8bpp CLUT of Plum2, TX3912 video module.
This commit is contained in:
uch
parent
e5ee37ffd9
commit
cc01cd2448
|
|
@ -2,7 +2,7 @@
|
|||
# Distribution kernel (TOSHIBA TX3912 based model) kernel config file
|
||||
|
||||
#
|
||||
# $NetBSD: TX3912,v 1.20 2000/05/04 10:25:45 takemura Exp $
|
||||
# $NetBSD: TX3912,v 1.21 2000/05/08 21:57:59 uch Exp $
|
||||
#
|
||||
include "arch/hpcmips/conf/std.hpcmips"
|
||||
|
||||
|
|
@ -165,6 +165,8 @@ btnmgr0 at mainbus0
|
|||
wskbd* at btnmgr0 mux 1
|
||||
|
||||
options WSEMUL_VT100
|
||||
options WS_KERNEL_FG=WSCOL_BROWN
|
||||
options WS_KERNEL_BG=WSCOL_BLUE
|
||||
options WSDISPLAY_DEFAULTSCREENS=4
|
||||
options FONT_VT220L8x10
|
||||
# compatibility to other console drivers
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Distribution kernel (TOSHIBA TX3922 based model) kernel config file
|
||||
#
|
||||
# $NetBSD: TX3922,v 1.20 2000/05/08 13:49:47 augustss Exp $
|
||||
# $NetBSD: TX3922,v 1.21 2000/05/08 21:57:59 uch Exp $
|
||||
#
|
||||
include "arch/hpcmips/conf/std.hpcmips"
|
||||
|
||||
|
|
@ -227,6 +227,8 @@ wskbd* at btnmgr0 mux 1
|
|||
options WSEMUL_VT100
|
||||
options WSDISPLAY_DEFAULTSCREENS=4
|
||||
options FONT_VT220L8x10
|
||||
options WS_KERNEL_FG=WSCOL_BROWN
|
||||
options WS_KERNEL_BG=WSCOL_BLUE
|
||||
# compatibility to other console drivers
|
||||
options WSDISPLAY_COMPAT_PCVT # emulate some ioctls
|
||||
options WSDISPLAY_COMPAT_SYSCONS # emulate some ioctls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: files.hpcmips,v 1.31 2000/05/04 08:18:59 takemura Exp $
|
||||
# $NetBSD: files.hpcmips,v 1.32 2000/05/08 21:57:59 uch Exp $
|
||||
|
||||
# maxpartitions must be first item in files.${ARCH}.
|
||||
maxpartitions 8
|
||||
|
|
@ -87,6 +87,8 @@ device btnmgr: wskbddev
|
|||
attach btnmgr at mainbus
|
||||
file arch/hpcmips/dev/btnmgr.c btnmgr
|
||||
|
||||
file arch/hpcmips/dev/video_subr.c tx3912video | plumvideo
|
||||
|
||||
#
|
||||
# ISA bus support
|
||||
#
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: plumvideo.c,v 1.7 2000/05/02 17:50:51 uch Exp $ */
|
||||
/* $NetBSD: plumvideo.c,v 1.8 2000/05/08 21:57:56 uch Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved.
|
||||
|
|
@ -32,6 +32,10 @@
|
|||
#include <sys/systm.h>
|
||||
#include <sys/device.h>
|
||||
|
||||
#include <sys/ioctl.h>
|
||||
#include <sys/buf.h>
|
||||
#include <vm/vm.h>
|
||||
|
||||
#include <dev/cons.h> /* consdev */
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
|
@ -45,10 +49,15 @@
|
|||
|
||||
#include <machine/bootinfo.h>
|
||||
|
||||
#include <dev/wscons/wsdisplayvar.h>
|
||||
#include <dev/rasops/rasops.h>
|
||||
#include <arch/hpcmips/dev/video_subr.h>
|
||||
|
||||
#include <dev/wscons/wsconsio.h>
|
||||
#include <arch/hpcmips/dev/hpcfbvar.h>
|
||||
#include <arch/hpcmips/dev/hpcfbio.h>
|
||||
|
||||
|
||||
#ifdef PLUMVIDEODEBUG
|
||||
int plumvideo_debug = 1;
|
||||
#define DPRINTF(arg) if (plumvideo_debug) printf arg;
|
||||
|
|
@ -58,26 +67,34 @@ int plumvideo_debug = 1;
|
|||
#define DPRINTFN(n, arg)
|
||||
#endif
|
||||
|
||||
int plumvideo_match __P((struct device*, struct cfdata*, void*));
|
||||
void plumvideo_attach __P((struct device*, struct device*, void*));
|
||||
|
||||
struct plumvideo_softc {
|
||||
struct device sc_dev;
|
||||
|
||||
plum_chipset_tag_t sc_pc;
|
||||
/* control register */
|
||||
bus_space_tag_t sc_regt;
|
||||
bus_space_handle_t sc_regh;
|
||||
bus_space_tag_t sc_iot;
|
||||
bus_space_handle_t sc_ioh;
|
||||
/* frame buffer */
|
||||
bus_space_tag_t sc_fbiot;
|
||||
bus_space_handle_t sc_fbioh;
|
||||
/* clut buffer (8bpp only) */
|
||||
bus_space_tag_t sc_clutiot;
|
||||
bus_space_handle_t sc_clutioh;
|
||||
/* bitblt */
|
||||
bus_space_tag_t sc_bitbltt;
|
||||
bus_space_handle_t sc_bitblth;
|
||||
|
||||
int sc_width;
|
||||
int sc_height;
|
||||
int sc_depth;
|
||||
|
||||
struct hpcfb_fbconf sc_fbconf;
|
||||
struct hpcfb_dspconf sc_dspconf;
|
||||
struct hpcfb_fbconf sc_fbconf;
|
||||
struct hpcfb_dspconf sc_dspconf;
|
||||
};
|
||||
|
||||
void plumvideo_hpcfbinit __P((struct plumvideo_softc *));
|
||||
int plumvideo_match __P((struct device*, struct cfdata*, void*));
|
||||
void plumvideo_attach __P((struct device*, struct device*, void*));
|
||||
|
||||
int plumvideo_ioctl __P((void *, u_long, caddr_t, int, struct proc *));
|
||||
int plumvideo_mmap __P((void *, off_t, int));
|
||||
|
||||
|
|
@ -90,6 +107,18 @@ struct hpcfb_accessops plumvideo_ha = {
|
|||
};
|
||||
|
||||
int plumvideo_init __P((struct plumvideo_softc*));
|
||||
void plumvideo_hpcfbinit __P((struct plumvideo_softc *));
|
||||
|
||||
void plumvideo_clut_default __P((struct plumvideo_softc *));
|
||||
void plumvideo_clut_set __P((struct plumvideo_softc *, u_int32_t *, int,
|
||||
int));
|
||||
void plumvideo_clut_get __P((struct plumvideo_softc *, u_int32_t *, int,
|
||||
int));
|
||||
void __plumvideo_clut_access __P((struct plumvideo_softc *,
|
||||
void (*) __P((bus_space_tag_t,
|
||||
bus_space_handle_t))));
|
||||
static void _flush_cache __P((void)) __attribute__((__unused__)); /* !!! */
|
||||
|
||||
#ifdef PLUMVIDEODEBUG
|
||||
void plumvideo_dump __P((struct plumvideo_softc*));
|
||||
#endif
|
||||
|
|
@ -103,7 +132,7 @@ plumvideo_match(parent, cf, aux)
|
|||
/*
|
||||
* VRAM area also uses as UHOSTC shared RAM.
|
||||
*/
|
||||
return 2; /* 1st attach group */
|
||||
return (2); /* 1st attach group */
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -119,7 +148,7 @@ plumvideo_attach(parent, self, aux)
|
|||
|
||||
sc->sc_pc = pa->pa_pc;
|
||||
sc->sc_regt = pa->pa_regt;
|
||||
sc->sc_iot = pa->pa_iot;
|
||||
sc->sc_fbiot = sc->sc_clutiot = sc->sc_bitbltt = pa->pa_iot;
|
||||
|
||||
printf(": ");
|
||||
/*
|
||||
|
|
@ -200,21 +229,21 @@ plumvideo_hpcfbinit(sc)
|
|||
struct plumvideo_softc *sc;
|
||||
{
|
||||
struct hpcfb_fbconf *fb = &sc->sc_fbconf;
|
||||
vaddr_t fbvaddr = (vaddr_t)sc->sc_ioh;
|
||||
vaddr_t fbvaddr = (vaddr_t)sc->sc_fbioh;
|
||||
|
||||
memset(fb, 0, sizeof(struct hpcfb_fbconf));
|
||||
|
||||
fb->hf_conf_index = 0; /* configuration index */
|
||||
fb->hf_nconfs = 1; /* how many configurations */
|
||||
strcpy(fb->hf_name, "PLUM built-in video");
|
||||
/* frame buffer name */
|
||||
strcpy(fb->hf_conf_name, "LCD");
|
||||
/* configuration name */
|
||||
strncpy(fb->hf_name, "PLUM built-in video", HPCFB_MAXNAMELEN);
|
||||
/* frame buffer name */
|
||||
strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN);
|
||||
/* configuration name */
|
||||
fb->hf_height = sc->sc_height;
|
||||
fb->hf_width = sc->sc_width;
|
||||
fb->hf_baseaddr = mips_ptob(mips_btop(fbvaddr));
|
||||
fb->hf_offset = (u_long)fbvaddr - fb->hf_baseaddr;
|
||||
/* frame buffer start offset */
|
||||
/* frame buffer start offset */
|
||||
fb->hf_bytes_per_line = (sc->sc_width * sc->sc_depth) / NBBY;
|
||||
fb->hf_nplanes = 1;
|
||||
fb->hf_bytes_per_plane = sc->sc_height * fb->hf_bytes_per_line;
|
||||
|
|
@ -236,7 +265,8 @@ plumvideo_hpcfbinit(sc)
|
|||
fb->hf_pixel_width = 16;
|
||||
|
||||
fb->hf_class_data_length = sizeof(struct hf_rgb_tag);
|
||||
fb->hf_u.hf_rgb.hf_flags = 0; /* reserved for future use */
|
||||
/* reserved for future use */
|
||||
fb->hf_u.hf_rgb.hf_flags = 0;
|
||||
|
||||
fb->hf_u.hf_rgb.hf_red_width = 5;
|
||||
fb->hf_u.hf_rgb.hf_red_shift = 11;
|
||||
|
|
@ -255,7 +285,8 @@ plumvideo_hpcfbinit(sc)
|
|||
fb->hf_pixels_per_pack = 1;
|
||||
fb->hf_pixel_width = 8;
|
||||
fb->hf_class_data_length = sizeof(struct hf_indexed_tag);
|
||||
fb->hf_u.hf_indexed.hf_flags = 0; /* reserved for future use */
|
||||
/* reserved for future use */
|
||||
fb->hf_u.hf_indexed.hf_flags = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -269,9 +300,18 @@ plumvideo_init(sc)
|
|||
plumreg_t reg;
|
||||
size_t vram_size;
|
||||
int bpp, vram_pitch;
|
||||
|
||||
#if notyet
|
||||
/* map BitBlt area */
|
||||
if (bus_space_map(sc->sc_bitbltt,
|
||||
PLUM_VIDEO_BITBLT_IOBASE,
|
||||
PLUM_VIDEO_BITBLT_IOSIZE, 0,
|
||||
&sc->sc_bitblth)) {
|
||||
printf(": BitBlt map failed\n");
|
||||
return (1);
|
||||
}
|
||||
#endif
|
||||
reg = plum_conf_read(regt, regh, PLUM_VIDEO_PLGMD_REG);
|
||||
switch (reg & PLUM_VIDEO_PLGMD_MASK) {
|
||||
switch (reg & PLUM_VIDEO_PLGMD_GMODE_MASK) {
|
||||
case PLUM_VIDEO_PLGMD_16BPP:
|
||||
#ifdef PLUM_BIG_OHCI_BUFFER
|
||||
printf("(16bpp disabled) ");
|
||||
|
|
@ -282,9 +322,14 @@ plumvideo_init(sc)
|
|||
#endif /* PLUM_BIG_OHCI_BUFFER */
|
||||
default:
|
||||
bootinfo->fb_type = BIFB_D8_FF; /* over ride */
|
||||
reg &= ~PLUM_VIDEO_PLGMD_MASK;
|
||||
reg &= ~PLUM_VIDEO_PLGMD_GMODE_MASK;
|
||||
plum_conf_write(regt, regh, PLUM_VIDEO_PLGMD_REG, reg);
|
||||
reg |= PLUM_VIDEO_PLGMD_8BPP;
|
||||
plum_conf_write(regt, regh, PLUM_VIDEO_PLGMD_REG, reg);
|
||||
#if notyet
|
||||
/* change BitBlt color depth */
|
||||
plum_conf_write(sc->sc_bitbltt, sc->sc_bitblth, 0x8, 0);
|
||||
#endif
|
||||
/* FALLTHROUGH */
|
||||
case PLUM_VIDEO_PLGMD_8BPP:
|
||||
bpp = 8;
|
||||
|
|
@ -297,27 +342,36 @@ plumvideo_init(sc)
|
|||
/*
|
||||
* set line byte length to bootinfo and LCD controller.
|
||||
*/
|
||||
bootinfo->fb_line_bytes = (bootinfo->fb_width * bpp) / 8;
|
||||
bootinfo->fb_line_bytes = (sc->sc_width * bpp) / NBBY;
|
||||
|
||||
vram_pitch = bootinfo->fb_width / (8 / bpp);
|
||||
vram_pitch = sc->sc_width / (8 / bpp);
|
||||
plum_conf_write(regt, regh, PLUM_VIDEO_PLPIT1_REG, vram_pitch);
|
||||
plum_conf_write(regt, regh, PLUM_VIDEO_PLPIT2_REG,
|
||||
vram_pitch & PLUM_VIDEO_PLPIT2_MASK);
|
||||
plum_conf_write(regt, regh, PLUM_VIDEO_PLOFS_REG, vram_pitch);
|
||||
|
||||
/*
|
||||
* boot messages.
|
||||
* boot messages and map CLUT(if any).
|
||||
*/
|
||||
printf("display mode: ");
|
||||
reg = plum_conf_read(regt, regh, PLUM_VIDEO_PLGMD_REG);
|
||||
switch (reg & PLUM_VIDEO_PLGMD_MASK) {
|
||||
case PLUM_VIDEO_PLGMD_DISABLE:
|
||||
switch (bpp) {
|
||||
default:
|
||||
printf("disabled ");
|
||||
break;
|
||||
case PLUM_VIDEO_PLGMD_8BPP:
|
||||
case 8:
|
||||
printf("8bpp ");
|
||||
/* map CLUT area */
|
||||
if (bus_space_map(sc->sc_clutiot,
|
||||
PLUM_VIDEO_CLUT_LCD_IOBASE,
|
||||
PLUM_VIDEO_CLUT_LCD_IOSIZE, 0,
|
||||
&sc->sc_clutioh)) {
|
||||
printf(": CLUT map failed\n");
|
||||
return (1);
|
||||
}
|
||||
/* install default CLUT */
|
||||
plumvideo_clut_default(sc);
|
||||
break;
|
||||
case PLUM_VIDEO_PLGMD_16BPP:
|
||||
case 16:
|
||||
printf("16bpp ");
|
||||
break;
|
||||
}
|
||||
|
|
@ -326,21 +380,19 @@ plumvideo_init(sc)
|
|||
* calcurate frame buffer size.
|
||||
*/
|
||||
reg = plum_conf_read(regt, regh, PLUM_VIDEO_PLGMD_REG);
|
||||
vram_size = (bootinfo->fb_width * bootinfo->fb_height *
|
||||
(((reg & PLUM_VIDEO_PLGMD_MASK) == PLUM_VIDEO_PLGMD_16BPP)
|
||||
? 16 : 8)) / 8;
|
||||
vram_size = (sc->sc_width * sc->sc_height * bpp) / NBBY;
|
||||
vram_size = mips_round_page(vram_size);
|
||||
|
||||
/*
|
||||
* map V-RAM area.
|
||||
*/
|
||||
if (bus_space_map(sc->sc_iot, PLUM_VIDEO_VRAM_IOBASE,
|
||||
vram_size, 0, &sc->sc_ioh)) {
|
||||
if (bus_space_map(sc->sc_fbiot, PLUM_VIDEO_VRAM_IOBASE,
|
||||
vram_size, 0, &sc->sc_fbioh)) {
|
||||
printf(": V-RAM map failed\n");
|
||||
return (1);
|
||||
}
|
||||
|
||||
bootinfo->fb_addr = (unsigned char *)sc->sc_ioh;
|
||||
bootinfo->fb_addr = (unsigned char *)sc->sc_fbioh;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -356,14 +408,74 @@ plumvideo_ioctl(v, cmd, data, flag, p)
|
|||
struct plumvideo_softc *sc = (struct plumvideo_softc *)v;
|
||||
struct hpcfb_fbconf *fbconf;
|
||||
struct hpcfb_dspconf *dspconf;
|
||||
struct wsdisplay_cmap *cmap;
|
||||
u_int8_t *r, *g, *b;
|
||||
u_int32_t *rgb;
|
||||
int idx, cnt, error;
|
||||
|
||||
switch (cmd) {
|
||||
case WSDISPLAYIO_GETCMAP:
|
||||
/* XXX not implemented yet */
|
||||
return (EINVAL);
|
||||
cmap = (struct wsdisplay_cmap*)data;
|
||||
cnt = cmap->count;
|
||||
idx = cmap->index;
|
||||
|
||||
if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR ||
|
||||
sc->sc_fbconf.hf_pack_width != 8 ||
|
||||
!LEGAL_CLUT_INDEX(idx) ||
|
||||
!LEGAL_CLUT_INDEX(idx + cnt -1)) {
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (!uvm_useracc(cmap->red, cnt, B_WRITE) ||
|
||||
!uvm_useracc(cmap->green, cnt, B_WRITE) ||
|
||||
!uvm_useracc(cmap->blue, cnt, B_WRITE)) {
|
||||
return (EFAULT);
|
||||
}
|
||||
|
||||
error = cmap_work_alloc(&r, &g, &b, &rgb, cnt);
|
||||
if (error != 0) {
|
||||
cmap_work_free(r, g, b, rgb);
|
||||
return (ENOMEM);
|
||||
}
|
||||
plumvideo_clut_get(sc, rgb, idx, cnt);
|
||||
rgb24_decompose(rgb, r, g, b, cnt);
|
||||
|
||||
copyout(r, cmap->red, cnt);
|
||||
copyout(g, cmap->green,cnt);
|
||||
copyout(b, cmap->blue, cnt);
|
||||
|
||||
cmap_work_free(r, g, b, rgb);
|
||||
|
||||
return (0);
|
||||
|
||||
case WSDISPLAYIO_PUTCMAP:
|
||||
/* XXX not implemented yet */
|
||||
cmap = (struct wsdisplay_cmap*)data;
|
||||
cnt = cmap->count;
|
||||
idx = cmap->index;
|
||||
|
||||
if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR ||
|
||||
sc->sc_fbconf.hf_pack_width != 8 ||
|
||||
!LEGAL_CLUT_INDEX(idx) ||
|
||||
!LEGAL_CLUT_INDEX(idx + cnt -1)) {
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (!uvm_useracc(cmap->red, cnt, B_WRITE) ||
|
||||
!uvm_useracc(cmap->green, cnt, B_WRITE) ||
|
||||
!uvm_useracc(cmap->blue, cnt, B_WRITE)) {
|
||||
return (EFAULT);
|
||||
}
|
||||
|
||||
error = cmap_work_alloc(&r, &g, &b, &rgb, cnt);
|
||||
if (error != 0) {
|
||||
cmap_work_free(r, g, b, rgb);
|
||||
return (ENOMEM);
|
||||
}
|
||||
rgb24_compose(rgb, r, g, b, cnt);
|
||||
plumvideo_clut_set(sc, rgb, idx, cnt);
|
||||
|
||||
cmap_work_free(r, g, b, rgb);
|
||||
|
||||
return (EINVAL);
|
||||
|
||||
case HPCFBIO_GCONF:
|
||||
|
|
@ -436,6 +548,152 @@ plumvideo_mmap(ctx, offset, prot)
|
|||
return (mips_btop(PLUM_VIDEO_VRAM_IOBASE_PHYSICAL + offset));
|
||||
}
|
||||
|
||||
void
|
||||
plumvideo_clut_get(sc, rgb, beg, cnt)
|
||||
struct plumvideo_softc *sc;
|
||||
u_int32_t *rgb;
|
||||
int beg, cnt;
|
||||
{
|
||||
static void __plumvideo_clut_get __P((bus_space_tag_t,
|
||||
bus_space_handle_t));
|
||||
static void __plumvideo_clut_get(iot, ioh)
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0, beg *= 4; i < cnt; i++, beg += 4) {
|
||||
*rgb++ = bus_space_read_4(iot, ioh, beg) &
|
||||
0x00ffffff;
|
||||
}
|
||||
}
|
||||
|
||||
KASSERT(rgb);
|
||||
KASSERT(LEGAL_CLUT_INDEX(beg));
|
||||
KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1));
|
||||
__plumvideo_clut_access(sc, __plumvideo_clut_get);
|
||||
}
|
||||
|
||||
void
|
||||
plumvideo_clut_set(sc, rgb, beg, cnt)
|
||||
struct plumvideo_softc *sc;
|
||||
u_int32_t *rgb;
|
||||
int beg, cnt;
|
||||
{
|
||||
static void __plumvideo_clut_set __P((bus_space_tag_t,
|
||||
bus_space_handle_t));
|
||||
static void __plumvideo_clut_set(iot, ioh)
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0, beg *= 4; i < cnt; i++, beg +=4) {
|
||||
bus_space_write_4(iot, ioh, beg,
|
||||
*rgb++ & 0x00ffffff);
|
||||
}
|
||||
}
|
||||
|
||||
KASSERT(rgb);
|
||||
KASSERT(LEGAL_CLUT_INDEX(beg));
|
||||
KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1));
|
||||
__plumvideo_clut_access(sc, __plumvideo_clut_set);
|
||||
}
|
||||
|
||||
void
|
||||
plumvideo_clut_default(sc)
|
||||
struct plumvideo_softc *sc;
|
||||
{
|
||||
static void __plumvideo_clut_default __P((bus_space_tag_t,
|
||||
bus_space_handle_t));
|
||||
static void __plumvideo_clut_default(iot, ioh)
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
{
|
||||
const u_int8_t compo6[6] = { 0, 51, 102, 153, 204, 255 };
|
||||
const u_int32_t ansi_color[16] = {
|
||||
0x000000, 0xff0000, 0x00ff00, 0xffff00,
|
||||
0x0000ff, 0xff00ff, 0x00ffff, 0xffffff,
|
||||
0x000000, 0x800000, 0x008000, 0x808000,
|
||||
0x000080, 0x800080, 0x008080, 0x808080,
|
||||
};
|
||||
int i, r, g, b;
|
||||
|
||||
/* ANSI escape sequence */
|
||||
for (i = 0; i < 16; i++) {
|
||||
bus_space_write_4(iot, ioh, i << 2, ansi_color[i]);
|
||||
}
|
||||
/* 16 - 31, gray scale */
|
||||
for ( ; i < 32; i++) {
|
||||
int j = (i - 16) * 17;
|
||||
bus_space_write_4(iot, ioh, i << 2, RGB24(j, j, j));
|
||||
}
|
||||
/* 32 - 247, RGB color */
|
||||
for (r = 0; r < 6; r++) {
|
||||
for (g = 0; g < 6; g++) {
|
||||
for (b = 0; b < 6; b++) {
|
||||
bus_space_write_4(iot, ioh, i << 2,
|
||||
RGB24(compo6[r],
|
||||
compo6[g],
|
||||
compo6[b]));
|
||||
i++;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* 248 - 245, just white */
|
||||
for ( ; i < 256; i++) {
|
||||
bus_space_write_4(iot, ioh, i << 2, 0xffffff);
|
||||
}
|
||||
}
|
||||
|
||||
__plumvideo_clut_access(sc, __plumvideo_clut_default);
|
||||
}
|
||||
|
||||
void
|
||||
__plumvideo_clut_access(sc, palette_func)
|
||||
struct plumvideo_softc *sc;
|
||||
void (*palette_func) __P((bus_space_tag_t, bus_space_handle_t));
|
||||
{
|
||||
bus_space_tag_t regt = sc->sc_regt;
|
||||
bus_space_handle_t regh = sc->sc_regh;
|
||||
plumreg_t val, gmode;
|
||||
|
||||
/* display off */
|
||||
val = bus_space_read_4(regt, regh, PLUM_VIDEO_PLGMD_REG);
|
||||
gmode = val & PLUM_VIDEO_PLGMD_GMODE_MASK;
|
||||
val &= ~PLUM_VIDEO_PLGMD_GMODE_MASK;
|
||||
bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val);
|
||||
|
||||
/* palette access disable */
|
||||
val &= ~PLUM_VIDEO_PLGMD_PALETTE_ENABLE;
|
||||
bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val);
|
||||
|
||||
/* change palette mode to CPU */
|
||||
val &= ~PLUM_VIDEO_PLGMD_MODE_DISPLAY;
|
||||
bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val);
|
||||
|
||||
/* palette access */
|
||||
(*palette_func) (sc->sc_clutiot, sc->sc_clutioh);
|
||||
|
||||
/* change palette mode to Display */
|
||||
val |= PLUM_VIDEO_PLGMD_MODE_DISPLAY;
|
||||
bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val);
|
||||
/* palette access enable */
|
||||
val |= PLUM_VIDEO_PLGMD_PALETTE_ENABLE;
|
||||
bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val);
|
||||
|
||||
/* display on */
|
||||
val |= gmode;
|
||||
bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val);
|
||||
}
|
||||
|
||||
/* !!! */
|
||||
static void
|
||||
_flush_cache()
|
||||
{
|
||||
MachFlushCache();
|
||||
}
|
||||
|
||||
#ifdef PLUMVIDEODEBUG
|
||||
void
|
||||
plumvideo_dump(sc)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: plumvideoreg.h,v 1.3 2000/05/02 17:50:51 uch Exp $ */
|
||||
/* $NetBSD: plumvideoreg.h,v 1.4 2000/05/08 21:57:57 uch Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved.
|
||||
|
|
@ -141,10 +141,14 @@
|
|||
/* Graphics Mode */
|
||||
#define PLUM_VIDEO_PLGMD_REG 0x0dc
|
||||
|
||||
#define PLUM_VIDEO_PLGMD_MASK 0x3
|
||||
#define PLUM_VIDEO_PLGMD_GMODE_MASK 0x3
|
||||
#define PLUM_VIDEO_PLGMD_DISABLE 0x0
|
||||
#define PLUM_VIDEO_PLGMD_8BPP 0x1
|
||||
#define PLUM_VIDEO_PLGMD_16BPP 0x2
|
||||
|
||||
#define PLUM_VIDEO_PLGMD_MODE_DISPLAY 0x4
|
||||
#define PLUM_VIDEO_PLGMD_PALETTE_ENABLE 0x8
|
||||
|
||||
/*
|
||||
* CRT Timing Register
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,95 @@
|
|||
/* $NetBSD: video_subr.c,v 1.1 2000/05/08 21:57:56 uch Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2000 UCHIYAMA Yasushi. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/malloc.h>
|
||||
|
||||
#include <arch/hpcmips/dev/video_subr.h>
|
||||
|
||||
int
|
||||
cmap_work_alloc(r, g, b, rgb, cnt)
|
||||
u_int8_t **r, **g, **b;
|
||||
u_int32_t **rgb;
|
||||
int cnt;
|
||||
{
|
||||
KASSERT(r && g && b && rgb && LEGAL_CLUT_INDEX(cnt - 1));
|
||||
|
||||
*r = malloc(cnt * sizeof(u_int8_t), M_DEVBUF, M_WAITOK);
|
||||
*g = malloc(cnt * sizeof(u_int8_t), M_DEVBUF, M_WAITOK);
|
||||
*b = malloc(cnt * sizeof(u_int8_t), M_DEVBUF, M_WAITOK);
|
||||
*rgb = malloc(cnt * sizeof(u_int32_t), M_DEVBUF, M_WAITOK);
|
||||
|
||||
return (!(*r && *g && *b && *rgb));
|
||||
}
|
||||
|
||||
void
|
||||
cmap_work_free(r, g, b, rgb)
|
||||
u_int8_t *r, *g, *b;
|
||||
u_int32_t *rgb;
|
||||
{
|
||||
if (r)
|
||||
free(r, M_DEVBUF);
|
||||
if (g)
|
||||
free(g, M_DEVBUF);
|
||||
if (b)
|
||||
free(b, M_DEVBUF);
|
||||
if (rgb)
|
||||
free(rgb, M_DEVBUF);
|
||||
}
|
||||
|
||||
void
|
||||
rgb24_compose(rgb24, r, g, b, cnt)
|
||||
u_int32_t *rgb24;
|
||||
u_int8_t *r, *g, *b;
|
||||
int cnt;
|
||||
{
|
||||
int i;
|
||||
KASSERT(rgb24 && r && g && b && LEGAL_CLUT_INDEX(cnt - 1));
|
||||
|
||||
for (i = 0; i < cnt; i++) {
|
||||
*rgb24++ = RGB24(r[i], g[i], b[i]);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
rgb24_decompose(rgb24, r, g, b, cnt)
|
||||
u_int32_t *rgb24;
|
||||
u_int8_t *r, *g, *b;
|
||||
int cnt;
|
||||
{
|
||||
int i;
|
||||
KASSERT(rgb24 && r && g && b && LEGAL_CLUT_INDEX(cnt - 1));
|
||||
|
||||
for (i = 0; i < cnt; i++) {
|
||||
u_int32_t rgb = *rgb24++;
|
||||
*r++ = (rgb >> 16) & 0xff;
|
||||
*g++ = (rgb >> 8) & 0xff;
|
||||
*b++ = rgb & 0xff;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* $NetBSD: video_subr.h,v 1.1 2000/05/08 21:57:56 uch Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2000 UCHIYAMA Yasushi. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#define LEGAL_CLUT_INDEX(x) ((x) >= 0 && (x) <= 255)
|
||||
#define RGB24(r, g, b) ((((r) << 24) & 0x00ff0000) | \
|
||||
(((g) << 16) & 0x0000ff00) | \
|
||||
(((b)) & 0x000000ff))
|
||||
|
||||
int cmap_work_alloc __P((u_int8_t **, u_int8_t **, u_int8_t **,
|
||||
u_int32_t **, int));
|
||||
void cmap_work_free __P((u_int8_t *, u_int8_t *, u_int8_t *,
|
||||
u_int32_t *));
|
||||
void rgb24_compose __P((u_int32_t *, u_int8_t *, u_int8_t *, u_int8_t *,
|
||||
int));
|
||||
void rgb24_decompose __P((u_int32_t *, u_int8_t *, u_int8_t *,
|
||||
u_int8_t *, int));
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: tx3912video.c,v 1.11 2000/05/02 17:50:52 uch Exp $ */
|
||||
/* $NetBSD: tx3912video.c,v 1.12 2000/05/08 21:57:58 uch Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved.
|
||||
|
|
@ -25,6 +25,7 @@
|
|||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#define TX3912VIDEO_DEBUG
|
||||
|
||||
#include "opt_tx39_debug.h"
|
||||
#include "hpcfb.h"
|
||||
|
|
@ -35,6 +36,8 @@
|
|||
#include <sys/extent.h>
|
||||
|
||||
#include <sys/ioctl.h>
|
||||
#include <sys/buf.h>
|
||||
#include <vm/vm.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/bootinfo.h>
|
||||
|
|
@ -43,12 +46,15 @@
|
|||
#include <hpcmips/tx/tx3912videovar.h>
|
||||
#include <hpcmips/tx/tx3912videoreg.h>
|
||||
|
||||
/* CLUT */
|
||||
#include <dev/wscons/wsdisplayvar.h>
|
||||
#include <dev/rasops/rasops.h>
|
||||
#include <arch/hpcmips/dev/video_subr.h>
|
||||
|
||||
#include <dev/wscons/wsconsio.h>
|
||||
#include <arch/hpcmips/dev/hpcfbvar.h>
|
||||
#include <arch/hpcmips/dev/hpcfbio.h>
|
||||
|
||||
#define TX3912VIDEO_DEBUG
|
||||
|
||||
static struct tx3912video_chip {
|
||||
tx_chipset_tag_t vc_tc;
|
||||
|
||||
|
|
@ -83,13 +89,21 @@ void tx3912video_hpcfbinit __P((struct tx3912video_softc *));
|
|||
int tx3912video_ioctl __P((void *, u_long, caddr_t, int, struct proc *));
|
||||
int tx3912video_mmap __P((void *, off_t, int));
|
||||
|
||||
void tx3912video_clut_init __P((struct tx3912video_softc *));
|
||||
void tx3912video_clut_install __P((void *, struct rasops_info *));
|
||||
void tx3912video_clut_get __P((struct tx3912video_softc *,
|
||||
u_int32_t *, int, int));
|
||||
static int __get_color8 __P((int));
|
||||
static int __get_color4 __P((int));
|
||||
|
||||
struct cfattach tx3912video_ca = {
|
||||
sizeof(struct tx3912video_softc), tx3912video_match,
|
||||
tx3912video_attach
|
||||
};
|
||||
|
||||
struct hpcfb_accessops tx3912video_ha = {
|
||||
tx3912video_ioctl, tx3912video_mmap
|
||||
tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0,
|
||||
tx3912video_clut_install
|
||||
};
|
||||
|
||||
void __tx3912video_attach_drawfunc __P((struct tx3912video_chip*));
|
||||
|
|
@ -118,6 +132,8 @@ tx3912video_attach(parent, self, aux)
|
|||
[TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color"
|
||||
};
|
||||
struct hpcfb_attach_args ha;
|
||||
tx_chipset_tag_t tc;
|
||||
txreg_t val;
|
||||
int console = (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) ? 0 : 1;
|
||||
|
||||
sc->sc_chip = chip = &tx3912video_chip;
|
||||
|
|
@ -128,6 +144,15 @@ tx3912video_attach(parent, self, aux)
|
|||
(unsigned)chip->vc_fbaddr,
|
||||
(unsigned)(chip->vc_fbaddr + chip->vc_fbsize));
|
||||
|
||||
/* don't inverse VDAT[3:0] signal */
|
||||
tc = chip->vc_tc;
|
||||
val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
|
||||
val &= ~TX3912_VIDEOCTRL1_INVVID;
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
|
||||
|
||||
/* install default CLUT */
|
||||
tx3912video_clut_init(sc);
|
||||
|
||||
/* if serial console, power off video module */
|
||||
#ifndef TX3912VIDEO_DEBUG
|
||||
if (!console) {
|
||||
|
|
@ -176,16 +201,17 @@ tx3912video_hpcfbinit(sc)
|
|||
|
||||
fb->hf_conf_index = 0; /* configuration index */
|
||||
fb->hf_nconfs = 1; /* how many configurations */
|
||||
strcpy(fb->hf_name, "TX3912 built-in video");
|
||||
strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN);
|
||||
/* frame buffer name */
|
||||
strcpy(fb->hf_conf_name, "LCD");
|
||||
strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN);
|
||||
/* configuration name */
|
||||
fb->hf_height = chip->vc_fbheight;
|
||||
fb->hf_width = chip->vc_fbwidth;
|
||||
fb->hf_baseaddr = mips_ptob(mips_btop(fbcaddr));
|
||||
fb->hf_offset = (u_long)fbcaddr - fb->hf_baseaddr;
|
||||
/* frame buffer start offset */
|
||||
fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth) / NBBY;
|
||||
fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth)
|
||||
/ NBBY;
|
||||
fb->hf_nplanes = 1;
|
||||
fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line;
|
||||
|
||||
|
|
@ -193,7 +219,6 @@ tx3912video_hpcfbinit(sc)
|
|||
fb->hf_access_flags |= HPCFB_ACCESS_WORD;
|
||||
fb->hf_access_flags |= HPCFB_ACCESS_DWORD;
|
||||
|
||||
fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; /* XXX */
|
||||
switch (chip->vc_fbdepth) {
|
||||
default:
|
||||
panic("tx3912video_hpcfbinit: not supported color depth\n");
|
||||
|
|
@ -208,7 +233,7 @@ tx3912video_hpcfbinit(sc)
|
|||
fb->hf_u.hf_gray.hf_flags = 0; /* reserved for future use */
|
||||
break;
|
||||
case 8:
|
||||
fb->hf_class = HPCFB_CLASS_INDEXCOLOR; /* XXX */
|
||||
fb->hf_class = HPCFB_CLASS_INDEXCOLOR;
|
||||
fb->hf_access_flags |= HPCFB_ACCESS_STATIC;
|
||||
fb->hf_pack_width = 8;
|
||||
fb->hf_pixels_per_pack = 1;
|
||||
|
|
@ -441,14 +466,50 @@ tx3912video_ioctl(v, cmd, data, flag, p)
|
|||
struct tx3912video_softc *sc = (struct tx3912video_softc *)v;
|
||||
struct hpcfb_fbconf *fbconf;
|
||||
struct hpcfb_dspconf *dspconf;
|
||||
struct wsdisplay_cmap *cmap;
|
||||
u_int8_t *r, *g, *b;
|
||||
u_int32_t *rgb;
|
||||
int idx, cnt, error;
|
||||
|
||||
switch (cmd) {
|
||||
case WSDISPLAYIO_GETCMAP:
|
||||
/* XXX not implemented yet */
|
||||
return (EINVAL);
|
||||
cmap = (struct wsdisplay_cmap*)data;
|
||||
cnt = cmap->count;
|
||||
idx = cmap->index;
|
||||
|
||||
if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR ||
|
||||
sc->sc_fbconf.hf_pack_width != 8 ||
|
||||
!LEGAL_CLUT_INDEX(idx) ||
|
||||
!LEGAL_CLUT_INDEX(idx + cnt -1)) {
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (!uvm_useracc(cmap->red, cnt, B_WRITE) ||
|
||||
!uvm_useracc(cmap->green, cnt, B_WRITE) ||
|
||||
!uvm_useracc(cmap->blue, cnt, B_WRITE)) {
|
||||
return (EFAULT);
|
||||
}
|
||||
|
||||
error = cmap_work_alloc(&r, &g, &b, &rgb, cnt);
|
||||
if (error != 0) {
|
||||
cmap_work_free(r, g, b, rgb);
|
||||
return (ENOMEM);
|
||||
}
|
||||
tx3912video_clut_get(sc, rgb, idx, cnt);
|
||||
rgb24_decompose(rgb, r, g, b, cnt);
|
||||
|
||||
copyout(r, cmap->red, cnt);
|
||||
copyout(g, cmap->green,cnt);
|
||||
copyout(b, cmap->blue, cnt);
|
||||
|
||||
cmap_work_free(r, g, b, rgb);
|
||||
|
||||
return (0);
|
||||
|
||||
case WSDISPLAYIO_PUTCMAP:
|
||||
/* XXX not implemented yet */
|
||||
/*
|
||||
* TX3912 can't change CLUT index. R:G:B = 3:3:2
|
||||
*/
|
||||
return (EINVAL);
|
||||
|
||||
case HPCFBIO_GCONF:
|
||||
|
|
@ -521,6 +582,187 @@ tx3912video_mmap(ctx, offset, prot)
|
|||
return (mips_btop(sc->sc_chip->vc_fbaddr + offset));
|
||||
}
|
||||
|
||||
/*
|
||||
* CLUT staff
|
||||
*/
|
||||
static const struct {
|
||||
int mul, div;
|
||||
} dither_list [] = {
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 },
|
||||
[TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 }
|
||||
}, *dlp;
|
||||
|
||||
static const int dither_level8[8] = {
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_0,
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_2_7,
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_2_5,
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_2_4,
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_3_5,
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_5_7,
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_4_5,
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_1,
|
||||
};
|
||||
|
||||
static const int dither_level4[4] = {
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_0,
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_1_3,
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_5_7,
|
||||
TX3912_VIDEO_DITHER_DUTYCYCLE_1,
|
||||
};
|
||||
|
||||
static int
|
||||
__get_color8(luti)
|
||||
int luti;
|
||||
{
|
||||
KASSERT(luti >=0 && luti < 8);
|
||||
dlp = &dither_list[dither_level8[luti]];
|
||||
|
||||
return ((0xff * dlp->mul) / dlp->div);
|
||||
}
|
||||
|
||||
static int
|
||||
__get_color4(luti)
|
||||
int luti;
|
||||
{
|
||||
KASSERT(luti >=0 && luti < 4);
|
||||
dlp = &dither_list[dither_level4[luti]];
|
||||
|
||||
return ((0xff * dlp->mul) / dlp->div);
|
||||
}
|
||||
|
||||
void
|
||||
tx3912video_clut_get(sc, rgb, beg, cnt)
|
||||
struct tx3912video_softc *sc;
|
||||
u_int32_t *rgb;
|
||||
int beg, cnt;
|
||||
{
|
||||
int i;
|
||||
|
||||
KASSERT(rgb);
|
||||
KASSERT(LEGAL_CLUT_INDEX(beg));
|
||||
KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1));
|
||||
|
||||
for (i = 0; i < cnt; i++) {
|
||||
rgb[i] = RGB24(__get_color8((i >> 5) & 0x7),
|
||||
__get_color8((i >> 2) & 0x7),
|
||||
__get_color4(i & 0x3));
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
tx3912video_clut_install(ctx, ri)
|
||||
void *ctx;
|
||||
struct rasops_info *ri;
|
||||
{
|
||||
struct tx3912video_softc *sc = ctx;
|
||||
const int system_cmap[0x10] = {
|
||||
TX3912VIDEO_BLACK,
|
||||
TX3912VIDEO_RED,
|
||||
TX3912VIDEO_GREEN,
|
||||
TX3912VIDEO_YELLOW,
|
||||
TX3912VIDEO_BLUE,
|
||||
TX3912VIDEO_MAGENTA,
|
||||
TX3912VIDEO_CYAN,
|
||||
TX3912VIDEO_WHITE,
|
||||
TX3912VIDEO_DARK_BLACK,
|
||||
TX3912VIDEO_DARK_RED,
|
||||
TX3912VIDEO_DARK_GREEN,
|
||||
TX3912VIDEO_DARK_YELLOW,
|
||||
TX3912VIDEO_DARK_BLUE,
|
||||
TX3912VIDEO_DARK_MAGENTA,
|
||||
TX3912VIDEO_DARK_CYAN,
|
||||
TX3912VIDEO_DARK_WHITE,
|
||||
};
|
||||
|
||||
KASSERT(ri);
|
||||
|
||||
if (sc->sc_chip->vc_fbdepth == 8) {
|
||||
/* XXX 2bit gray scale LUT not supported */
|
||||
memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
tx3912video_clut_init(sc)
|
||||
struct tx3912video_softc *sc;
|
||||
{
|
||||
tx_chipset_tag_t tc = sc->sc_chip->vc_tc;
|
||||
|
||||
if (sc->sc_chip->vc_fbdepth != 8) {
|
||||
return; /* XXX 2bit gray scale LUT not supported */
|
||||
}
|
||||
|
||||
/*
|
||||
* time-based dithering pattern (TOSHIBA recommended pattern)
|
||||
*/
|
||||
/* 2/3, 1/3 */
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL8_REG,
|
||||
TX3912_VIDEOCTRL8_PAT2_3_DEFAULT);
|
||||
/* 3/4, 2/4 */
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL9_REG,
|
||||
(TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) |
|
||||
TX3912_VIDEOCTRL9_PAT2_4_DEFAULT);
|
||||
/* 4/5, 1/5 */
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL10_REG,
|
||||
TX3912_VIDEOCTRL10_PAT4_5_DEFAULT);
|
||||
/* 3/5, 2/5 */
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL11_REG,
|
||||
TX3912_VIDEOCTRL11_PAT3_5_DEFAULT);
|
||||
/* 6/7, 1/7 */
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL12_REG,
|
||||
TX3912_VIDEOCTRL12_PAT6_7_DEFAULT);
|
||||
/* 5/7, 2/7 */
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL13_REG,
|
||||
TX3912_VIDEOCTRL13_PAT5_7_DEFAULT);
|
||||
/* 4/7, 3/7 */
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL14_REG,
|
||||
TX3912_VIDEOCTRL14_PAT4_7_DEFAULT);
|
||||
|
||||
/*
|
||||
* dither-pattern look-up table. (selected by uch)
|
||||
*/
|
||||
/* red */
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL5_REG,
|
||||
(dither_level8[7] << 28) |
|
||||
(dither_level8[6] << 24) |
|
||||
(dither_level8[5] << 20) |
|
||||
(dither_level8[4] << 16) |
|
||||
(dither_level8[3] << 12) |
|
||||
(dither_level8[2] << 8) |
|
||||
(dither_level8[1] << 4) |
|
||||
(dither_level8[0] << 0));
|
||||
/* green */
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL6_REG,
|
||||
(dither_level8[7] << 28) |
|
||||
(dither_level8[6] << 24) |
|
||||
(dither_level8[5] << 20) |
|
||||
(dither_level8[4] << 16) |
|
||||
(dither_level8[3] << 12) |
|
||||
(dither_level8[2] << 8) |
|
||||
(dither_level8[1] << 4) |
|
||||
(dither_level8[0] << 0));
|
||||
/* blue (2bit gray scale also use this look-up table) */
|
||||
tx_conf_write(tc, TX3912_VIDEOCTRL7_REG,
|
||||
(dither_level4[3] << 12) |
|
||||
(dither_level4[2] << 8) |
|
||||
(dither_level4[1] << 4) |
|
||||
(dither_level4[0] << 0));
|
||||
}
|
||||
|
||||
/*
|
||||
* Debug routines.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,51 +1,51 @@
|
|||
/* $NetBSD: tx3912videoreg.h,v 1.2 2000/01/07 15:10:50 uch Exp $ */
|
||||
/* $NetBSD: tx3912videoreg.h,v 1.3 2000/05/08 21:57:58 uch Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1999, by UCHIYAMA Yasushi
|
||||
* All rights reserved.
|
||||
/*-
|
||||
* Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. The name of the developer may NOT be used to endorse or promote products
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*
|
||||
* TOSHIBA TMPR3912/05, Philips PR31700 Video module register
|
||||
*/
|
||||
#define TX3912_VIDEOCTRL1_REG 0x28
|
||||
#define TX3912_VIDEOCTRL2_REG 0x2c
|
||||
#define TX3912_VIDEOCTRL3_REG 0x30
|
||||
#define TX3912_VIDEOCTRL4_REG 0x34
|
||||
#define TX3912_VIDEOCTRL5_REG 0x38
|
||||
#define TX3912_VIDEOCTRL6_REG 0x3c
|
||||
#define TX3912_VIDEOCTRL7_REG 0x40
|
||||
#define TX3912_VIDEOCTRL8_REG 0x44
|
||||
#define TX3912_VIDEOCTRL9_REG 0x48
|
||||
#define TX3912_VIDEOCTRL10_REG 0x4c
|
||||
#define TX3912_VIDEOCTRL11_REG 0x50
|
||||
#define TX3912_VIDEOCTRL12_REG 0x54
|
||||
#define TX3912_VIDEOCTRL13_REG 0x58
|
||||
#define TX3912_VIDEOCTRL14_REG 0x5c
|
||||
#define TX3912_VIDEOCTRL1_REG 0x28
|
||||
#define TX3912_VIDEOCTRL2_REG 0x2c
|
||||
#define TX3912_VIDEOCTRL3_REG 0x30
|
||||
#define TX3912_VIDEOCTRL4_REG 0x34
|
||||
#define TX3912_VIDEOCTRL5_REG 0x38
|
||||
#define TX3912_VIDEOCTRL6_REG 0x3c
|
||||
#define TX3912_VIDEOCTRL7_REG 0x40
|
||||
#define TX3912_VIDEOCTRL8_REG 0x44
|
||||
#define TX3912_VIDEOCTRL9_REG 0x48
|
||||
#define TX3912_VIDEOCTRL10_REG 0x4c
|
||||
#define TX3912_VIDEOCTRL11_REG 0x50
|
||||
#define TX3912_VIDEOCTRL12_REG 0x54
|
||||
#define TX3912_VIDEOCTRL13_REG 0x58
|
||||
#define TX3912_VIDEOCTRL14_REG 0x5c
|
||||
|
||||
#define TX3912_FRAMEBUFFER_ALIGNMENT 16
|
||||
#define TX3912_FRAMEBUFFER_BOUNDARY 0x100000
|
||||
#define TX3912_FRAMEBUFFER_MAX (2048 * 1024 * 8)
|
||||
#define TX3912_FRAMEBUFFER_ALIGNMENT 16
|
||||
#define TX3912_FRAMEBUFFER_BOUNDARY 0x100000
|
||||
#define TX3912_FRAMEBUFFER_MAX (2048 * 1024 * 8)
|
||||
|
||||
/*
|
||||
* Video Control 1 Register
|
||||
|
|
@ -53,8 +53,8 @@
|
|||
/* R */
|
||||
#define TX3912_VIDEOCTRL1_LINECNT_SHIFT 22
|
||||
#define TX3912_VIDEOCTRL1_LINECNT_MASK 0x3ff
|
||||
#define TX3912_VIDEOCTRL1_LINECNT(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL1_LINECNT_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL1_LINECNT(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL1_LINECNT_SHIFT) & \
|
||||
TX3912_VIDEOCTRL1_LINECNT_MASK)
|
||||
/* R/W */
|
||||
#define TX3912_VIDEOCTRL1_LOADDLY 0x00200000
|
||||
|
|
@ -64,35 +64,35 @@
|
|||
*/
|
||||
#define TX3912_VIDEOCTRL1_BAUDVAL_SHIFT 16
|
||||
#define TX3912_VIDEOCTRL1_BAUDVAL_MASK 0x1f
|
||||
#define TX3912_VIDEOCTRL1_BAUDVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL1_BAUDVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \
|
||||
TX3912_VIDEOCTRL1_BAUDVAL_MASK)
|
||||
#define TX3912_VIDEOCTRL1_BAUDVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL1_BAUDVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL1_BAUDVAL_MASK << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT)))
|
||||
|
||||
/* R/W */
|
||||
#define TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT 9
|
||||
#define TX3912_VIDEOCTRL1_VIDDONEVAL_MASK 0x7f
|
||||
#define TX3912_VIDEOCTRL1_VIDDONEVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL1_VIDDONEVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \
|
||||
TX3912_VIDEOCTRL1_VIDDONEVAL_MASK)
|
||||
#define TX3912_VIDEOCTRL1_VIDDONEVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL1_VIDDONEVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL1_VIDDONEVAL_MASK << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT)))
|
||||
/* R/W */
|
||||
#define TX3912_VIDEOCTRL1_ENFREEZEFRAME 0x00000100
|
||||
/* R/W */
|
||||
#define TX3912_VIDEOCTRL1_BITSEL_SHIFT 6
|
||||
#define TX3912_VIDEOCTRL1_BITSEL_MASK 0x3
|
||||
#define TX3912_VIDEOCTRL1_BITSEL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL1_BITSEL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \
|
||||
TX3912_VIDEOCTRL1_BITSEL_MASK)
|
||||
#define TX3912_VIDEOCTRL1_BITSEL_CLR(cr) \
|
||||
((cr) &= ~(TX3912_VIDEOCTRL1_BITSEL_MASK << \
|
||||
#define TX3912_VIDEOCTRL1_BITSEL_CLR(cr) \
|
||||
((cr) &= ~(TX3912_VIDEOCTRL1_BITSEL_MASK << \
|
||||
TX3912_VIDEOCTRL1_BITSEL_SHIFT))
|
||||
#define TX3912_VIDEOCTRL1_BITSEL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL1_BITSEL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL1_BITSEL_MASK << TX3912_VIDEOCTRL1_BITSEL_SHIFT)))
|
||||
#define TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR 0x3
|
||||
#define TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE 0x2
|
||||
|
|
@ -112,11 +112,11 @@
|
|||
/* W */
|
||||
#define TX3912_VIDEOCTRL2_VIDRATE_SHIFT 22
|
||||
#define TX3912_VIDEOCTRL2_VIDRATE_MASK 0x3ff
|
||||
#define TX3912_VIDEOCTRL2_VIDRATE(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL2_VIDRATE(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \
|
||||
TX3912_VIDEOCTRL2_VIDRATE_MASK)
|
||||
#define TX3912_VIDEOCTRL2_VIDRATE_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL2_VIDRATE_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL2_VIDRATE_MASK << TX3912_VIDEOCTRL2_VIDRATE_SHIFT)))
|
||||
|
||||
/* W */
|
||||
|
|
@ -126,11 +126,11 @@
|
|||
*/
|
||||
#define TX3912_VIDEOCTRL2_HORZVAL_SHIFT 12
|
||||
#define TX3912_VIDEOCTRL2_HORZVAL_MASK 0x1ff
|
||||
#define TX3912_VIDEOCTRL2_HORZVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL2_HORZVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \
|
||||
TX3912_VIDEOCTRL2_HORZVAL_MASK)
|
||||
#define TX3912_VIDEOCTRL2_HORZVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL2_HORZVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL2_HORZVAL_MASK << TX3912_VIDEOCTRL2_HORZVAL_SHIFT)))
|
||||
|
||||
/* W */
|
||||
|
|
@ -140,11 +140,11 @@
|
|||
*/
|
||||
#define TX3912_VIDEOCTRL2_LINEVAL_SHIFT 0
|
||||
#define TX3912_VIDEOCTRL2_LINEVAL_MASK 0x3ff
|
||||
#define TX3912_VIDEOCTRL2_LINEVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL2_LINEVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \
|
||||
TX3912_VIDEOCTRL2_LINEVAL_MASK)
|
||||
#define TX3912_VIDEOCTRL2_LINEVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL2_LINEVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL2_LINEVAL_MASK << TX3912_VIDEOCTRL2_LINEVAL_SHIFT)))
|
||||
|
||||
/*
|
||||
|
|
@ -153,21 +153,21 @@
|
|||
/* W */
|
||||
#define TX3912_VIDEOCTRL3_VIDBANK_SHIFT 20
|
||||
#define TX3912_VIDEOCTRL3_VIDBANK_MASK 0xfff
|
||||
#define TX3912_VIDEOCTRL3_VIDBANK(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL3_VIDBANK(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \
|
||||
TX3912_VIDEOCTRL3_VIDBANK_MASK)
|
||||
#define TX3912_VIDEOCTRL3_VIDBANK_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL3_VIDBANK_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL3_VIDBANK_MASK << TX3912_VIDEOCTRL3_VIDBANK_SHIFT)))
|
||||
|
||||
/* W */
|
||||
#define TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT 4
|
||||
#define TX3912_VIDEOCTRL3_VIDBASEHI_MASK 0xffff
|
||||
#define TX3912_VIDEOCTRL3_VIDBASEHI(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL3_VIDBASEHI(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \
|
||||
TX3912_VIDEOCTRL3_VIDBASEHI_MASK)
|
||||
#define TX3912_VIDEOCTRL3_VIDBASEHI_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL3_VIDBASEHI_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL3_VIDBASEHI_MASK << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT)))
|
||||
|
||||
|
||||
|
|
@ -180,29 +180,29 @@
|
|||
*/
|
||||
#define TX3912_VIDEOCTRL4_DFVAL_SHIFT 24
|
||||
#define TX3912_VIDEOCTRL4_DFVAL_MASK 0xff
|
||||
#define TX3912_VIDEOCTRL4_DFVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL4_DFVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \
|
||||
TX3912_VIDEOCTRL4_DFVAL_MASK)
|
||||
#define TX3912_VIDEOCTRL4_DFVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL4_DFVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL4_DFVAL_MASK << TX3912_VIDEOCTRL4_DFVAL_SHIFT)))
|
||||
|
||||
#define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT 20
|
||||
#define TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK 0xf
|
||||
#define TX3912_VIDEOCTRL4_FRAMEMASKVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL4_FRAMEMASKVAL(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \
|
||||
TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK)
|
||||
#define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT)))
|
||||
|
||||
#define TX3912_VIDEOCTRL4_VIDBASELO_SHIFT 4
|
||||
#define TX3912_VIDEOCTRL4_VIDBASELO_MASK 0xffff
|
||||
#define TX3912_VIDEOCTRL4_VIDBASELO(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL4_VIDBASELO(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \
|
||||
TX3912_VIDEOCTRL4_VIDBASELO_MASK)
|
||||
#define TX3912_VIDEOCTRL4_VIDBASELO_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL4_VIDBASELO_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL4_VIDBASELO_MASK << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT)))
|
||||
|
||||
/*
|
||||
|
|
@ -238,11 +238,11 @@
|
|||
*/
|
||||
#define TX3912_VIDEOCTRL8_PAT2_3_SHIFT 0
|
||||
#define TX3912_VIDEOCTRL8_PAT2_3_MASK 0xfff
|
||||
#define TX3912_VIDEOCTRL8_PAT2_3(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL8_PAT2_3(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \
|
||||
TX3912_VIDEOCTRL8_PAT2_3_MASK)
|
||||
#define TX3912_VIDEOCTRL8_PAT2_3_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL8_PAT2_3_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL8_PAT2_3_MASK << TX3912_VIDEOCTRL8_PAT2_3_SHIFT)))
|
||||
|
||||
/*
|
||||
|
|
@ -251,20 +251,20 @@
|
|||
/* W */
|
||||
#define TX3912_VIDEOCTRL9_PAT3_4_SHIFT 16
|
||||
#define TX3912_VIDEOCTRL9_PAT3_4_MASK 0xffff
|
||||
#define TX3912_VIDEOCTRL9_PAT3_4(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL9_PAT3_4(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \
|
||||
TX3912_VIDEOCTRL9_PAT3_4_MASK)
|
||||
#define TX3912_VIDEOCTRL9_PAT3_4_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL9_PAT3_4_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL9_PAT3_4_MASK << TX3912_VIDEOCTRL9_PAT3_4_SHIFT)))
|
||||
/* W */
|
||||
#define TX3912_VIDEOCTRL9_PAT2_4_SHIFT 0
|
||||
#define TX3912_VIDEOCTRL9_PAT2_4_MASK 0xffff
|
||||
#define TX3912_VIDEOCTRL9_PAT2_4(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL9_PAT2_4(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \
|
||||
TX3912_VIDEOCTRL9_PAT2_4_MASK)
|
||||
#define TX3912_VIDEOCTRL9_PAT2_4_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL9_PAT2_4_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL9_PAT2_4_MASK << TX3912_VIDEOCTRL9_PAT2_4_SHIFT)))
|
||||
|
||||
/*
|
||||
|
|
@ -273,11 +273,11 @@
|
|||
/* W */
|
||||
#define TX3912_VIDEOCTRL10_PAT4_5_SHIFT 0
|
||||
#define TX3912_VIDEOCTRL10_PAT4_5_MASK 0xfffff
|
||||
#define TX3912_VIDEOCTRL10_PAT4_5(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL10_PAT4_5(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \
|
||||
TX3912_VIDEOCTRL10_PAT4_5_MASK)
|
||||
#define TX3912_VIDEOCTRL10_PAT4_5_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL10_PAT4_5_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL10_PAT4_5_MASK << TX3912_VIDEOCTRL10_PAT4_5_SHIFT)))
|
||||
|
||||
/*
|
||||
|
|
@ -286,11 +286,11 @@
|
|||
/* W */
|
||||
#define TX3912_VIDEOCTRL11_PAT3_5_SHIFT 0
|
||||
#define TX3912_VIDEOCTRL11_PAT3_5_MASK 0xfffff
|
||||
#define TX3912_VIDEOCTRL11_PAT3_5(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL11_PAT3_5(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \
|
||||
TX3912_VIDEOCTRL11_PAT3_5_MASK)
|
||||
#define TX3912_VIDEOCTRL11_PAT3_5_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL11_PAT3_5_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL11_PAT3_5_MASK << TX3912_VIDEOCTRL11_PAT3_5_SHIFT)))
|
||||
|
||||
/*
|
||||
|
|
@ -299,11 +299,11 @@
|
|||
/* W */
|
||||
#define TX3912_VIDEOCTRL12_PAT6_7_SHIFT 0
|
||||
#define TX3912_VIDEOCTRL12_PAT6_7_MASK 0xfffffff
|
||||
#define TX3912_VIDEOCTRL12_PAT6_7(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL12_PAT6_7(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \
|
||||
TX3912_VIDEOCTRL12_PAT6_7_MASK)
|
||||
#define TX3912_VIDEOCTRL12_PAT6_7_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL12_PAT6_7_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL12_PAT6_7_MASK << TX3912_VIDEOCTRL12_PAT6_7_SHIFT)))
|
||||
|
||||
/*
|
||||
|
|
@ -312,11 +312,11 @@
|
|||
/* W */
|
||||
#define TX3912_VIDEOCTRL13_PAT5_7_SHIFT 0
|
||||
#define TX3912_VIDEOCTRL13_PAT5_7_MASK 0xfffffff
|
||||
#define TX3912_VIDEOCTRL13_PAT5_7(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL13_PAT5_7(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \
|
||||
TX3912_VIDEOCTRL13_PAT5_7_MASK)
|
||||
#define TX3912_VIDEOCTRL13_PAT5_7_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL13_PAT5_7_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL13_PAT5_7_MASK << TX3912_VIDEOCTRL13_PAT5_7_SHIFT)))
|
||||
|
||||
/*
|
||||
|
|
@ -325,11 +325,67 @@
|
|||
/* W */
|
||||
#define TX3912_VIDEOCTRL14_PAT4_7_SHIFT 0
|
||||
#define TX3912_VIDEOCTRL14_PAT4_7_MASK 0xfffffff
|
||||
#define TX3912_VIDEOCTRL14_PAT4_7(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL14_PAT4_7(cr) \
|
||||
(((cr) >> TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \
|
||||
TX3912_VIDEOCTRL14_PAT4_7_MASK)
|
||||
#define TX3912_VIDEOCTRL14_PAT4_7_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \
|
||||
#define TX3912_VIDEOCTRL14_PAT4_7_SET(cr, val) \
|
||||
((cr) | (((val) << TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \
|
||||
(TX3912_VIDEOCTRL14_PAT4_7_MASK << TX3912_VIDEOCTRL14_PAT4_7_SHIFT)))
|
||||
|
||||
/*
|
||||
* Default dither pattern
|
||||
*/
|
||||
#define P0000 0x0
|
||||
#define P0001 0x1
|
||||
#define P0010 0x2
|
||||
#define P0011 0x3
|
||||
#define P0100 0x4
|
||||
#define P0101 0x5
|
||||
#define P0110 0x6
|
||||
#define P0111 0x7
|
||||
#define P1000 0x8
|
||||
#define P1001 0x9
|
||||
#define P1010 0xa
|
||||
#define P1011 0xb
|
||||
#define P1100 0xc
|
||||
#define P1101 0xd
|
||||
#define P1110 0xe
|
||||
#define P1111 0xf
|
||||
|
||||
#define DITHER_PATTERN(p0, p1, p2, p3, p4, p5, p6) \
|
||||
(((p0) << 24) | ((p1) << 20) | ((p2) << 16) | ((p3) << 12) | \
|
||||
((p4) << 8) | ((p5) << 4) || (p6))
|
||||
|
||||
#define TX3912_VIDEOCTRL8_PAT2_3_DEFAULT \
|
||||
DITHER_PATTERN(0, 0, 0, 0, P0111, P1101, P1010)
|
||||
#define TX3912_VIDEOCTRL9_PAT3_4_DEFAULT \
|
||||
DITHER_PATTERN(0, 0, 0, P0111, P1101, P1011, P1110)
|
||||
#define TX3912_VIDEOCTRL9_PAT2_4_DEFAULT \
|
||||
DITHER_PATTERN(0, 0, 0, P1010, P0101, P1010, P0101)
|
||||
#define TX3912_VIDEOCTRL10_PAT4_5_DEFAULT \
|
||||
DITHER_PATTERN(0, 0, P0111, P1101, P1111, P1011, P1111)
|
||||
#define TX3912_VIDEOCTRL11_PAT3_5_DEFAULT \
|
||||
DITHER_PATTERN(0, 0, P0111, P1010, P0101, P1010, P1101)
|
||||
#define TX3912_VIDEOCTRL12_PAT6_7_DEFAULT \
|
||||
DITHER_PATTERN(P1111, P1011, P1111, P1101, P1111, P1110, P0111)
|
||||
#define TX3912_VIDEOCTRL13_PAT5_7_DEFAULT \
|
||||
DITHER_PATTERN(P0111, P1011, P0101, P1010, P1101, P1110, P1111)
|
||||
#define TX3912_VIDEOCTRL14_PAT4_7_DEFAULT \
|
||||
DITHER_PATTERN(P1011, P1001, P1101, P1101, P1100, P0110, P0011)
|
||||
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_1 15
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_6_7 14
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_4_5 13
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_3_4 12
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_5_7 11
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_2_3 10
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_3_5 9
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_4_7 8
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_2_4 7
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_3_7 6
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_2_5 5
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_1_3 4
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_2_7 3
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_1_5 2
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_1_7 1
|
||||
#define TX3912_VIDEO_DITHER_DUTYCYCLE_0 0
|
||||
|
|
|
|||
|
|
@ -1,8 +1,7 @@
|
|||
/* $NetBSD: tx3912videovar.h,v 1.4 2000/04/24 13:02:14 uch Exp $ */
|
||||
/* $NetBSD: tx3912videovar.h,v 1.5 2000/05/08 21:57:58 uch Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1999, 2000 UCHIYAMA Yasushi
|
||||
* All rights reserved.
|
||||
/*-
|
||||
* Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -12,6 +11,8 @@
|
|||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
|
|
@ -21,12 +22,44 @@
|
|||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
int tx3912video_init __P((paddr_t, paddr_t *));
|
||||
|
||||
/*
|
||||
* 8bpp CLUT
|
||||
*/
|
||||
#define TX3912VIDEO_RGB24TOINDEX(rgb) \
|
||||
((((((rgb) >> 16) & 0xff) >> 5) << 5) | \
|
||||
(((((rgb) >> 8) & 0xff) >> 5) << 2) | \
|
||||
((((rgb) & 0xff) >> 6)))
|
||||
|
||||
/* system color */
|
||||
#define TX3912VIDEO_BLACK TX3912VIDEO_RGB24TOINDEX(0x000000)
|
||||
#define TX3912VIDEO_RED TX3912VIDEO_RGB24TOINDEX(0xff0000)
|
||||
#define TX3912VIDEO_GREEN TX3912VIDEO_RGB24TOINDEX(0x00ff00)
|
||||
#define TX3912VIDEO_YELLOW TX3912VIDEO_RGB24TOINDEX(0xffff00)
|
||||
#define TX3912VIDEO_BLUE TX3912VIDEO_RGB24TOINDEX(0x0000ff)
|
||||
#define TX3912VIDEO_MAGENTA TX3912VIDEO_RGB24TOINDEX(0xff00ff)
|
||||
#define TX3912VIDEO_CYAN TX3912VIDEO_RGB24TOINDEX(0x00ffff)
|
||||
#define TX3912VIDEO_WHITE TX3912VIDEO_RGB24TOINDEX(0xffffff)
|
||||
#define TX3912VIDEO_DARK_BLACK TX3912VIDEO_RGB24TOINDEX(0x000000)
|
||||
#define TX3912VIDEO_DARK_RED TX3912VIDEO_RGB24TOINDEX(0x800000)
|
||||
#define TX3912VIDEO_DARK_GREEN TX3912VIDEO_RGB24TOINDEX(0x008000)
|
||||
#define TX3912VIDEO_DARK_YELLOW TX3912VIDEO_RGB24TOINDEX(0x808000)
|
||||
#define TX3912VIDEO_DARK_BLUE TX3912VIDEO_RGB24TOINDEX(0x000080)
|
||||
#define TX3912VIDEO_DARK_MAGENTA TX3912VIDEO_RGB24TOINDEX(0x800080)
|
||||
#define TX3912VIDEO_DARK_CYAN TX3912VIDEO_RGB24TOINDEX(0x008080)
|
||||
#define TX3912VIDEO_DARK_WHITE TX3912VIDEO_RGB24TOINDEX(0x808080)
|
||||
|
||||
/*
|
||||
* Y = 0.2990 * R + 0.5870 * G + 0.1140 * B
|
||||
* U = -0.1690 * R - 0.3316 * G + 0.5000 * B
|
||||
* V = 0.5000 * R - 0.4186 * G - 0.0813 * B
|
||||
*/
|
||||
|
||||
/*
|
||||
* debug functions.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue