Support ARMADA XP.
This commit is contained in:
kiyohara
parent
cd5fb389c3
commit
cbe271df9d
@ -1,4 +1,4 @@
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/* $NetBSD: marvell_machdep.c,v 1.21 2012/12/12 00:03:11 matt Exp $ */
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/* $NetBSD: marvell_machdep.c,v 1.22 2013/09/30 12:57:53 kiyohara Exp $ */
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/*
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* Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi
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* All rights reserved.
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@ -25,7 +25,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.21 2012/12/12 00:03:11 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.22 2013/09/30 12:57:53 kiyohara Exp $");
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#include "opt_evbarm_boardtype.h"
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#include "opt_ddb.h"
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@ -65,6 +65,8 @@ __KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.21 2012/12/12 00:03:11 matt Ex
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#include <arm/marvell/mvsocvar.h>
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#include <arm/marvell/orionreg.h>
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#include <arm/marvell/kirkwoodreg.h>
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#include <arm/marvell/mv78xx0reg.h>
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#include <arm/marvell/armadaxpreg.h>
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#include <arm/marvell/mvsocgppvar.h>
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#include <evbarm/marvell/marvellreg.h>
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@ -173,10 +175,15 @@ read_ttb(void)
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#define _A(a) ((a) & ~L1_S_OFFSET)
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#define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1))
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static const struct pmap_devmap marvell_devmap[] = {
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static struct pmap_devmap marvell_devmap[] = {
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{
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MARVELL_INTERREGS_VBASE,
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#if (defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)) && \
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defined(ARMADAXP)
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_A(0x00000000),
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#else
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_A(MARVELL_INTERREGS_PBASE),
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#endif
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_S(MARVELL_INTERREGS_SIZE),
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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@ -185,9 +192,6 @@ static const struct pmap_devmap marvell_devmap[] = {
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{ 0, 0, 0, 0, 0 }
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};
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#undef _A
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#undef _S
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extern uint32_t *u_boot_args[];
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/*
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@ -214,9 +218,50 @@ initarm(void *arg)
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mvsoc_bootstrap(MARVELL_INTERREGS_VBASE);
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#if (defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)) && \
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defined(ARMADAXP)
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int i;
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for (i = 0; marvell_devmap[i].pd_size != 0; i++)
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if (marvell_devmap[i].pd_va == MARVELL_INTERREGS_VBASE) {
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marvell_devmap[i].pd_pa = _A(MARVELL_INTERREGS_PBASE);
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break;
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}
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#endif
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/* map some peripheral registers */
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pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap);
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/*
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* Heads up ... Setup the CPU / MMU / TLB functions
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*/
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if (set_cpufuncs())
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panic("cpu not recognized!");
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/*
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* U-Boot doesn't use the virtual memory.
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*
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* Physical Address Range Description
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* ----------------------- ----------------------------------
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* 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB)
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* 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB)
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* 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB)
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* 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB)
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* 0xf1000000 - 0xf10fffff SoC Internal Registers
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*/
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cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
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consinit();
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/* Talk to the user */
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#ifndef EVBARM_BOARDTYPE
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#define EVBARM_BOARDTYPE Marvell
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#endif
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#define BDSTR(s) _BDSTR(s)
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#define _BDSTR(s) #s
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printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n");
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/* Get ready for splfoo() */
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switch (mvsoc_model()) {
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#ifdef ORION
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@ -262,8 +307,8 @@ initarm(void *arg)
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case MARVELL_MV78XX0_MV78200:
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mv78xx0_intr_bootstrap();
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memtag = MV78XX0_TAG_PEX_MEM;
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iotag = MV78XX0_TAG_PEX_IO;
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memtag = MV78XX0_TAG_PEX0_MEM;
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iotag = MV78XX0_TAG_PEX0_IO;
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nwindow = MV78XX0_MLMB_NWINDOW;
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nremap = MV78XX0_MLMB_NREMAP;
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@ -271,6 +316,37 @@ initarm(void *arg)
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break;
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#endif /* MV78XX0 */
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#ifdef ARMADAXP
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case MARVELL_ARMADAXP_MV78130:
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case MARVELL_ARMADAXP_MV78160:
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case MARVELL_ARMADAXP_MV78230:
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case MARVELL_ARMADAXP_MV78260:
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case MARVELL_ARMADAXP_MV78460:
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armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE);
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memtag = ARMADAXP_TAG_PEX00_MEM;
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iotag = ARMADAXP_TAG_PEX00_IO;
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nwindow = ARMADAXP_MLMB_NWINDOW;
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nremap = ARMADAXP_MLMB_NREMAP;
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armadaxp_getclks();
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#ifdef L2CACHE_ENABLE
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/* Initialize L2 Cache */
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{
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extern int armadaxp_l2_init(bus_addr_t);
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(void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE);
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}
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#endif
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#ifdef AURORA_IO_CACHE_COHERENCY
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/* Initialize cache coherency */
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armadaxp_io_coherency_init();
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#endif
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break;
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#endif /* ARMADAXP */
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default:
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/* We can't output console here yet... */
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panic("unknown model...\n");
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@ -310,36 +386,6 @@ initarm(void *arg)
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}
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#endif
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/*
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* Heads up ... Setup the CPU / MMU / TLB functions
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*/
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if (set_cpufuncs())
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panic("cpu not recognized!");
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/*
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* U-Boot doesn't use the virtual memory.
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*
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* Physical Address Range Description
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* ----------------------- ----------------------------------
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* 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB)
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* 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB)
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* 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB)
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* 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB)
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* 0xf1000000 - 0xf10fffff SoC Internal Registers
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*/
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cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
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consinit();
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/* Talk to the user */
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#ifndef EVBARM_BOARDTYPE
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#define EVBARM_BOARDTYPE Marvell
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#endif
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#define BDSTR(s) _BDSTR(s)
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#define _BDSTR(s) #s
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printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n");
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/* copy command line U-Boot gave us, if args is valid. */
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if (u_boot_args[3] != 0) /* XXXXX: need more check?? */
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strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs));
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@ -398,7 +444,7 @@ consinit(void)
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uint32_t, int);
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if (mvuart_cnattach(&mvsoc_bs_tag,
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MARVELL_INTERREGS_VBASE + MVSOC_COM0_BASE,
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MARVELL_INTERREGS_PBASE + MVSOC_COM0_BASE,
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comcnspeed, mvTclk, comcnmode))
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panic("can't init serial console");
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}
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@ -418,9 +464,11 @@ marvell_device_register(device_t dev, void *aux)
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device_is_a(device_parent(dev), "mvsoc"))
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prop_dictionary_set_uint32(dict, "frequency", mvTclk);
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#endif
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if (device_is_a(dev, "gtidmac"))
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prop_dictionary_set_uint32(dict,
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"dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */
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#if NGTPCI > 0 && defined(ORION)
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if (device_is_a(dev, "gtpci")) {
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extern struct bus_space
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@ -498,6 +546,7 @@ marvell_device_register(device_t dev, void *aux)
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prop_dictionary_set(dict, "int2gpp", int2gpp);
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}
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#endif /* NGTPCI > 0 && defined(ORION) */
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#if NMVPEX > 0
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if (device_is_a(dev, "mvpex")) {
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#ifdef ORION
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@ -510,12 +559,20 @@ marvell_device_register(device_t dev, void *aux)
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kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag,
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kirkwood_pex1_io_bs_tag, kirkwood_pex1_mem_bs_tag;
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#endif
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extern struct arm32_pci_chipset arm32_mvpex0_chipset;
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#if defined(ORION) || defined(KIRKWOOD)
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extern struct arm32_pci_chipset arm32_mvpex1_chipset;
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#ifdef ARMADAXP
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extern struct bus_space
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armadaxp_pex00_io_bs_tag, armadaxp_pex00_mem_bs_tag,
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armadaxp_pex01_io_bs_tag, armadaxp_pex01_mem_bs_tag,
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armadaxp_pex02_io_bs_tag, armadaxp_pex02_mem_bs_tag,
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armadaxp_pex03_io_bs_tag, armadaxp_pex03_mem_bs_tag,
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armadaxp_pex2_io_bs_tag, armadaxp_pex2_mem_bs_tag,
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armadaxp_pex3_io_bs_tag, armadaxp_pex3_mem_bs_tag;
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int i;
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#endif
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extern struct arm32_pci_chipset
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arm32_mvpex0_chipset, arm32_mvpex1_chipset;
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struct marvell_attach_args *mva = aux;
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#endif
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struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag;
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struct arm32_pci_chipset *arm32_mvpex_chipset;
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prop_data_t io_bs_tag, mem_bs_tag, pc;
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@ -569,6 +626,85 @@ marvell_device_register(device_t dev, void *aux)
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break;
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#endif
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#ifdef ARMADAXP
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case MARVELL_ARMADAXP_MV78130:
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case MARVELL_ARMADAXP_MV78160:
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case MARVELL_ARMADAXP_MV78230:
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case MARVELL_ARMADAXP_MV78260:
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case MARVELL_ARMADAXP_MV78460:
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{
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extern struct arm32_pci_chipset
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arm32_mvpex2_chipset, arm32_mvpex3_chipset,
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arm32_mvpex4_chipset, arm32_mvpex5_chipset;
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const struct {
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bus_size_t offset;
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struct bus_space *io_bs_tag;
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struct bus_space *mem_bs_tag;
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struct arm32_pci_chipset *chipset;
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int iotag;
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int memtag;
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} mvpex_tags[] = {
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{ MVSOC_PEX_BASE,
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&armadaxp_pex00_io_bs_tag,
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&armadaxp_pex00_mem_bs_tag,
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&arm32_mvpex0_chipset,
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ARMADAXP_TAG_PEX00_IO,
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ARMADAXP_TAG_PEX00_MEM },
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{ ARMADAXP_PEX01_BASE,
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&armadaxp_pex01_io_bs_tag,
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&armadaxp_pex01_mem_bs_tag,
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&arm32_mvpex1_chipset,
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ARMADAXP_TAG_PEX01_IO,
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ARMADAXP_TAG_PEX01_MEM },
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{ ARMADAXP_PEX02_BASE,
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&armadaxp_pex02_io_bs_tag,
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&armadaxp_pex02_mem_bs_tag,
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&arm32_mvpex2_chipset,
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ARMADAXP_TAG_PEX02_IO,
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ARMADAXP_TAG_PEX02_MEM },
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{ ARMADAXP_PEX03_BASE,
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&armadaxp_pex03_io_bs_tag,
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&armadaxp_pex03_mem_bs_tag,
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&arm32_mvpex3_chipset,
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ARMADAXP_TAG_PEX03_IO,
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ARMADAXP_TAG_PEX03_MEM },
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{ ARMADAXP_PEX2_BASE,
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&armadaxp_pex2_io_bs_tag,
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&armadaxp_pex2_mem_bs_tag,
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&arm32_mvpex4_chipset,
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ARMADAXP_TAG_PEX2_IO,
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ARMADAXP_TAG_PEX2_MEM },
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{ ARMADAXP_PEX3_BASE,
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&armadaxp_pex3_io_bs_tag,
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&armadaxp_pex3_mem_bs_tag,
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&arm32_mvpex5_chipset,
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ARMADAXP_TAG_PEX3_IO,
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ARMADAXP_TAG_PEX3_MEM },
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{ 0, 0, 0, 0, 0 },
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};
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for (i = 0; mvpex_tags[i].offset != 0; i++) {
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if (mva->mva_offset != mvpex_tags[i].offset)
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continue;
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break;
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}
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if (mvpex_tags[i].offset == 0)
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return;
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mvpex_io_bs_tag = mvpex_tags[i].io_bs_tag;
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mvpex_mem_bs_tag = mvpex_tags[i].mem_bs_tag;
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arm32_mvpex_chipset = mvpex_tags[i].chipset;
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iotag = mvpex_tags[i].iotag;
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memtag = mvpex_tags[i].memtag;
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break;
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}
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#endif
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default:
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return;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: marvellreg.h,v 1.2 2013/05/01 12:32:46 rkujawa Exp $ */
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/* $NetBSD: marvellreg.h,v 1.3 2013/09/30 12:57:53 kiyohara Exp $ */
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/*
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* Copyright (c) 2007 KIYOHARA Takashi
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* All rights reserved.
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@ -33,12 +33,13 @@
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* that are used while bootstrapping.
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*/
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#define MARVELL_PEXMEM_PBASE 0xe0000000
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#if defined(ARMADAXP)
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#define MARVELL_INTERREGS_PBASE 0xd0000000
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#define MARVELL_PEXMEM_SIZE 0x01000000
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#else
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#if !defined(ARMADAXP)
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#define MARVELL_INTERREGS_PBASE 0xf1000000
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#define MARVELL_PEXMEM_SIZE 0x08000000
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#elif !defined(ORION) && !defined(KIRKWOOD) && !defined(MV78XX0)
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#define MARVELL_INTERREGS_PBASE 0xd0000000
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#else
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#define MARVELL_INTERREGS_PBASE marvell_interregs_pbase
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#endif
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#define MARVELL_INTERREGS_SIZE 0x00100000
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#define MARVELL_PEXIO_PBASE 0xf2000000
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@ -1,4 +1,4 @@
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/* $NetBSD: marvellvar.h,v 1.1 2010/10/03 06:03:10 kiyohara Exp $ */
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/* $NetBSD: marvellvar.h,v 1.2 2013/09/30 12:57:53 kiyohara Exp $ */
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/*
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* Copyright (c) 2007 KIYOHARA Takashi
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* All rights reserved.
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@ -37,4 +37,6 @@
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#define MARVELL_INTERREGS_VBASE 0xf1000000
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#define MARVELL_PEXIO_VBASE 0xf2000000
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extern bus_addr_t marvell_interregs_pbase;
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#endif /* _EVBARM_MARVELLVAR_H_ */
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