Cleanup freq setting a bit. Add a table of supported rates in ~200MHz steps
from 600MHz to 1608MHz, and let the cpu.frequency parameter match the closest available freq (without going over +50MHz). After updating APLL, wait for PLL lock. Do APLL changes with PLL mode set to slow, rather than the previous (and more complex) APLL/GPLL dance.
This commit is contained in:
jmcneill
parent
1f86325e8b
commit
cad7817261
@ -1,4 +1,4 @@
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/* $NetBSD: rockchip_board.c,v 1.8 2014/12/31 16:16:35 jmcneill Exp $ */
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/* $NetBSD: rockchip_board.c,v 1.9 2014/12/31 18:09:05 jmcneill Exp $ */
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/*-
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* Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca>
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@ -29,7 +29,7 @@
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#include "opt_rockchip.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rockchip_board.c,v 1.8 2014/12/31 16:16:35 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: rockchip_board.c,v 1.9 2014/12/31 18:09:05 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -83,6 +83,13 @@ rockchip_get_cru_bsh(bus_space_handle_t *pbsh)
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ROCKCHIP_CRU_OFFSET, ROCKCHIP_CRU_SIZE, pbsh);
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}
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static void
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rockchip_get_grf_bsh(bus_space_handle_t *pbsh)
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{
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bus_space_subregion(&rockchip_bs_tag, rockchip_core1_bsh,
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ROCKCHIP_GRF_OFFSET, ROCKCHIP_GRF_SIZE, pbsh);
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}
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static u_int
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rockchip_pll_get_rate(bus_size_t con0_reg, bus_size_t con1_reg)
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{
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@ -127,79 +134,67 @@ rockchip_apll_get_rate(void)
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return rockchip_pll_get_rate(CRU_APLL_CON0_REG, CRU_APLL_CON1_REG);
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}
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struct rk3188_apll_rate {
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u_int rate;
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u_int nr, nf, no;
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u_int core_div, core_periph_div, core_axi_div;
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u_int aclk_div, hclk_div, pclk_div, ahb2apb_div;
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};
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#define RK3188_RATE(_r, _nf, _no, _p, _a, _aclk, _hclk, _pclk, _ahb2apb) \
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{ .rate = (_r) * 1000000, .nr = 1, .nf = (_nf), .no = (_no), \
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.core_div = 1, .core_periph_div = (_p), .core_axi_div = (_a), \
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.aclk_div = (_aclk), .hclk_div = (_hclk), .pclk_div = (_pclk), \
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.ahb2apb_div = (_ahb2apb) }
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static const struct rk3188_apll_rate rk3188_apll_rates[] = {
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RK3188_RATE(1608, 67, 1, 8, 4, 4, 2, 4, 2),
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RK3188_RATE(1416, 59, 1, 8, 4, 4, 2, 4, 2),
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RK3188_RATE(1200, 50, 1, 8, 4, 4, 2, 4, 2),
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RK3188_RATE(1008, 42, 1, 8, 3, 3, 2, 4, 2),
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RK3188_RATE( 816, 68, 2, 8, 4, 3, 2, 4, 2),
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RK3188_RATE( 600, 50, 2, 4, 4, 3, 2, 4, 2),
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};
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#define RK3188_GRF_STATUS0_REG 0x00ac
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#define RK3188_GRF_STATUS0_APLL_LOCK __BIT(6)
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static u_int
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rk3188_apll_set_rate(u_int rate)
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{
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const struct rk3188_apll_rate *r = NULL;
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bus_space_tag_t bst = &rockchip_bs_tag;
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bus_space_handle_t bsh;
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bus_space_handle_t bsh, grf_bsh;
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uint32_t apll_con0, apll_con1, apll_con2, clksel0_con, clksel1_con;
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uint32_t reset_mask, reset;
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u_int no, nr, nf, core_div, core_periph_div, core_axi_div,
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aclk_div, hclk_div, pclk_div, ahb2apb_div;
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u_int cpu_aclk_div_con;
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const bool rk3188plus_p = rockchip_is_chip(ROCKCHIP_CHIPVER_RK3188PLUS);
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rockchip_get_cru_bsh(&bsh);
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rockchip_get_grf_bsh(&grf_bsh);
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#ifdef ROCKCHIP_CLOCK_DEBUG
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printf("%s: rate=%u rk3188plus_p=%d\n", __func__, rate, rk3188plus_p);
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#endif
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switch (rate) {
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case 1608000000:
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nr = 1;
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nf = 67;
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no = 1;
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core_div = 1;
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core_periph_div = 8;
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core_axi_div = 4;
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aclk_div = 4;
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hclk_div = 2;
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pclk_div = 4;
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ahb2apb_div = 2;
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break;
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case 1416000000:
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nr = 1;
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nf = 59;
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no = 1;
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core_div = 1;
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core_periph_div = 8;
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core_axi_div = 4;
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aclk_div = 4;
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hclk_div = 2;
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pclk_div = 4;
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ahb2apb_div = 2;
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break;
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case 1008000000:
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nr = 1;
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nf = 42;
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no = 1;
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core_div = 1;
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core_periph_div = 8;
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core_axi_div = 3;
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aclk_div = 3;
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hclk_div = 2;
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pclk_div = 4;
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ahb2apb_div = 2;
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break;
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case 600000000:
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nr = 1;
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nf = 50;
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no = 2;
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core_div = 1;
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core_periph_div = 4;
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core_axi_div = 4;
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aclk_div = 3;
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hclk_div = 2;
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pclk_div = 4;
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ahb2apb_div = 2;
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break;
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default:
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#ifdef ROCKCHIP_CLOCK_DEBUG
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printf("%s: unsupported rate %u\n", __func__, rate);
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#endif
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return EINVAL;
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/* Pick the closest rate (nearest 100MHz increment) */
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for (int i = 0; i < __arraycount(rk3188_apll_rates); i++) {
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u_int trate = rate / 1000000;
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u_int arate = ((rk3188_apll_rates[i].rate / 1000000) + 50)
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/ 100 * 100;
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if (arate <= trate) {
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r = &rk3188_apll_rates[i];
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break;
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}
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}
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if (r == NULL) {
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#ifdef ROCKCHIP_CLOCK_DEBUG
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printf("CPU: No matching rate found for %u MHz\n", rate);
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#endif
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return ENOENT;
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}
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printf("CPU: Set frequency to %u MHz...\n", r->rate / 1000000);
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if (rk3188plus_p) {
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reset_mask = CRU_PLL_CON3_RESET_MASK;
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@ -210,15 +205,15 @@ rk3188_apll_set_rate(u_int rate)
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}
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apll_con0 = CRU_PLL_CON0_CLKR_MASK | CRU_PLL_CON0_CLKOD_MASK;
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apll_con0 |= __SHIFTIN(no - 1, CRU_PLL_CON0_CLKOD);
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apll_con0 |= __SHIFTIN(nr - 1, CRU_PLL_CON0_CLKR);
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apll_con0 |= __SHIFTIN(r->no - 1, CRU_PLL_CON0_CLKOD);
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apll_con0 |= __SHIFTIN(r->nr - 1, CRU_PLL_CON0_CLKR);
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apll_con1 = CRU_PLL_CON1_CLKF_MASK;
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apll_con1 |= __SHIFTIN(nf - 1, CRU_PLL_CON1_CLKF);
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apll_con1 |= __SHIFTIN(r->nf - 1, CRU_PLL_CON1_CLKF);
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if (rk3188plus_p) {
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apll_con2 = CRU_PLL_CON2_BWADJ_MASK;
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apll_con2 |= __SHIFTIN(nf >> 1, CRU_PLL_CON2_BWADJ);
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apll_con2 |= __SHIFTIN(r->nf >> 1, CRU_PLL_CON2_BWADJ);
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} else {
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apll_con2 = 0;
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}
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@ -226,18 +221,19 @@ rk3188_apll_set_rate(u_int rate)
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clksel0_con = RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
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CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK |
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CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK;
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clksel0_con |= __SHIFTIN(core_div - 1,
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clksel0_con |= __SHIFTIN(r->core_div - 1,
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RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
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clksel0_con |= __SHIFTIN(ffs(core_periph_div) - 2,
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clksel0_con |= __SHIFTIN(ffs(r->core_periph_div) - 2,
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CRU_CLKSEL_CON0_CORE_PERI_DIV_CON);
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clksel0_con |= __SHIFTIN(aclk_div - 1,
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clksel0_con |= __SHIFTIN(r->aclk_div - 1,
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CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
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clksel1_con = CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
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CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK |
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CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK;
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CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK |
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RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK;
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switch (core_axi_div) {
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switch (r->core_axi_div) {
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case 1: cpu_aclk_div_con = 0; break;
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case 2: cpu_aclk_div_con = 1; break;
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case 3: cpu_aclk_div_con = 2; break;
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@ -245,12 +241,14 @@ rk3188_apll_set_rate(u_int rate)
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case 8: cpu_aclk_div_con = 4; break;
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default: panic("bad core_axi_div");
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}
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clksel1_con |= __SHIFTIN(ffs(ahb2apb_div) - 1,
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clksel1_con |= __SHIFTIN(ffs(r->ahb2apb_div) - 1,
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CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON);
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clksel1_con |= __SHIFTIN(ffs(hclk_div) - 1,
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clksel1_con |= __SHIFTIN(ffs(r->hclk_div) - 1,
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CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON);
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clksel1_con |= __SHIFTIN(ffs(pclk_div) - 1,
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clksel1_con |= __SHIFTIN(ffs(r->pclk_div) - 1,
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CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON);
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clksel1_con |= __SHIFTIN(cpu_aclk_div_con,
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RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
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#ifdef ROCKCHIP_CLOCK_DEBUG
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printf("before: APLL_CON0: %#x\n",
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@ -263,16 +261,10 @@ rk3188_apll_set_rate(u_int rate)
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bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(1)));
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#endif
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/* Set CPU clk src to GPLL */
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const u_int curcpufreq = rockchip_cpu_get_rate();
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const u_int gpllfreq = rockchip_gpll_get_rate();
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bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(0),
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RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK|
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CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL_MASK|
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__SHIFTIN(howmany(curcpufreq, gpllfreq) - 1,
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RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON)|
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CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL);
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bus_space_write_4(bst, bsh, CRU_MODE_CON_REG,
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CRU_MODE_CON_APLL_WORK_MODE_MASK |
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__SHIFTIN(CRU_MODE_CON_APLL_WORK_MODE_SLOW,
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CRU_MODE_CON_APLL_WORK_MODE));
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/* Power down */
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bus_space_write_4(bst, bsh, CRU_APLL_CON3_REG, reset_mask | reset);
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@ -283,28 +275,36 @@ rk3188_apll_set_rate(u_int rate)
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if (apll_con2)
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bus_space_write_4(bst, bsh, CRU_APLL_CON2_REG, apll_con2);
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/* Wait for PLL lock */
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for (volatile int i = 5000; i >= 0; i--)
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;
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/* Power up */
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bus_space_write_4(bst, bsh, CRU_APLL_CON3_REG, reset_mask);
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/* Wait for PLL lock */
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printf("CPU: Waiting for PLL lock...\n");
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for (volatile int i = 50000; i >= 0; i--)
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;
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int retry = ROCKCHIP_REF_FREQ;
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while (--retry > 0) {
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uint32_t status = bus_space_read_4(bst, grf_bsh,
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RK3188_GRF_STATUS0_REG);
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if (status & RK3188_GRF_STATUS0_APLL_LOCK)
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break;
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for (volatile int i = 1000; i >= 0; i--)
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;
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}
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printf("CPU: PLL lock %s\n", retry == 0 ? "timeout!" : "OK");
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/* Update CLKSEL regs */
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bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(0), clksel0_con);
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bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(1), clksel1_con);
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/* Set CPU clk src to APLL */
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bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(0),
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CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL_MASK);
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bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(0),
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RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK |
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__SHIFTIN(cpu_aclk_div_con,
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RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON));
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/* Slow -> Normal mode */
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bus_space_write_4(bst, bsh, CRU_MODE_CON_REG,
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CRU_MODE_CON_APLL_WORK_MODE_MASK |
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__SHIFTIN(CRU_MODE_CON_APLL_WORK_MODE_NORMAL,
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CRU_MODE_CON_APLL_WORK_MODE));
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#ifdef ROCKCHIP_CLOCK_DEBUG
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printf("after: APLL_CON0: %#x\n",
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