complete the driver/bus frontend split and make sure the driver can deal with
both PCI and VLB variants of the chip
This commit is contained in:
macallan
parent
3346190448
commit
ca8e7514cb
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@ -1,4 +1,4 @@
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/* $NetBSD: ct65550.c,v 1.1 2011/02/09 21:18:04 macallan Exp $ */
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/* $NetBSD: ct65550.c,v 1.2 2011/03/23 04:02:43 macallan Exp $ */
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/*
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* Copyright (c) 2006 Michael Lorenz
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ct65550.c,v 1.1 2011/02/09 21:18:04 macallan Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ct65550.c,v 1.2 2011/03/23 04:02:43 macallan Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -130,13 +130,13 @@ struct wsdisplay_accessops chipsfb_accessops = {
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static inline void
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chipsfb_write32(struct chipsfb_softc *sc, uint32_t reg, uint32_t val)
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{
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bus_space_write_4(sc->sc_fbt, sc->sc_fbh, reg, val);
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bus_space_write_4(sc->sc_memt, sc->sc_mmregh, reg, val);
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}
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static inline uint32_t
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chipsfb_read32(struct chipsfb_softc *sc, uint32_t reg)
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{
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return bus_space_read_4(sc->sc_fbt, sc->sc_fbh, reg);
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return bus_space_read_4(sc->sc_memt, sc->sc_mmregh, reg);
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}
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static inline void
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@ -203,10 +203,8 @@ chipsfb_do_attach(struct chipsfb_softc *sc)
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#ifdef CHIPSFB_DEBUG
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printf(prop_dictionary_externalize(dict));
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#endif
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chipsfb_init(sc);
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/* we should read these from the chip instead of depending on OF */
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width = height = -1;
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/* detect panel size */
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@ -218,7 +216,12 @@ chipsfb_do_attach(struct chipsfb_softc *sc)
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height |= (chipsfb_read_indexed(sc, CT_FP_INDEX, FP_VERT_OVERFLOW_1)
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& 0x0f) << 8;
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height++;
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aprint_verbose("Panel size: %d x %d\n", width, height);
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if ((width < 640) || ( width > 1280) || (height < 480) ||
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(height > 1024)) {
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/* no sane values in the panel registers */
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width = height = -1;
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} else
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aprint_verbose("Panel size: %d x %d\n", width, height);
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if (!prop_dictionary_get_uint32(dict, "width", &sc->width))
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sc->width = width;
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@ -255,9 +258,6 @@ chipsfb_do_attach(struct chipsfb_softc *sc)
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* since we're not the console we can postpone the rest
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* until someone actually allocates a screen for us
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*/
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#ifdef notyet
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chipsfb_set_videomode(sc, &videomode_list[0]);
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#endif
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}
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rasops_unpack_attr(defattr, &fg, &bg, &ul);
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@ -269,7 +269,7 @@ chipsfb_do_attach(struct chipsfb_softc *sc)
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aprint_normal_dev(sc->sc_dev, "%d MB aperture, %d MB VRAM at 0x%08x\n",
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(u_int)(sc->sc_fbsize >> 20),
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sc->memsize >> 20, (u_int)sc->sc_fb);
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(int)sc->memsize >> 20, (u_int)sc->sc_fb);
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#ifdef CHIPSFB_DEBUG
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aprint_debug("fb: %08lx\n", (ulong)ri->ri_bits);
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#endif
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@ -644,7 +644,7 @@ chipsfb_feed(struct chipsfb_softc *sc, int count, uint8_t *data)
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bork = data[i];
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latch |= (bork << shift);
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if (shift == 24) {
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chipsfb_write32(sc, CT_OFF_DATA, latch);
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chipsfb_write32(sc, CT_OFF_DATA - CT_OFF_BITBLT, latch);
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latch = 0;
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shift = 0;
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} else
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@ -652,12 +652,12 @@ chipsfb_feed(struct chipsfb_softc *sc, int count, uint8_t *data)
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}
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if (shift != 0) {
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chipsfb_write32(sc, CT_OFF_DATA, latch);
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chipsfb_write32(sc, CT_OFF_DATA - CT_OFF_BITBLT, latch);
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}
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/* apparently the chip wants 64bit-aligned data or it won't go idle */
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if ((count + 3) & 0x04) {
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chipsfb_write32(sc, CT_OFF_DATA, 0);
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chipsfb_write32(sc, CT_OFF_DATA - CT_OFF_BITBLT, 0);
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}
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#ifdef CHIPSFB_WAIT
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chipsfb_wait_idle(sc);
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@ -760,10 +760,13 @@ chipsfb_mmap(void *v, void *vs, off_t offset, int prot)
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struct chipsfb_softc *sc = vd->cookie;
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paddr_t pa;
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if (sc->sc_mmap != NULL)
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return sc->sc_mmap(v, vs, offset, prot);
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/* 'regular' framebuffer mmap()ing */
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if (offset < sc->memsize) {
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pa = bus_space_mmap(sc->sc_fbt, offset, 0, prot,
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BUS_SPACE_MAP_LINEAR);
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pa = bus_space_mmap(sc->sc_memt, offset, 0, prot,
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BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE);
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return pa;
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}
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@ -809,7 +812,7 @@ chipsfb_init_screen(void *cookie, struct vcons_screen *scr,
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ri->ri_stride = sc->width;
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ri->ri_flg = RI_CENTER | RI_FULLCLEAR;
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ri->ri_bits = bus_space_vaddr(sc->sc_fbt, sc->sc_fbh);
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ri->ri_bits = bus_space_vaddr(sc->sc_memt, sc->sc_fbh);
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#ifdef CHIPSFB_DEBUG
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aprint_debug("addr: %08lx\n", (ulong)ri->ri_bits);
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@ -866,14 +869,14 @@ chipsfb_probe_vram(struct chipsfb_softc *sc)
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* if what we wrote to 0 is left untouched. Max. fb size is 4MB so
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* we voluntarily stop there.
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*/
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chipsfb_write32(sc, 0, 0xf0f0f0f0);
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chipsfb_write32(sc, ofs, 0x0f0f0f0f);
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while ((chipsfb_read32(sc, 0) == 0xf0f0f0f0) &&
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(chipsfb_read32(sc, ofs) == 0x0f0f0f0f) &&
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bus_space_write_4(sc->sc_memt, sc->sc_fbh, 0, 0xf0f0f0f0);
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bus_space_write_4(sc->sc_memt, sc->sc_fbh, ofs, 0x0f0f0f0f);
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while ((bus_space_read_4(sc->sc_memt, sc->sc_fbh, 0) == 0xf0f0f0f0) &&
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(bus_space_read_4(sc->sc_memt, sc->sc_fbh, ofs) == 0x0f0f0f0f) &&
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(ofs < 0x00400000)) {
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ofs += 0x00080000;
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chipsfb_write32(sc, ofs, 0x0f0f0f0f);
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bus_space_write_4(sc->sc_memt, sc->sc_fbh, ofs, 0x0f0f0f0f);
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}
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return ofs;
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@ -1,4 +1,4 @@
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/* $NetBSD: ct65550reg.h,v 1.1 2011/02/09 21:18:04 macallan Exp $ */
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/* $NetBSD: ct65550reg.h,v 1.2 2011/03/23 04:02:43 macallan Exp $ */
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/*
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* Copyright 2006 by Michael Lorenz.
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@ -62,15 +62,15 @@
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#define CT_OFF_BE 0x00800000
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/* blitter registers */
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#define CT_BLT_STRIDE CT_OFF_BITBLT
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#define CT_BLT_STRIDE 0x00000000
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/*
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* upper 16 bit are destination stride in bytes
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* lower 16 bit are source stride in bytes
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*/
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#define CT_BLT_BG CT_OFF_BITBLT + 0x04
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#define CT_BLT_FG CT_OFF_BITBLT + 0x08
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#define CT_BLT_EXPCTL CT_OFF_BITBLT + 0x0c /* expansion control */
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#define CT_BLT_BG 0x04
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#define CT_BLT_FG 0x08
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#define CT_BLT_EXPCTL 0x0c /* expansion control */
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#define LEFT_CLIPPING_MSK 0x0000003f
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#define MONO_RIGHT_CLIPPING_MSK 0x00003f00
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#define MONO_INITIAL_DISCARD 0x003f0000
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@ -82,7 +82,7 @@
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#define MONO_SRC_ALIGN_LONGLONG 0x05000000
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#define MONO_SELECT_ALT_FG_BG 0x08000000 /* use CT_SRC_EXP_* */
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#define CT_BLT_CONTROL CT_OFF_BITBLT + 0x10
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#define CT_BLT_CONTROL 0x10
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#define BLT_ROP_MASK 0x000000ff
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#define BLT_START_RIGHT 0x00000100 /* 0 for start left */
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#define BLT_START_BOTTOM 0x00000200 /* 0 for start top */
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@ -101,18 +101,18 @@
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#define ROP_NOT_DST 0x55
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#define ROP_PAT 0xf0
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#define CT_BLT_PATTERN CT_OFF_BITBLT + 0x14 /* address in vram */
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#define CT_BLT_SRCADDR CT_OFF_BITBLT + 0x18
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#define CT_BLT_DSTADDR CT_OFF_BITBLT + 0x1c
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#define CT_BLT_PATTERN 0x14 /* address in vram */
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#define CT_BLT_SRCADDR 0x18
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#define CT_BLT_DSTADDR 0x1c
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#define CT_BLT_SIZE CT_OFF_BITBLT + 0x20 /* width and height */
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#define CT_BLT_SIZE 0x20 /* width and height */
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/*
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* upper 16 bit are destination height
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* lower 16 bit are destination width in bytes
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*/
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#define CT_SRC_EXP_BG CT_OFF_BITBLT + 0x24
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#define CT_SRC_EXP_FG CT_OFF_BITBLT + 0x28
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#define CT_SRC_EXP_BG 0x24
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#define CT_SRC_EXP_FG 0x28
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/* extension registers ( via CT_CONF */
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#define XR_VENDOR_LO 0x00
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@ -1,4 +1,4 @@
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/* $NetBSD: ct65550var.h,v 1.1 2011/02/09 21:18:04 macallan Exp $ */
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/* $NetBSD: ct65550var.h,v 1.2 2011/03/23 04:02:43 macallan Exp $ */
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/*
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* Copyright (c) 2006 Michael Lorenz
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@ -40,19 +40,16 @@ struct chipsfb_softc {
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bus_space_tag_t sc_memt;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_memh;
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bus_space_tag_t sc_fbt;
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bus_space_tag_t sc_ioregt;
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bus_space_handle_t sc_fbh;
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bus_space_handle_t sc_mmregh;
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bus_space_handle_t sc_ioregh;
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bus_addr_t sc_fb, sc_ioreg;
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bus_addr_t sc_fb;
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bus_size_t sc_fbsize, sc_ioregsize;
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int (*sc_ioctl)(void *, void *, u_long, void *, int, struct lwp *);
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paddr_t (*chipsfb_mmap)(void *, void *, off_t, int);
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paddr_t (*sc_mmap)(void *, void *, off_t, int);
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void *sc_ih;
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size_t memsize;
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@ -1,4 +1,4 @@
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/* $NetBSD: chipsfb.c,v 1.26 2011/02/09 21:21:32 macallan Exp $ */
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/* $NetBSD: chipsfb.c,v 1.27 2011/03/23 04:02:43 macallan Exp $ */
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/*
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* Copyright (c) 2006 Michael Lorenz
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@ -31,7 +31,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: chipsfb.c,v 1.26 2011/02/09 21:21:32 macallan Exp $");
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__KERNEL_RCSID(0, "$NetBSD: chipsfb.c,v 1.27 2011/03/23 04:02:43 macallan Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -99,7 +99,8 @@ chipsfb_pci_attach(device_t parent, device_t self, void *aux)
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screg = pci_conf_read(scp->sc_pc, scp->sc_pcitag,
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PCI_COMMAND_STATUS_REG);
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screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
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pci_conf_write(scp->sc_pc, scp->sc_pcitag,PCI_COMMAND_STATUS_REG, screg);
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pci_conf_write(scp->sc_pc, scp->sc_pcitag, PCI_COMMAND_STATUS_REG,
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screg);
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pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
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aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
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@ -111,12 +112,23 @@ chipsfb_pci_attach(device_t parent, device_t self, void *aux)
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sc->sc_memt = pa->pa_memt;
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sc->sc_iot = pa->pa_iot;
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sc->sc_ioctl = chipsfb_pci_ioctl;
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sc->sc_mmap = NULL;
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/* the framebuffer */
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if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_MEM,
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BUS_SPACE_MAP_LINEAR,
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&sc->sc_fbt, &sc->sc_fbh, &sc->sc_fb, &sc->sc_fbsize)) {
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aprint_error_dev(sc->sc_dev, "failed to map the frame buffer.\n");
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sc->sc_fb = (pci_conf_read(scp->sc_pc, scp->sc_pcitag, PCI_BAR0) &
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~PCI_MAPREG_MEM_TYPE_MASK);
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sc->sc_fbsize = 0x01000000; /* 16MB aperture */
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if (bus_space_map(sc->sc_memt, sc->sc_fb, 0x400000,
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BUS_SPACE_MAP_LINEAR, &sc->sc_fbh)) {
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aprint_error_dev(sc->sc_dev,
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"failed to map the frame buffer.\n");
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}
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if (bus_space_map(sc->sc_memt, sc->sc_fb + CT_OFF_BITBLT, 0x20000,
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BUS_SPACE_MAP_LINEAR, &sc->sc_mmregh)) {
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aprint_error_dev(sc->sc_dev,
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"failed to map MMIO registers.\n");
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}
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/* IO-mapped registers */
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