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Overhaul the interface to pci_configure_bus(): 

- Don't expose how PCI bus configuration resource management is implemented.
  Provide a new resource provider API:

  ==> pciconf_resource_init() -- Initialize a PCI configuration resources
      container.
  ==> pciconf_resource_add() -- Add a PCI configuration resource to the
      container (I/O, MEM, or prefetchable MEM).  Multiple resources of
      each type may be added.
  ==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
      container once the bus has been configured.

  This is much easier to use than the previous method of providing an
  extent map for each kind of resource, and works better for e.g. ACPI
  platforms that provide potentially multiple PCI resources in tables
  provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
  rather than extent maps.
This commit is contained in:
thorpej 2020-07-07 03:38:45 +00:00
parent 8635cb3dd6
commit ca8ce3aeb1
49 changed files with 913 additions and 831 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

100
sys/arch/algor/dev/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.27 2020/06/14 01:40:02 chs Exp $ */
/* $NetBSD: mainbus.c,v 1.28 2020/07/07 03:38:45 thorpej Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.27 2020/06/14 01:40:02 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.28 2020/07/07 03:38:45 thorpej Exp $");
#include "opt_algor_p4032.h"
#include "opt_algor_p5064.h"
@ -42,7 +42,6 @@ __KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.27 2020/06/14 01:40:02 chs Exp $");
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <sys/reboot.h>
#include <sys/systm.h>
@ -98,6 +97,13 @@ struct mainbusdev mainbusdevs[] = {
{ NULL, 0, 0 },
};
/* Reserve the bottom 64K of the I/O space for ISA devices. */
#define PCI_IO_START 0x00010000
#define PCI_IO_END 0x000effff
#define PCI_MEM_START 0x01000000
#define PCI_MEM_END 0x07ffffff
#define PCI_CHIPSET &p4032_configuration.ac_pc
#endif /* ALGOR_P4032 */
#if defined(ALGOR_P5064)
@ -110,6 +116,19 @@ struct mainbusdev mainbusdevs[] = {
{ NULL, 0, 0 },
};
/*
* Reserve the bottom 512K of the I/O space for ISA devices.
* According to the PMON sources, this is a work-around for
* a bug in the ISA bridge.
*/
#define PCI_IO_START 0x00080000
#define PCI_IO_END 0x00ffffff
#define PCI_MEM_START 0x01000000
#define PCI_MEM_END 0x07ffffff
#define PCI_IDE_DEV 2
#define PCI_IDE_FUNC 1
#define PCI_CHIPSET &p5064_configuration.ac_pc
#endif /* ALGOR_P5064 */
#if defined(ALGOR_P6032)
@ -122,8 +141,20 @@ struct mainbusdev mainbusdevs[] = {
{ NULL, 0, 0 },
};
/* Reserve the bottom 64K of the I/O space for ISA devices. */
#define PCI_IO_START 0x00010000
#define PCI_IO_END 0x000effff
#define PCI_MEM_START 0x01000000
#define PCI_MEM_END 0x0affffff
#define PCI_IDE_DEV 17
#define PCI_IDE_FUNC 1
#define PCI_CHIPSET &p6032_configuration.ac_pc
#endif /* ALGOR_P6032 */
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
int
mainbus_match(device_t parent, cfdata_t cf, void *aux)
{
@ -140,63 +171,22 @@ mainbus_attach(device_t parent, device_t self, void *aux)
struct mainbus_attach_args ma;
struct mainbusdev *md;
bus_space_tag_t st;
#if defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext, *memext;
pci_chipset_tag_t pc;
#if defined(PCI_NETBSD_ENABLE_IDE)
pcitag_t idetag;
pcireg_t idetim;
#endif
#endif
mainbus_found = 1;
printf("\n");
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
#if defined(ALGOR_P4032)
/*
* Reserve the bottom 64K of the I/O space for ISA devices.
*/
ioext = extent_create("pciio", 0x00010000, 0x000effff,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", 0x01000000, 0x07ffffff,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pc = &p4032_configuration.ac_pc;
#elif defined(ALGOR_P5064)
/*
* Reserve the bottom 512K of the I/O space for ISA devices.
* According to the PMON sources, this is a work-around for
* a bug in the ISA bridge.
*/
ioext = extent_create("pciio", 0x00080000, 0x00ffffff,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", 0x01000000, 0x07ffffff,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
pc = &p5064_configuration.ac_pc;
#if defined(PCI_NETBSD_ENABLE_IDE)
idetag = pci_make_tag(pc, 0, 2, 1);
#endif
#elif defined(ALGOR_P6032)
/*
* Reserve the bottom 64K of the I/O space for ISA devices.
*/
ioext = extent_create("pciio", 0x00010000, 0x000effff,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", 0x01000000, 0x0affffff,
NULL, 0, EX_WAITOK);
pc = &p6032_configuration.ac_pc;
#if defined(PCI_NETBSD_ENABLE_IDE)
idetag = pci_make_tag(pc, 0, 17, 1);
#endif
#endif /* ALGOR_P4032 || ALGOR_P5064 || ALGOR_P6032 */
pci_configure_bus(pc, ioext, memext, NULL, 0, mips_cache_info.mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pci_configure_bus(PCI_CHIPSET, pcires, 0,
mips_cache_info.mci_dcache_align);
pciconf_resource_fini(pcires);
#if defined(PCI_NETBSD_ENABLE_IDE)
/*
@ -206,12 +196,14 @@ mainbus_attach(device_t parent, device_t self, void *aux)
* except for the ENABLE bits -- the `pciide' driver will
* properly configure it later.
*/
idetim = 0;
pcitag_t idetag = pci_make_tag(PCI_CHIPSET, 0, PCI_IDE_DEV,
PCI_IDE_FUNC);
pcireg_t idetim = 0;
if (PCI_NETBSD_ENABLE_IDE & 0x01)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 0);
if (PCI_NETBSD_ENABLE_IDE & 0x02)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1);
pci_conf_write(pc, idetag, PIIX_IDETIM, idetim);
pci_conf_write(PCI_CHIPSET, idetag, PIIX_IDETIM, idetim);
#endif
#endif /* NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) */

20
sys/arch/amiga/pci/em4k.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: em4k.c,v 1.5 2020/06/14 01:40:02 chs Exp $ */
/* $NetBSD: em4k.c,v 1.6 2020/07/07 03:38:45 thorpej Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@ -38,7 +38,6 @@
#include <sys/errno.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/extent.h>
#include <sys/kmem.h>
#include <uvm/uvm_extern.h>
@ -243,24 +242,23 @@ em4k_callback(device_t self) {
static void
em4k_pci_configure(struct em4k_softc *sc)
{
struct extent *ioext, *memext;
struct pciconf_resources *pcires;
pcires = pciconf_resource_init();
/* I/O addresses are relative to I/O space address. */
ioext = extent_create("em4kio", 0, EM4K_IO_SIZE,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 0, EM4K_IO_SIZE);
/*
* Memory space addresses are absolute (and keep in mind that
* they are in a separate address space.
*/
memext = extent_create("em4kmem", kvtop((void*) sc->pci_mem_win.base),
kvtop((void*) sc->pci_mem_win.base) + sc->pci_mem_win_size,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
kvtop((void*) sc->pci_mem_win.base), sc->pci_mem_win_size);
pci_configure_bus(&sc->apc, ioext, memext, NULL, 0, CACHELINE_SIZE);
pci_configure_bus(&sc->apc, pcires, 0, CACHELINE_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
}
#endif /* PCI_NETBSD_CONFIGURE */

20
sys/arch/amiga/pci/empb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: empb.c,v 1.12 2020/06/14 01:40:02 chs Exp $ */
/* $NetBSD: empb.c,v 1.13 2020/07/07 03:38:45 thorpej Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@ -38,7 +38,6 @@
#include <sys/errno.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/extent.h>
#include <sys/kmem.h>
#include <uvm/uvm_extern.h>
@ -173,9 +172,6 @@ empb_callback(device_t self) {
struct empb_softc *sc;
pci_chipset_tag_t pc;
struct pcibus_attach_args pba;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif /* PCI_NETBSD_CONFIGURE */
sc = device_private(self);
pc = &sc->apc;
@ -233,16 +229,16 @@ empb_callback(device_t self) {
sc->apc.cookie = sc;
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("empbio", 0, EMPB_BRIDGE_SIZE,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
memext = extent_create("empbmem", EMPB_MEM_BASE, EMPB_MEM_END,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
0, EMPB_BRIDGE_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
EMPB_MEM_BASE, EMPB_MEM_SIZE);
pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE);
pci_configure_bus(pc, pcires, 0, CACHELINE_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */

7
sys/arch/amiga/pci/empbreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: empbreg.h,v 1.6 2013/01/29 00:49:43 rkujawa Exp $ */
/* $NetBSD: empbreg.h,v 1.7 2020/07/07 03:38:45 thorpej Exp $ */
/*-
* Copyright (c) 2012, 2013 The NetBSD Foundation, Inc.
@ -85,8 +85,9 @@
#define EMPB_WINDOW_MASK_8M 0xFF80
#define EMPB_WINDOW_MASK_4M 0xFFC0
#define EMPB_MEM_BASE 0x80000000
#define EMPB_MEM_END 0xA0000000
#define EMPB_MEM_BASE 0x80000000U
#define EMPB_MEM_END 0x9FFFFFFFU
#define EMPB_MEM_SIZE ((EMPB_MEM_END - EMPB_MEM_BASE) + 1)
#define EMPB_PM_OFF 0x40 /* power management register */
#define EMPB_PM_PSU_SHUTDOWN 0x0

21
sys/arch/amiga/pci/mppb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mppb.c,v 1.9 2020/06/14 01:40:02 chs Exp $ */
/* $NetBSD: mppb.c,v 1.10 2020/07/07 03:38:45 thorpej Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
@ -38,7 +38,6 @@
#include <sys/errno.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/extent.h>
#include <sys/kmem.h>
#include <uvm/uvm_extern.h>
@ -112,9 +111,6 @@ mppb_attach(device_t parent, device_t self, void *aux)
struct pcibus_attach_args pba;
struct zbus_args *zap;
pci_chipset_tag_t pc;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif /* PCI_NETBSD_CONFIGURE */
zap = aux;
sc = device_private(self);
@ -166,18 +162,19 @@ mppb_attach(device_t parent, device_t self, void *aux)
sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt;
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("mppbio", MPPB_IO_BASE,
MPPB_IO_BASE + MPPB_IO_SIZE, NULL, 0, EX_WAITOK);
memext = extent_create("mppbmem", MPPB_MEM_BASE,
MPPB_MEM_BASE + MPPB_MEM_SIZE, NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
MPPB_IO_BASE, MPPB_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
MPPB_MEM_BASE, MPPB_MEM_SIZE);
#ifdef MPPB_DEBUG
aprint_normal("mppb: reconfiguring the bus!\n");
#endif /* MPPB_DEBUG */
pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE);
pci_configure_bus(pc, pcires, 0, CACHELINE_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */
pba.pba_iot = &(sc->pci_io_area);

20
sys/arch/amiga/pci/p5pb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: p5pb.c,v 1.16 2020/06/14 01:40:02 chs Exp $ */
/* $NetBSD: p5pb.c,v 1.17 2020/07/07 03:38:45 thorpej Exp $ */
/*-
* Copyright (c) 2011, 2012 The NetBSD Foundation, Inc.
@ -37,7 +37,6 @@
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/kmem.h>
#include <sys/extent.h>
#include <uvm/uvm_extern.h>
@ -489,24 +488,23 @@ p5pb_cvppc_probe(struct p5pb_softc *sc)
bool
p5pb_bus_reconfigure(struct p5pb_softc *sc)
{
struct extent *ioext, *memext;
pci_chipset_tag_t pc;
pc = &sc->apc;
ioext = extent_create("p5pbio", 0, P5BUS_PCI_IO_SIZE, NULL, 0,
EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
0, P5BUS_PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
sc->pci_mem_lowest, sc->pci_mem_highest - sc->pci_mem_lowest);
memext = extent_create("p5pbmem", sc->pci_mem_lowest,
sc->pci_mem_highest - 1, NULL, 0, EX_WAITOK);
#ifdef P5PB_DEBUG
aprint_normal("p5pb: reconfiguring the bus!\n");
#endif /* P5PB_DEBUG */
pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE);
pci_configure_bus(pc, pcires, 0, CACHELINE_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
return true; /* TODO: better error handling */
}

5
sys/arch/arc/include/pci_machdep.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pci_machdep.h,v 1.11 2014/03/29 19:28:26 christos Exp $ */
/* $NetBSD: pci_machdep.h,v 1.12 2020/07/07 03:38:45 thorpej Exp $ */
/* NetBSD: pci_machdep.h,v 1.3 1999/03/19 03:40:46 cgd Exp */
/*
@ -70,9 +70,6 @@ struct arc_pci_chipset {
int, int *);
int (*pc_conf_hook)(pci_chipset_tag_t, int, int, int,
pcireg_t);
struct extent *pc_memext;
struct extent *pc_ioext;
};
/*

25
sys/arch/arc/pci/necpb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: necpb.c,v 1.44 2020/06/14 01:40:02 chs Exp $ */
/* $NetBSD: necpb.c,v 1.45 2020/07/07 03:38:45 thorpej Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@ -61,7 +61,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: necpb.c,v 1.44 2020/06/14 01:40:02 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: necpb.c,v 1.45 2020/07/07 03:38:45 thorpej Exp $");
#include "opt_pci.h"
@ -137,6 +137,14 @@ struct necpb_context necpb_main_context;
static long necpb_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)];
static long necpb_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)];
#define PCI_IO_START 0x00100000
#define PCI_IO_END 0x01ffffff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START 0x08000000
#define PCI_MEM_END 0x3fffffff
#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
static int
necpbmatch(device_t parent, cfdata_t cf, void *aux)
{
@ -243,12 +251,13 @@ necpbattach(device_t parent, device_t self, void *aux)
pc = &sc->sc_ncp->nc_pc;
#ifdef PCI_NETBSD_CONFIGURE
pc->pc_ioext = extent_create("necpbio", 0x00100000, 0x01ffffff,
NULL, 0, EX_WAITOK);
pc->pc_memext = extent_create("necpbmem", 0x08000000, 0x3fffffff,
NULL, 0, EX_WAITOK);
pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
mips_cache_info.mci_dcache_align);
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
pci_configure_bus(pc, pcires, 0, mips_cache_info.mci_dcache_align);
pciconf_resource_fini(pcires);
#endif
out32(RD94_SYS_PCI_INTMASK, 0xf);

16
sys/arch/arm/broadcom/bcm53xx_pax.c
View File

@ -34,12 +34,11 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(1, "$NetBSD: bcm53xx_pax.c,v 1.18 2020/06/14 01:40:02 chs Exp $");
__KERNEL_RCSID(1, "$NetBSD: bcm53xx_pax.c,v 1.19 2020/07/07 03:38:45 thorpej Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/intr.h>
#include <sys/kmem.h>
#include <sys/systm.h>
@ -346,13 +345,12 @@ bcmpax_ccb_attach(device_t parent, device_t self, void *aux)
bcmpax_write_4(sc, PCIE_OMAP_1_LOWER, base1 | 1);
}
struct extent *memext = extent_create("pcimem", base,
base + size, NULL, 0, EX_WAITOK);
error = pci_configure_bus(&sc->sc_pc,
NULL, memext, NULL, 0, arm_pcache.dcache_line_size);
extent_destroy(memext);
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
base, size);
error = pci_configure_bus(&sc->sc_pc, pcires,
0, arm_pcache.dcache_line_size);
pciconf_resource_fini(pcires);
if (error) {
aprint_normal_dev(self, "configuration failed\n");

67
sys/arch/arm/fdt/pcihost_fdt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pcihost_fdt.c,v 1.16 2020/06/14 01:40:02 chs Exp $ */
/* $NetBSD: pcihost_fdt.c,v 1.17 2020/07/07 03:38:45 thorpej Exp $ */
/*-
* Copyright (c) 2018 Jared D. McNeill <jmcneill@invisible.ca>
@ -27,13 +27,12 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.16 2020/06/14 01:40:02 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.17 2020/07/07 03:38:45 thorpej Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/intr.h>
#include <sys/kernel.h>
#include <sys/kmem.h>
@ -224,10 +223,9 @@ pcihost_init(pci_chipset_tag_t pc, void *priv)
static int
pcihost_config(struct pcihost_softc *sc)
{
struct extent *ioext = NULL, *memext = NULL, *pmemext = NULL;
const u_int *ranges;
u_int probe_only;
int error, len;
int error, len, type;
bool swap;
struct pcih_bus_space * const pibs = &sc->sc_io;
@ -265,6 +263,8 @@ pcihost_config(struct pcihost_softc *sc)
swap = true;
}
struct pciconf_resources *pcires = pciconf_resource_init();
/*
* Each entry in the ranges table contains:
* - bus address (3 cells)
@ -276,9 +276,9 @@ pcihost_config(struct pcihost_softc *sc)
#define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o])
#define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1]))
const uint32_t phys_hi = DECODE32(ranges, 0);
const uint64_t bus_phys = DECODE64(ranges, 1);
uint64_t bus_phys = DECODE64(ranges, 1);
const uint64_t cpu_phys = DECODE64(ranges, 3);
const uint64_t size = DECODE64(ranges, 5);
uint64_t size = DECODE64(ranges, 5);
#undef DECODE32
#undef DECODE64
@ -297,18 +297,21 @@ pcihost_config(struct pcihost_softc *sc)
pibs->ranges[pibs->nranges].bbus = cpu_phys;
pibs->ranges[pibs->nranges].size = size;
++pibs->nranges;
if (ioext != NULL) {
aprint_error_dev(sc->sc_dev, "ignoring duplicate IO space range\n");
continue;
}
ioext = extent_create("pciio", bus_phys, bus_phys + size - 1, NULL, 0, EX_WAITOK);
aprint_verbose_dev(sc->sc_dev,
"IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n",
bus_phys, size, cpu_phys);
/* reserve a PC-like legacy IO ports range, perhaps for access to VGA registers */
if (bus_phys == 0 && size >= 0x10000)
extent_alloc_region(ioext, 0, 0x1000, EX_WAITOK);
sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY;
/*
* Reserve a PC-like legacy IO ports range, perhaps
* for access to VGA registers.
*/
if (bus_phys == 0 && size >= 0x10000) {
bus_phys += 0x1000;
size -= 0x1000;
}
error = pciconf_resource_add(pcires,
PCICONF_RESOURCE_IO, bus_phys, size);
if (error == 0)
sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY;
break;
case PHYS_HI_SPACE_MEM64:
/* FALLTHROUGH */
@ -324,44 +327,30 @@ pcihost_config(struct pcihost_softc *sc)
++pmbs->nranges;
if ((phys_hi & PHYS_HI_PREFETCH) != 0 ||
__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) {
if (pmemext != NULL) {
aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (prefetchable) range\n");
continue;
}
pmemext = extent_create("pcipmem", bus_phys, bus_phys + size - 1, NULL, 0, EX_WAITOK);
type = PCICONF_RESOURCE_PREFETCHABLE_MEM;
aprint_verbose_dev(sc->sc_dev,
"MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n",
is64 ? 64 : 32, bus_phys, size, cpu_phys);
} else {
if (memext != NULL) {
aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (non-prefetchable) range\n");
continue;
}
memext = extent_create("pcimem", bus_phys, bus_phys + size - 1, NULL, 0, EX_WAITOK);
type = PCICONF_RESOURCE_MEM;
aprint_verbose_dev(sc->sc_dev,
"MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n",
is64 ? 64 : 32, bus_phys, size, cpu_phys);
}
sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY;
error = pciconf_resource_add(pcires, type, bus_phys,
size);
if (error == 0)
sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY;
break;
default:
break;
}
}
if (memext == NULL && pmemext != NULL) {
memext = pmemext;
pmemext = NULL;
}
error = pci_configure_bus(&sc->sc_pc, pcires, sc->sc_bus_min,
PCIHOST_CACHELINE_SIZE);
error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, sc->sc_bus_min, PCIHOST_CACHELINE_SIZE);
if (ioext)
extent_destroy(ioext);
if (memext)
extent_destroy(memext);
if (pmemext)
extent_destroy(pmemext);
pciconf_resource_fini(pcires);
if (error) {
aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error);

27
sys/arch/arm/gemini/gemini_pci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: gemini_pci.c,v 1.21 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: gemini_pci.c,v 1.22 2020/07/07 03:38:45 thorpej Exp $ */
/* adapted from:
* NetBSD: i80312_pci.c,v 1.9 2005/12/11 12:16:51 christos Exp
@ -44,7 +44,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gemini_pci.c,v 1.21 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: gemini_pci.c,v 1.22 2020/07/07 03:38:45 thorpej Exp $");
#include "opt_gemini.h"
#include "opt_pci.h"
@ -53,7 +53,6 @@ __KERNEL_RCSID(0, "$NetBSD: gemini_pci.c,v 1.21 2020/06/14 01:40:03 chs Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <sys/bus.h>
#include <sys/intr.h>
@ -156,10 +155,7 @@ gemini_pci_intrq_dispatch(void)
void
gemini_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct obio_softc *sc = cookie;
struct extent *ioext, *memext;
#endif
pc->pc_conf_v = cookie;
pc->pc_attach_hook = gemini_pci_attach_hook;
@ -199,30 +195,27 @@ gemini_pci_init(pci_chipset_tag_t pc, void *cookie)
aprint_normal("%s: configuring Secondary PCI bus\n",
device_xname(sc->sc_dev));
struct pciconf_resources *pcires = pciconf_resource_init();
/*
* XXX PCI IO addr should be inherited ?
*/
ioext = extent_create("pciio",
GEMINI_PCIIO_BASE,
GEMINI_PCIIO_BASE + GEMINI_PCIIO_SIZE - 1,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
GEMINI_PCIIO_BASE, GEMINI_PCIIO_SIZE);
/*
* XXX PCI mem addr should be inherited ?
*/
memext = extent_create("pcimem",
GEMINI_PCIMEM_BASE,
GEMINI_PCIMEM_BASE + GEMINI_PCIMEM_SIZE - 1,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
GEMINI_PCIMEM_BASE, GEMINI_PCIMEM_SIZE);
pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align);
pci_configure_bus(pc, pcires, 0, arm_dcache_align);
gemini_pci_conf_write(sc, 0, GEMINI_PCI_CFG_REG_MEM1,
PCI_CFG_REG_MEM_BASE((GEMINI_DRAM_BASE + (GEMINI_BUSBASE * 1024 * 1024)))
| gemini_pci_cfg_reg_mem_size(MEMSIZE * 1024 * 1024));
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif
}

24
sys/arch/arm/imx/fdt/imx6_pcie.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_pcie.c,v 1.7 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: imx6_pcie.c,v 1.8 2020/07/07 03:38:45 thorpej Exp $ */
/*-
* Copyright (c) 2019 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@ -25,7 +25,7 @@
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.7 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.8 2020/07/07 03:38:45 thorpej Exp $");
#include "opt_pci.h"
#include "opt_fdt.h"
@ -41,7 +41,6 @@ __KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.7 2020/06/14 01:40:03 chs Exp $");
#include <sys/systm.h>
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/extent.h>
#include <sys/queue.h>
#include <sys/mutex.h>
#include <sys/kmem.h>
@ -228,21 +227,16 @@ imx6_pcie_configure(void *cookie)
struct imxpcie_softc * const sc = &ifsc->sc_imxpcie;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
int error;
struct pciconf_resources *pcires = pciconf_resource_init();
ioext = extent_create("pciio", IMX6_PCIE_IO_BASE,
IMX6_PCIE_IO_BASE + IMX6_PCIE_IO_SIZE - 1,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", IMX6_PCIE_MEM_BASE,
IMX6_PCIE_MEM_BASE + IMX6_PCIE_MEM_SIZE - 1,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
IMX6_PCIE_IO_BASE, IMX6_PCIE_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
IMX6_PCIE_MEM_BASE, IMX6_PCIE_MEM_SIZE);
error = pci_configure_bus(&sc->sc_pc, ioext, memext, NULL, 0,
arm_dcache_align);
int error = pci_configure_bus(&sc->sc_pc, pcires, 0, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
if (error) {
aprint_error_dev(sc->sc_dev, "configuration failed (%d)\n",

24
sys/arch/arm/imx/imx6_pcie.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: imx6_pcie.c,v 1.16 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: imx6_pcie.c,v 1.17 2020/07/07 03:38:45 thorpej Exp $ */
/*
* Copyright (c) 2016 Genetec Corporation. All rights reserved.
@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.16 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.17 2020/07/07 03:38:45 thorpej Exp $");
#include "opt_pci.h"
@ -47,7 +47,6 @@ __KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.16 2020/06/14 01:40:03 chs Exp $");
#include <sys/systm.h>
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/extent.h>
#include <sys/queue.h>
#include <sys/mutex.h>
#include <sys/kmem.h>
@ -189,21 +188,16 @@ imx6_pcie_configure(void *cookie)
struct imxpcie_softc *sc = &ipsc->sc_imxpcie;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
int error;
struct pciconf_resources *pcires = pciconf_resource_init();
ioext = extent_create("pciio", IMX6_PCIE_IO_BASE,
IMX6_PCIE_IO_BASE + IMX6_PCIE_IO_SIZE - 1,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", IMX6_PCIE_MEM_BASE,
IMX6_PCIE_MEM_BASE + IMX6_PCIE_MEM_SIZE - 1,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
IMX6_PCIE_IO_BASE, IMX6_PCIE_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
IMX6_PCIE_MEM_BASE, IMX6_PCIE_MEM_SIZE);
error = pci_configure_bus(&sc->sc_pc, ioext, memext, NULL, 0,
arm_dcache_align);
int error = pci_configure_bus(&sc->sc_pc, pcires, 0, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
if (error) {
aprint_error_dev(sc->sc_dev, "configuration failed (%d)\n",

25
sys/arch/arm/ixp12x0/ixp12x0_pci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ixp12x0_pci.c,v 1.16 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: ixp12x0_pci.c,v 1.17 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright (c) 2002, 2003 The NetBSD Foundation, Inc.
* All rights reserved.
@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixp12x0_pci.c,v 1.16 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: ixp12x0_pci.c,v 1.17 2020/07/07 03:38:46 thorpej Exp $");
/*
* PCI configuration support for IXP12x0 Network Processor chip.
@ -41,7 +41,6 @@ __KERNEL_RCSID(0, "$NetBSD: ixp12x0_pci.c,v 1.16 2020/06/14 01:40:03 chs Exp $")
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <uvm/uvm_extern.h>
@ -86,7 +85,6 @@ ixp12x0_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct ixp12x0_softc *sc = cookie;
struct extent *ioext, *memext;
#endif
pc->pc_conf_v = cookie;
pc->pc_attach_hook = ixp12x0_pci_attach_hook;
@ -98,19 +96,20 @@ ixp12x0_pci_init(pci_chipset_tag_t pc, void *cookie)
pc->pc_conf_interrupt = ixp12x0_pci_conf_interrupt;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
ioext = extent_create("pciio", 0, IXP12X0_PCI_IO_SIZE - 1,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
0, IXP12X0_PCI_IO_SIZE);
/* PCI MEM space is mapped same address as real memory */
memext = extent_create("pcimem", IXP12X0_PCI_MEM_HWBASE,
IXP12X0_PCI_MEM_HWBASE +
IXP12X0_PCI_MEM_SIZE - 1,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
IXP12X0_PCI_MEM_HWBASE, IXP12X0_PCI_MEM_SIZE);
aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n");
pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */,
pci_configure_bus(pc, pcires, 0 /* XXX bus = 0 */,
arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif
}

30
sys/arch/arm/nvidia/tegra_pcie.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tegra_pcie.c,v 1.30 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: tegra_pcie.c,v 1.31 2020/07/07 03:38:46 thorpej Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -27,13 +27,12 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.30 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.31 2020/07/07 03:38:46 thorpej Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/intr.h>
#include <sys/kmem.h>
#include <sys/kernel.h>
@ -149,7 +148,7 @@ tegra_pcie_attach(device_t parent, device_t self, void *aux)
{
struct tegra_pcie_softc * const sc = device_private(self);
struct fdt_attach_args * const faa = aux;
struct extent *ioext, *memext, *pmemext;
struct pciconf_resources *pcires;
struct pcibus_attach_args pba;
bus_addr_t afi_addr, cs_addr, pads_addr;
bus_size_t afi_size, cs_size, pads_size;
@ -228,22 +227,19 @@ tegra_pcie_attach(device_t parent, device_t self, void *aux)
tegra_pcie_init(&sc->sc_pc, sc);
ioext = extent_create("pciio", TEGRA_PCIE_IO_BASE,
TEGRA_PCIE_IO_BASE + TEGRA_PCIE_IO_SIZE - 1,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE,
TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1,
NULL, 0, EX_WAITOK);
pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE,
TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1,
NULL, 0, EX_WAITOK);
pcires = pciconf_resource_init();
error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, 0,
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
TEGRA_PCIE_IO_BASE, TEGRA_PCIE_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
TEGRA_PCIE_MEM_BASE, TEGRA_PCIE_MEM_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_PREFETCHABLE_MEM,
TEGRA_PCIE_PMEM_BASE, TEGRA_PCIE_PMEM_SIZE);
error = pci_configure_bus(&sc->sc_pc, pcires, 0,
arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
extent_destroy(pmemext);
pciconf_resource_fini(pcires);
if (error) {
aprint_error_dev(self, "configuration failed (%d)\n",

22
sys/arch/arm/s3c2xx0/s3c2800_pci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: s3c2800_pci.c,v 1.28 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: s3c2800_pci.c,v 1.29 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright (c) 2002 Fujitsu Component Limited
@ -100,7 +100,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.28 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.29 2020/07/07 03:38:46 thorpej Exp $");
#include "opt_pci.h"
#include "pci.h"
@ -109,7 +109,6 @@ __KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.28 2020/06/14 01:40:03 chs Exp $")
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <uvm/uvm_extern.h>
@ -233,7 +232,7 @@ sspci_attach(device_t parent, device_t self, void *aux)
bus_dma_tag_t pci_dma_tag;
const char *error_on; /* for panic message */
#if defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext, *memext;
struct pciconf_resources *pcires;
struct pcibus_attach_args pci_pba;
#endif
@ -295,20 +294,19 @@ sspci_attach(device_t parent, device_t self, void *aux)
}
#if defined(PCI_NETBSD_CONFIGURE)
ioext = extent_create("pciio", 0x100, S3C2800_PCI_IOSPACE_SIZE - 0x100,
NULL, 0, EX_WAITOK);
pcires = pciconf_resource_init();
memext = extent_create("pcimem", 0, S3C2800_PCI_MEMSPACE_SIZE,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
0x100, S3C2800_PCI_IOSPACE_SIZE - 0x100);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
0, S3C2800_PCI_MEMSPACE_SIZE);
sspci_chipset.pc_conf_v = (void *) sc;
sspci_chipset.pc_intr_v = (void *) sc;
pci_configure_bus(&sspci_chipset, ioext, memext, NULL, 0,
arm_dcache_align);
pci_configure_bus(&sspci_chipset, pcires, 0, arm_dcache_align);
extent_destroy(memext);
extent_destroy(ioext);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */
/* initialize bus space tag */

24
sys/arch/arm/xscale/becc_pci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: becc_pci.c,v 1.20 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: becc_pci.c,v 1.21 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: becc_pci.c,v 1.20 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: becc_pci.c,v 1.21 2020/07/07 03:38:46 thorpej Exp $");
#include "opt_pci.h"
#include "pci.h"
@ -49,7 +49,6 @@ __KERNEL_RCSID(0, "$NetBSD: becc_pci.c,v 1.20 2020/06/14 01:40:03 chs Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <sys/bus.h>
@ -97,7 +96,7 @@ becc_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct becc_softc *sc = cookie;
struct extent *ioext, *memext;
struct pciconf_resources *pcires;
#endif
pc->pc_conf_v = cookie;
@ -127,19 +126,18 @@ becc_pci_init(pci_chipset_tag_t pc, void *cookie)
* the Secondary bus.
*/
pcires = pciconf_resource_init();
/* Reserve the bottom 32K of the PCI address space. */
ioext = extent_create("pciio", sc->sc_ioout_xlate + (32 * 1024),
sc->sc_ioout_xlate + (64 * 1024) - 1,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", sc->sc_owin_xlate[0],
sc->sc_owin_xlate[0] + BECC_PCI_MEM1_SIZE - 1,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
sc->sc_ioout_xlate + (32 * 1024), (32 * 1024));
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
sc->sc_owin_xlate[0], BECC_PCI_MEM1_SIZE);
aprint_normal("%s: configuring PCI bus\n", device_xname(sc->sc_dev));
pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align);
pci_configure_bus(pc, pcires, 0, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif
}

24
sys/arch/arm/xscale/i80312_pci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: i80312_pci.c,v 1.18 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: i80312_pci.c,v 1.19 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: i80312_pci.c,v 1.18 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: i80312_pci.c,v 1.19 2020/07/07 03:38:46 thorpej Exp $");
#include "opt_pci.h"
#include "pci.h"
@ -48,7 +48,6 @@ __KERNEL_RCSID(0, "$NetBSD: i80312_pci.c,v 1.18 2020/06/14 01:40:03 chs Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <sys/bus.h>
@ -81,7 +80,7 @@ i80312_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct i80312_softc *sc = cookie;
struct extent *ioext, *memext;
struct pciconf_resources *pcires;
pcireg_t binfo;
int sbus;
#endif
@ -110,18 +109,17 @@ i80312_pci_init(pci_chipset_tag_t pc, void *cookie)
/* pbus = PCI_BRIDGE_BUS_NUM_PRIMARY(binfo); */
sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(binfo);
ioext = extent_create("pciio", sc->sc_sioout_base,
sc->sc_sioout_base + sc->sc_sioout_size - 1,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", sc->sc_smemout_base,
sc->sc_smemout_base + sc->sc_smemout_size - 1,
NULL, 0, EX_WAITOK);
pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
sc->sc_sioout_base, sc->sc_sioout_size);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
sc->sc_smemout_base, sc->sc_smemout_size);
aprint_normal_dev(sc->sc_dev, "configuring Secondary PCI bus\n");
pci_configure_bus(pc, ioext, memext, NULL, sbus, arm_dcache_align);
pci_configure_bus(pc, pcires, sbus, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif
}

30
sys/arch/arm/xscale/i80321_pci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: i80321_pci.c,v 1.17 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: i80321_pci.c,v 1.18 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: i80321_pci.c,v 1.17 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: i80321_pci.c,v 1.18 2020/07/07 03:38:46 thorpej Exp $");
#include "opt_pci.h"
#include "opt_i80321.h"
@ -49,7 +49,6 @@ __KERNEL_RCSID(0, "$NetBSD: i80321_pci.c,v 1.17 2020/06/14 01:40:03 chs Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <sys/bus.h>
@ -82,7 +81,7 @@ i80321_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct i80321_softc *sc = cookie;
struct extent *ioext, *memext;
struct pciconf_resources *pcires;
uint32_t busno;
#endif
@ -111,26 +110,25 @@ i80321_pci_init(pci_chipset_tag_t pc, void *cookie)
if (busno == 0xff)
busno = 0;
ioext = extent_create("pciio",
pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
sc->sc_ioout_xlate + sc->sc_ioout_xlate_offset,
sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE - 1,
NULL, 0, EX_WAITOK);
VERDE_OUT_XLATE_IO_WIN_SIZE - sc->sc_ioout_xlate_offset);
#ifdef I80321_USE_DIRECT_WIN
memext = extent_create("pcimem", VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SKIP,
VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SIZE- 1,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SKIP,
VERDE_OUT_DIRECT_WIN_SIZE - VERDE_OUT_DIRECT_WIN_SKIP);
#else
memext = extent_create("pcimem", sc->sc_owin[0].owin_xlate_lo,
sc->sc_owin[0].owin_xlate_lo + VERDE_OUT_XLATE_MEM_WIN_SIZE - 1,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
sc->sc_owin[0].owin_xlate_lo, VERDE_OUT_XLATE_MEM_WIN_SIZE);
#endif
aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n");
pci_configure_bus(pc, ioext, memext, NULL, busno, arm_dcache_align);
pci_configure_bus(pc, pcires, busno, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif
}

26
sys/arch/arm/xscale/ixp425_pci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ixp425_pci.c,v 1.13 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: ixp425_pci.c,v 1.14 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright (c) 2003
@ -28,12 +28,11 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixp425_pci.c,v 1.13 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: ixp425_pci.c,v 1.14 2020/07/07 03:38:46 thorpej Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <uvm/uvm_extern.h>
@ -69,7 +68,7 @@ ixp425_pci_init(struct ixp425_softc *sc)
{
pci_chipset_tag_t pc = &sc->ia_pci_chipset;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext, *memext;
struct pciconf_resources *pcires;
#endif
/*
* Initialise the PCI chipset tag
@ -90,19 +89,20 @@ ixp425_pci_init(struct ixp425_softc *sc)
ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
ioext = extent_create("pciio", 0, IXP425_PCI_IO_SIZE - 1,
NULL, 0, EX_WAITOK);
pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
0, IXP425_PCI_IO_SIZE);
/* PCI MEM space is mapped same address as real memory */
memext = extent_create("pcimem", IXP425_PCI_MEM_HWBASE,
IXP425_PCI_MEM_HWBASE +
IXP425_PCI_MEM_SIZE - 1,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE);
aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n");
pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */,
pci_configure_bus(pc, pcires, 0 /* XXX bus = 0 */,
arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif
}

32
sys/arch/bebox/bebox/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.31 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: mainbus.c,v 1.32 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@ -31,10 +31,9 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.31 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.32 2020/07/07 03:38:46 thorpej Exp $");
#include <sys/param.h>
#include <sys/extent.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
@ -68,6 +67,14 @@ int mainbus_found = 0;
struct powerpc_isa_chipset genppc_ict;
struct genppc_pci_chipset *genppc_pct;
#define PCI_IO_START 0x00008000
#define PCI_IO_END 0x0000ffff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START 0x00000000
#define PCI_MEM_END 0x0fffffff
#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
/*
* Probe for the mainbus; always succeeds.
*/
@ -88,16 +95,12 @@ mainbus_attach(device_t parent, device_t self, void *aux)
#if NPCI > 0
struct genppc_pci_chipset_businfo *pbi;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
#endif
mainbus_found = 1;
aprint_normal("\n");
#if defined(RESIDUAL_DATA_DUMP)
print_residual_device_info();
#endif
@ -133,15 +136,16 @@ mainbus_attach(device_t parent, device_t self, void *aux)
SIMPLEQ_INSERT_TAIL(&genppc_pct->pc_pbi, pbi, next);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio", 0x00008000, 0x0000ffff,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", 0x00000000, 0x0fffffff,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pci_configure_bus(genppc_pct, ioext, memext, NULL, 0, CACHELINESIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pci_configure_bus(genppc_pct, pcires, 0, CACHELINESIZE);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */
#endif /* NPCI */

26
sys/arch/cobalt/dev/gt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: gt.c,v 1.31 2020/06/14 01:40:03 chs Exp $ */
/* $NetBSD: gt.c,v 1.32 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.31 2020/06/14 01:40:03 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.32 2020/07/07 03:38:46 thorpej Exp $");
#include "opt_pci.h"
#include "pci.h"
@ -35,7 +35,6 @@ __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.31 2020/06/14 01:40:03 chs Exp $");
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/file.h>
#include <sys/intr.h>
#include <sys/ioctl.h>
@ -84,6 +83,14 @@ struct mips_bus_space gt_memt;
CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc),
gt_match, gt_attach, NULL, NULL);
#define PCI_IO_START 0x00001000
#define PCI_IO_END 0x01ffffff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START 0x12000000
#define PCI_MEM_END 0x13ffffff
#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
static int
gt_match(device_t parent, cfdata_t cf, void *aux)
{
@ -132,12 +139,13 @@ gt_attach(device_t parent, device_t self, void *aux)
pc->pc_bsh = sc->sc_bsh;
#ifdef PCI_NETBSD_CONFIGURE
pc->pc_ioext = extent_create("pciio", 0x00001000, 0x01ffffff,
NULL, 0, EX_WAITOK);
pc->pc_memext = extent_create("pcimem", 0x12000000, 0x13ffffff,
NULL, 0, EX_WAITOK);
pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
mips_cache_info.mci_dcache_align);
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
pci_configure_bus(pc, pcires, 0, mips_cache_info.mci_dcache_align);
pciconf_resource_fini(pcires);
#endif
memset(&pba, 0, sizeof(pba));
pba.pba_memt = &gt_memt;

5
sys/arch/cobalt/include/pci_machdep.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pci_machdep.h,v 1.14 2014/07/29 21:21:44 skrll Exp $ */
/* $NetBSD: pci_machdep.h,v 1.15 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@ -58,9 +58,6 @@ typedef int pci_intr_handle_t;
struct cobalt_pci_chipset {
bus_space_tag_t pc_bst; /* bus space tag for PCICFG regs */
bus_space_handle_t pc_bsh; /* bus space handle for PCICFG regs */
struct extent *pc_memext; /* PCI memory extent */
struct extent *pc_ioext; /* PCI I/O extent */
};
/*

30
sys/arch/evbarm/ifpga/ifpga.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ifpga.c,v 1.27 2020/06/14 01:40:04 chs Exp $ */
/* $NetBSD: ifpga.c,v 1.28 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright (c) 2001 ARM Ltd
@ -38,13 +38,12 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ifpga.c,v 1.27 2020/06/14 01:40:04 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: ifpga.c,v 1.28 2020/07/07 03:38:46 thorpej Exp $");
#include <sys/param.h>
#include <sys/types.h>
#include <sys/device.h>
#include <sys/systm.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <sys/null.h>
@ -158,7 +157,7 @@ ifpga_attach(device_t parent, device_t self, void *aux)
u_int id, sysclk;
extern struct bus_space ifpga_common_bs_tag;
#if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0
struct extent *ioext, *memext, *pmemext;
struct pciconf_resources *pcires;
struct ifpga_pci_softc *pci_sc;
struct pcibus_attach_args pci_pba;
#endif
@ -295,20 +294,19 @@ ifpga_attach(device_t parent, device_t self, void *aux)
}
#if defined(PCI_NETBSD_CONFIGURE)
ioext = extent_create("pciio", 0x00000000,
0x00000000 + IFPGA_PCI_IO_VSIZE, NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", IFPGA_PCI_APP0_BASE,
IFPGA_PCI_APP0_BASE + IFPGA_PCI_APP0_SIZE,
NULL, 0, EX_WAITOK);
pmemext = extent_create("pcipmem", IFPGA_PCI_APP1_BASE,
IFPGA_PCI_APP1_BASE + IFPGA_PCI_APP1_SIZE,
NULL, 0, EX_WAITOK);
pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
0x00000000, IFPGA_PCI_IO_VSIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
IFPGA_PCI_APP0_BASE, IFPGA_PCI_APP0_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_PREFETCHABLE_MEM,
IFPGA_PCI_APP1_BASE, IFPGA_PCI_APP1_SIZE);
ifpga_pci_chipset.pc_conf_v = (void *)pci_sc;
pci_configure_bus(&ifpga_pci_chipset, ioext, memext, pmemext, 0,
pci_configure_bus(&ifpga_pci_chipset, pcires, 0,
arm_dcache_align);
extent_destroy(pmemext);
extent_destroy(memext);
extent_destroy(ioext);
pciconf_resource_fini(pcires);
printf("pci_configure_bus done\n");
#endif /* PCI_NETBSD_CONFIGURE */

28
sys/arch/evbmips/gdium/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.6 2020/06/14 01:40:04 chs Exp $ */
/* $NetBSD: mainbus.c,v 1.7 2020/07/07 03:38:46 thorpej Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.6 2020/06/14 01:40:04 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.7 2020/07/07 03:38:46 thorpej Exp $");
#include "opt_pci.h"
@ -44,7 +44,6 @@ __KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.6 2020/06/14 01:40:04 chs Exp $");
#include <sys/systm.h>
#include <sys/device.h>
#if defined(PCI_NETBSD_CONFIGURE)
#include <sys/extent.h>
#include <sys/malloc.h>
#endif
@ -81,6 +80,13 @@ const char * const mainbusdevs[] = {
#endif
};
#define PCI_IO_START 0x00001000
#define PCI_IO_END 0x00003fff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START 0
#define PCI_MEM_SIZE BONITO_PCILO_SIZE
static int
mainbus_match(device_t parent, cfdata_t match, void *aux)
{
@ -101,14 +107,14 @@ mainbus_attach(device_t parent, device_t self, void *aux)
#if defined(PCI_NETBSD_CONFIGURE)
struct mips_cache_info * const mci = &mips_cache_info;
struct extent *ioext = extent_create("pciio", 0x00001000, 0x00003fff,
NULL, 0, EX_WAITOK);
struct extent *memext = extent_create("pcimem", 0, BONITO_PCILO_SIZE,
NULL, 0, EX_WAITOK);
pci_configure_bus(&gdium_configuration.gc_pc, ioext, memext,
NULL, 0, mci->mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
pci_configure_bus(&gdium_configuration.gc_pc, pcires,
0, mci->mci_dcache_align);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */
for (i = 0; i < __arraycount(mainbusdevs); i++) {

28
sys/arch/evbmips/loongson/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.3 2020/06/14 01:40:04 chs Exp $ */
/* $NetBSD: mainbus.c,v 1.4 2020/07/07 03:38:47 thorpej Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.3 2020/06/14 01:40:04 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.4 2020/07/07 03:38:47 thorpej Exp $");
#include "opt_pci.h"
@ -44,7 +44,6 @@ __KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.3 2020/06/14 01:40:04 chs Exp $");
#include <sys/systm.h>
#include <sys/device.h>
#if defined(PCI_NETBSD_CONFIGURE)
#include <sys/extent.h>
#include <sys/malloc.h>
#endif
@ -85,6 +84,13 @@ const char * const mainbusdevs[] = {
#endif
};
#define PCI_IO_START 0x00001000
#define PCI_IO_END 0x00003fff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START 0
#define PCI_MEM_SIZE BONITO_PCILO_SIZE
static int
mainbus_match(device_t parent, cfdata_t match, void *aux)
{
@ -103,16 +109,16 @@ mainbus_attach(device_t parent, device_t self, void *aux)
aprint_normal("\n");
#if defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext = extent_create("pciio", 0x00001000, 0x00003fff,
NULL, 0, EX_WAITOK);
struct extent *memext = extent_create("pcimem", 0, BONITO_PCILO_SIZE,
NULL, 0, EX_WAITOK);
struct mips_cache_info * const mci = &mips_cache_info;
struct pciconf_resources *pcires = pciconf_resource_init();
pci_configure_bus(&bonito_pc, ioext, memext,
NULL, 0, mci->mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
pci_configure_bus(&bonito_pc, pcires, 0, mci->mci_dcache_align);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */
for (i = 0; i < __arraycount(mainbusdevs); i++) {

35
sys/arch/evbmips/malta/dev/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.14 2020/06/14 01:40:04 chs Exp $ */
/* $NetBSD: mainbus.c,v 1.15 2020/07/07 03:38:47 thorpej Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.14 2020/06/14 01:40:04 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.15 2020/07/07 03:38:47 thorpej Exp $");
#include "opt_pci.h"
@ -44,7 +44,6 @@ __KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.14 2020/06/14 01:40:04 chs Exp $");
#include <sys/systm.h>
#include <sys/device.h>
#if defined(PCI_NETBSD_CONFIGURE)
#include <sys/extent.h>
#include <sys/malloc.h>
#endif
@ -93,6 +92,13 @@ const struct mainbusdev mainbusdevs[] = {
{ NULL, 0, 0 },
};
#define PCI_IO_START 0x00001000
#define PCI_IO_END 0x0000efff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START MALTA_PCIMEM1_BASE
#define PCI_MEM_SIZE MALTA_PCIMEM1_SIZE
static int
mainbus_match(device_t parent, cfdata_t match, void *aux)
{
@ -112,26 +118,21 @@ mainbus_attach(device_t parent, device_t self, void *aux)
struct malta_config *mcp = &malta_configuration;
pci_chipset_tag_t pc = &mcp->mc_pc;
#endif
#if defined(PCI_NETBSD_ENABLE_IDE)
pcitag_t idetag;
pcireg_t idetim;
#endif
mainbus_found = true;
printf("\n");
#if defined(PCI_NETBSD_CONFIGURE)
struct mips_cache_info * const mci = &mips_cache_info;
struct pciconf_resources *pcires = pciconf_resource_init();
struct extent *ioext = extent_create("pciio", 0x00001000, 0x0000efff,
NULL, 0, EX_WAITOK);
struct extent *memext = extent_create("pcimem", MALTA_PCIMEM1_BASE,
MALTA_PCIMEM1_BASE + MALTA_PCIMEM1_SIZE,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
pci_configure_bus(pc, ioext, memext, NULL, 0, mci->mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pci_configure_bus(pc, pcires, 0, mci->mci_dcache_align);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */
#if defined(PCI_NETBSD_ENABLE_IDE)
@ -142,14 +143,14 @@ mainbus_attach(device_t parent, device_t self, void *aux)
* except for the ENABLE bits -- the `pciide' driver will
* properly configure it later.
*/
idetim = 0;
pcireg_t idetim = 0;
if (PCI_NETBSD_ENABLE_IDE & 0x01)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 0);
if (PCI_NETBSD_ENABLE_IDE & 0x02)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1);
/* pciide0 is pci device 10, function 1 */
idetag = pci_make_tag(pc, 0, 10, 1);
pcitag_t idetag = pci_make_tag(pc, 0, 10, 1);
pci_conf_write(pc, idetag, PIIX_IDETIM, idetim);
#endif
for (md = mainbusdevs; md->md_name != NULL; md++) {

28
sys/arch/evbppc/walnut/pci/pchb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pchb.c,v 1.14 2020/06/14 01:40:04 chs Exp $ */
/* $NetBSD: pchb.c,v 1.15 2020/07/07 03:38:47 thorpej Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.14 2020/06/14 01:40:04 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.15 2020/07/07 03:38:47 thorpej Exp $");
#include "pci.h"
#include "opt_pci.h"
@ -38,7 +38,6 @@ __KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.14 2020/06/14 01:40:04 chs Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#define _IBM4XX_BUS_DMA_PRIVATE
@ -78,6 +77,11 @@ static struct powerpc_bus_space pchb_mem_tag = {
MIN_PCI_MEMADDR_NOPREFETCH + 0x1fffffff, /* extent limit */
};
#define PCI_IO_START MIN_PCI_PCI_IOADDR
#define PCI_IO_SIZE 0x10000
#define PCI_MEM_START MIN_PCI_MEMADDR_NOPREFETCH
#define PCI_MEM_SIZE 0x20000000
static int
pchbmatch(device_t parent, cfdata_t cf, void *aux)
@ -122,7 +126,6 @@ pchbattach(device_t parent, device_t self, void *aux)
struct pcibus_attach_args pba;
char devinfo[256];
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#ifdef PCI_CONFIGURE_VERBOSE
extern int pci_conf_debug;
@ -163,14 +166,15 @@ pchbattach(device_t parent, device_t self, void *aux)
panic("pchbattach: can't init MEM tag");
#ifdef PCI_NETBSD_CONFIGURE
memext = extent_create("pcimem", MIN_PCI_MEMADDR_NOPREFETCH,
MIN_PCI_MEMADDR_NOPREFETCH + 0x1fffffff, M_DEVBUF, NULL, 0,
EX_WAITOK);
ioext = extent_create("pciio", MIN_PCI_PCI_IOADDR,
MIN_PCI_PCI_IOADDR + 0xffff, M_DEVBUF, NULL, 0, EX_WAITOK);
pci_configure_bus(0, ioext, memext, NULL, 0, 32);
extent_destroy(memext);
extent_destroy(ioext);
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
pci_configure_bus(0, pcires, 0, 32);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */
#ifdef PCI_CONFIGURE_VERBOSE

31
sys/arch/ibmnws/ibmnws/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.13 2020/06/14 01:40:04 chs Exp $ */
/* $NetBSD: mainbus.c,v 1.14 2020/07/07 03:38:47 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@ -37,7 +37,6 @@
#include "isa.h"
#include <sys/param.h>
#include <sys/extent.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
@ -71,6 +70,14 @@ int mainbus_found = 0;
struct powerpc_isa_chipset genppc_ict;
struct genppc_pci_chipset *genppc_pct;
#define PCI_IO_START 0x00008000
#define PCI_IO_END 0x0000ffff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START 0x00000000
#define PCI_MEM_END 0x0fffffff
#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
/*
* Probe for the mainbus; always succeeds.
*/
@ -92,11 +99,6 @@ mainbus_attach(device_t parent, device_t self, void *aux)
struct mainbus_softc *sc = device_private(self);
union mainbus_attach_args mba;
struct confargs ca;
#if NPCI > 0
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
#endif
mainbus_found = 1;
@ -123,15 +125,16 @@ mainbus_attach(device_t parent, device_t self, void *aux)
ibmnws_pci_get_chipset_tag_indirect (genppc_pct);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio", 0x00008000, 0x0000ffff,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", 0x00000000, 0x0fffffff,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pci_configure_bus(genppc_pct, ioext, memext, NULL, 0, CACHELINESIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pci_configure_bus(genppc_pct, pcires, 0, CACHELINESIZE);
pciconf_resource_fini(pcires);
#endif
memset(&mba, 0, sizeof(mba));

53
sys/arch/mips/adm5120/dev/admpci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: admpci.c,v 1.13 2015/10/02 05:22:51 msaitoh Exp $ */
/* $NetBSD: admpci.c,v 1.14 2020/07/07 03:38:47 thorpej Exp $ */
/*-
* Copyright (c) 2007 David Young. All rights reserved.
@ -61,7 +61,7 @@
#include "pci.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: admpci.c,v 1.13 2015/10/02 05:22:51 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: admpci.c,v 1.14 2020/07/07 03:38:47 thorpej Exp $");
#include <sys/param.h>
#include <sys/types.h>
@ -140,12 +140,6 @@ static void *admpci_intr_establish(void *, pci_intr_handle_t, int,
int (*)(void *), void *);
static void admpci_intr_disestablish(void *, void *);
static int admpci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
#ifdef PCI_NETBSD_CONFIGURE
static struct extent *io_ex = NULL;
static struct extent *mem_ex = NULL;
#endif /* PCI_NETBSD_CONFIGURE */
#endif /* NPCI > 0 */
CFATTACH_DECL_NEW(admpci, sizeof(struct admpci_softc),
@ -163,6 +157,15 @@ int admpci_found = 0;
#endif
#endif
#define PCI_IO_START ADM5120_BASE_PCI_IO
#define PCI_IO_SIZE (ADM5120_BASE_PCI_CONFADDR - ADM5120_BASE_PCI_IO)
#define PCI_MEM_START1 ADM5120_BASE_PCI_MEM
#define PCI_MEM_SIZE1 (ADM5120_BASE_PCI_IO - ADM5120_BASE_PCI_MEM)
#define PCI_MEM_START2 ADM5120_BOTTOM
#define PCI_MEM_SIZE2 (ADM5120_BASE_SRAM1 - ADM5120_BOTTOM)
int
admpcimatch(device_t parent, cfdata_t match, void *aux)
{
@ -178,7 +181,6 @@ admpciattach(device_t parent, device_t self, void *aux)
struct admpci_softc *sc = device_private(self);
struct mainbus_attach_args *ma = (struct mainbus_attach_args *)aux;
#if NPCI > 0
u_long result;
struct pcibus_attach_args pba;
#endif
@ -229,28 +231,21 @@ admpciattach(device_t parent, device_t self, void *aux)
#endif
#ifdef PCI_NETBSD_CONFIGURE
mem_ex = extent_create("pcimem",
ADM5120_BOTTOM, ADM5120_TOP,
NULL, 0, EX_WAITOK);
(void)extent_alloc_subregion(mem_ex,
ADM5120_BASE_SRAM1, ADM5120_BASE_PCI_MEM - 1,
ADM5120_BASE_PCI_MEM - ADM5120_BASE_SRAM1,
ADM5120_BASE_PCI_MEM - ADM5120_BASE_SRAM1,
0, EX_WAITOK, &result);
(void)extent_alloc_subregion(mem_ex,
ADM5120_BASE_PCI_IO, ADM5120_TOP,
ADM5120_TOP - ADM5120_BASE_PCI_IO + 1,
ADM5120_TOP - ADM5120_BASE_PCI_IO + 1,
0, EX_WAITOK, &result);
struct pciconf_resources *pcires = pciconf_resource_init();
io_ex = extent_create("pciio",
ADM5120_BASE_PCI_IO, ADM5120_BASE_PCI_CONFADDR - 1,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START1, PCI_MEM_SIZE1);
pci_configure_bus(&sc->sc_pc,
io_ex, mem_ex, NULL, 0, mips_cache_info.mci_dcache_align);
extent_destroy(mem_ex);
extent_destroy(io_ex);
/* XXX Is this one really needed? */
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START2, PCI_MEM_SIZE2);
pci_configure_bus(&sc->sc_pc, pcires,
0, mips_cache_info.mci_dcache_align);
pciconf_resource_fini(pcires);
#endif
pba.pba_iot = sc->sc_iot;

33
sys/arch/mips/alchemy/dev/aupci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: aupci.c,v 1.17 2015/10/02 05:22:51 msaitoh Exp $ */
/* $NetBSD: aupci.c,v 1.18 2020/07/07 03:38:47 thorpej Exp $ */
/*-
* Copyright (c) 2006 Itronix Inc.
@ -35,7 +35,7 @@
#include "pci.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: aupci.c,v 1.17 2015/10/02 05:22:51 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: aupci.c,v 1.18 2020/07/07 03:38:47 thorpej Exp $");
#include <sys/types.h>
#include <sys/param.h>
@ -44,7 +44,6 @@ __KERNEL_RCSID(0, "$NetBSD: aupci.c,v 1.17 2015/10/02 05:22:51 msaitoh Exp $");
#include <sys/errno.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/extent.h>
#include <sys/bus.h>
#include <uvm/uvm_extern.h>
@ -105,14 +104,16 @@ static void *aupci_intr_establish(void *, pci_intr_handle_t, int,
int (*)(void *), void *);
static void aupci_intr_disestablish(void *, void *);
#ifdef PCI_NETBSD_CONFIGURE
static struct extent *io_ex = NULL;
static struct extent *mem_ex = NULL;
#endif /* PCI_NETBSD_CONFIGURE */
#define PCI_CFG_READ 0
#define PCI_CFG_WRITE 1
#define PCI_IO_START AUPCI_IO_START
#define PCI_IO_END AUPCI_IO_END
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_END 0xffffffff
#define PCI_MEM_SIZE(m) ((PCI_MEM_END - (m)) + 1)
#endif /* NPCI > 0 */
CFATTACH_DECL_NEW(aupci, sizeof(struct aupci_softc),
@ -258,16 +259,16 @@ aupciattach(device_t parent, device_t self, void *aux)
sc->sc_pc.pc_conf_interrupt = aupci_conf_interrupt;
#ifdef PCI_NETBSD_CONFIGURE
mem_ex = extent_create("pcimem", mstart, 0xffffffff,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
io_ex = extent_create("pciio", AUPCI_IO_START, AUPCI_IO_END,
NULL, 0, EX_WAITOK);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
mstart, PCI_MEM_SIZE(mstart));
pci_configure_bus(&sc->sc_pc,
io_ex, mem_ex, NULL, 0, mips_cache_info.mci_dcache_align);
extent_destroy(mem_ex);
extent_destroy(io_ex);
pci_configure_bus(&sc->sc_pc, pcires, 0,
mips_cache_info.mci_dcache_align);
pciconf_resource_fini(pcires);
#endif
pba.pba_iot = sc->sc_iot;

27
sys/arch/mips/rmi/rmixl_pcie.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: rmixl_pcie.c,v 1.13 2019/11/10 21:16:30 chs Exp $ */
/* $NetBSD: rmixl_pcie.c,v 1.14 2020/07/07 03:38:47 thorpej Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: rmixl_pcie.c,v 1.13 2019/11/10 21:16:30 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: rmixl_pcie.c,v 1.14 2020/07/07 03:38:47 thorpej Exp $");
#include "opt_pci.h"
#include "pci.h"
@ -671,7 +671,7 @@ rmixl_pcie_init(struct rmixl_pcie_softc *sc)
{
pci_chipset_tag_t pc = &sc->sc_pci_chipset;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext, *memext;
struct pciconf_resources *pcires;
#endif
pc->pc_conf_v = (void *)sc;
@ -696,24 +696,19 @@ rmixl_pcie_init(struct rmixl_pcie_softc *sc)
*/
struct rmixl_config *rcp = &rmixl_configuration;
aprint_normal("%s: configuring PCI bus\n",
device_xname(sc->sc_dev));
aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n");
ioext = extent_create("pciio",
rcp->rc_pci_io_pbase,
rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1,
NULL, 0, EX_NOWAIT);
pcires = pciconf_resource_init();
memext = extent_create("pcimem",
rcp->rc_pci_mem_pbase,
rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1,
NULL, 0, EX_NOWAIT);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
rcp->rc_pci_io_pbase, rcp->rc_pci_io_size);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
rcp->rc_pci_mem_pbase, rcp->rc_pci_mem_size);
pci_configure_bus(pc, ioext, memext, NULL, 0,
pci_configure_bus(pc, pcires, 0,
mips_cache_info.mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif
}

26
sys/arch/mips/rmi/rmixl_pcix.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: rmixl_pcix.c,v 1.14 2019/11/10 21:16:30 chs Exp $ */
/* $NetBSD: rmixl_pcix.c,v 1.15 2020/07/07 03:38:47 thorpej Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: rmixl_pcix.c,v 1.14 2019/11/10 21:16:30 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: rmixl_pcix.c,v 1.15 2020/07/07 03:38:47 thorpej Exp $");
#include "opt_pci.h"
#include "pci.h"
@ -539,7 +539,7 @@ rmixl_pcix_init(rmixl_pcix_softc_t *sc)
{
pci_chipset_tag_t pc = &sc->sc_pci_chipset;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext, *memext;
struct pciconf_resources *pcires;
#endif
pc->pc_conf_v = (void *)sc;
@ -564,23 +564,19 @@ rmixl_pcix_init(rmixl_pcix_softc_t *sc)
*/
struct rmixl_config *rcp = &rmixl_configuration;
aprint_normal_dev(sc->sc_dev, "%s: configuring PCI bus\n");
aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n");
ioext = extent_create("pciio",
rcp->rc_pci_io_pbase,
rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
pcires = pciconf_resource_init();
memext = extent_create("pcimem",
rcp->rc_pci_mem_pbase,
rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
rcp->rc_pci_io_pbase, rcp->rc_pci_io_size);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
rcp->rc_pci_mem_pbase, rcp->rc_pci_mem_size);
pci_configure_bus(pc, ioext, memext, NULL, 0,
pci_configure_bus(pc, pcires, 0,
mips_cache_info.mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif
}

31
sys/arch/mvmeppc/mvmeppc/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.18 2020/06/14 01:40:04 chs Exp $ */
/* $NetBSD: mainbus.c,v 1.19 2020/07/07 03:38:47 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@ -31,10 +31,9 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.18 2020/06/14 01:40:04 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.19 2020/07/07 03:38:47 thorpej Exp $");
#include <sys/param.h>
#include <sys/extent.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
@ -63,6 +62,14 @@ static int mainbus_found;
struct powerpc_isa_chipset genppc_ict;
struct genppc_pci_chipset *genppc_pct;
#define PCI_IO_START 0x00008000
#define PCI_IO_END 0x0000ffff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START 0x00000000
#define PCI_MEM_END 0x0fffffff
#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
/*
* Probe for the mainbus; always succeeds.
*/
@ -85,9 +92,6 @@ mainbus_attach(device_t parent, device_t self, void *aux)
#if NPCI > 0
struct genppc_pci_chipset_businfo *pbi;
#endif
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
mainbus_found = 1;
@ -116,15 +120,16 @@ mainbus_attach(device_t parent, device_t self, void *aux)
SIMPLEQ_INSERT_TAIL(&genppc_pct->pc_pbi, pbi, next);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio", 0x00008000, 0x0000ffff,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", 0x00000000, 0x0fffffff,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pci_configure_bus(genppc_pct, ioext, memext, NULL, 0, CACHELINESIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pci_configure_bus(genppc_pct, pcires, 0, CACHELINESIZE);
pciconf_resource_fini(pcires);
#endif
pba.pba_iot = &prep_io_space_tag;

29
sys/arch/ofppc/pci/ofwpci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ofwpci.c,v 1.16 2020/06/14 01:40:04 chs Exp $ */
/* $NetBSD: ofwpci.c,v 1.17 2020/07/07 03:38:47 thorpej Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
@ -30,14 +30,13 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ofwpci.c,v 1.16 2020/06/14 01:40:04 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: ofwpci.c,v 1.17 2020/07/07 03:38:47 thorpej Exp $");
#include "opt_pci.h"
#include <sys/param.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/extent.h>
#include <sys/systm.h>
#include <dev/pci/pcivar.h>
@ -137,9 +136,6 @@ ofwpci_attach(device_t parent, device_t self, void *aux)
int i;
uint32_t busrange[2];
char buf[64];
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
aprint_normal("\n");
@ -208,18 +204,21 @@ ofwpci_attach(device_t parent, device_t self, void *aux)
genofw_setup_pciintr_map((void *)pc, pbi, pc->pc_node);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio",
modeldata.pciiodata[device_unit(self)].start,
modeldata.pciiodata[device_unit(self)].limit,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", sc->sc_memt.pbs_base,
sc->sc_memt.pbs_limit-1, NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
if (pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINESIZE))
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
modeldata.pciiodata[device_unit(self)].start,
(modeldata.pciiodata[device_unit(self)].limit -
modeldata.pciiodata[device_unit(self)].start) + 1);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
sc->sc_memt.pbs_base,
(sc->sc_memt.pbs_limit - sc->sc_memt.pbs_base) + 1);
if (pci_configure_bus(pc, pcires, 0, CACHELINESIZE))
aprint_error("pci_configure_bus() failed\n");
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */
memset(&pba, 0, sizeof(pba));
pba.pba_memt = pc->pc_memt;

19
sys/arch/powerpc/booke/pci/pq3pci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pq3pci.c,v 1.24 2020/07/06 09:34:16 rin Exp $ */
/* $NetBSD: pq3pci.c,v 1.25 2020/07/07 03:38:48 thorpej Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@ -39,7 +39,7 @@
#define __INTR_PRIVATE
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pq3pci.c,v 1.24 2020/07/06 09:34:16 rin Exp $");
__KERNEL_RCSID(0, "$NetBSD: pq3pci.c,v 1.25 2020/07/07 03:38:48 thorpej Exp $");
#include "locators.h"
@ -941,16 +941,17 @@ pq3pci_cpunode_attach(device_t parent, device_t self, void *aux)
return;
}
struct extent *ioext = extent_create("pciio", 0, PCI_IOSIZE,
NULL, 0, EX_NOWAIT);
struct extent *memext = extent_create("pcimem", membase,
membase + PCI_MEMSIZE, NULL, 0, EX_NOWAIT);
struct pciconf_resources *pcires = pciconf_resource_init();
error = pci_configure_bus(pc, ioext, memext, NULL, 0,
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
0, PCI_IOSIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
membase, PCI_MEMSIZE);
error = pci_configure_bus(pc, pcires, 0,
curcpu()->ci_ci.dcache_line_size);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
if (error) {
aprint_normal(": configuration failed\n");

24
sys/arch/powerpc/ibm4xx/pci/pchb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pchb.c,v 1.13 2020/07/06 09:34:17 rin Exp $ */
/* $NetBSD: pchb.c,v 1.14 2020/07/07 03:38:48 thorpej Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.13 2020/07/06 09:34:17 rin Exp $");
__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.14 2020/07/07 03:38:48 thorpej Exp $");
#include "pci.h"
@ -42,7 +42,6 @@ __KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.13 2020/07/06 09:34:17 rin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#define _IBM4XX_BUS_DMA_PRIVATE
@ -163,16 +162,15 @@ pchbattach(device_t parent, device_t self, void *aux)
panic("pchbattach: can't init MEM tag");
#ifdef PCI_NETBSD_CONFIGURE
struct extent *memext = extent_create("pcimem",
IBM405GP_PCI_MEM_START,
IBM405GP_PCI_MEM_START + 0x1fffffff, NULL, 0,
EX_WAITOK);
struct extent *ioext = extent_create("pciio",
IBM405GP_PCI_PCI_IO_START,
IBM405GP_PCI_PCI_IO_START + 0xffff, NULL, 0, EX_WAITOK);
pci_configure_bus(pc, ioext, memext, NULL, 0, 32);
extent_destroy(ioext);
extent_destroy(memext);
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
IBM405GP_PCI_PCI_IO_START, 0x10000);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
IBM405GP_PCI_MEM_START, 0x20000000);
pci_configure_bus(pc, pcires, 0, 32);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */
#ifdef PCI_CONFIGURE_VERBOSE

31
sys/arch/prep/prep/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.36 2020/06/14 01:40:05 chs Exp $ */
/* $NetBSD: mainbus.c,v 1.37 2020/07/07 03:38:48 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.36 2020/06/14 01:40:05 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.37 2020/07/07 03:38:48 thorpej Exp $");
#include "opt_pci.h"
#include "opt_residual.h"
@ -41,7 +41,6 @@ __KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.36 2020/06/14 01:40:05 chs Exp $");
#include "isa.h"
#include <sys/param.h>
#include <sys/extent.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
@ -77,6 +76,14 @@ int mainbus_found = 0;
struct powerpc_isa_chipset genppc_ict;
struct genppc_pci_chipset *genppc_pct;
#define PCI_IO_START 0x00008000
#define PCI_IO_END 0x0000ffff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START 0x00000000
#define PCI_MEM_END 0x0fffffff
#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
/*
* Probe for the mainbus; always succeeds.
*/
@ -100,9 +107,6 @@ mainbus_attach(device_t parent, device_t self, void *aux)
int i;
#if NPCI > 0
struct genppc_pci_chipset_businfo *pbi;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
#endif
mainbus_found = 1;
@ -145,15 +149,16 @@ mainbus_attach(device_t parent, device_t self, void *aux)
setup_pciintr_map(pbi, 0, 0, 0);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio", 0x00008000, 0x0000ffff,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", 0x00000000, 0x0fffffff,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pci_configure_bus(genppc_pct, ioext, memext, NULL, 0, CACHELINESIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pci_configure_bus(genppc_pct, pcires, 0, CACHELINESIZE);
pciconf_resource_fini(pcires);
#endif /* PCI_NETBSD_CONFIGURE */
#endif /* NPCI */

31
sys/arch/sandpoint/sandpoint/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.31 2020/06/14 01:40:05 chs Exp $ */
/* $NetBSD: mainbus.c,v 1.32 2020/07/07 03:38:48 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@ -31,13 +31,12 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.31 2020/06/14 01:40:05 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.32 2020/07/07 03:38:48 thorpej Exp $");
#include "opt_pci.h"
#include "pci.h"
#include <sys/param.h>
#include <sys/extent.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/systm.h>
@ -60,6 +59,14 @@ CFATTACH_DECL_NEW(mainbus, 0,
struct powerpc_isa_chipset genppc_ict;
#define PCI_IO_START 0x00001000
#define PCI_IO_END 0x0000ffff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START 0x80000000U
#define PCI_MEM_END 0x8fffffffU
#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
/*
* Probe for the mainbus; always succeeds.
*/
@ -79,9 +86,6 @@ mainbus_attach(device_t parent, device_t self, void *aux)
struct mainbus_attach_args mba;
struct pcibus_attach_args pba;
struct btinfo_prodfamily *pfam;
#if defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext, *memext;
#endif
aprint_naive("\n");
aprint_normal("\n");
@ -113,15 +117,16 @@ mainbus_attach(device_t parent, device_t self, void *aux)
*/
#if NPCI > 0
#if defined(PCI_NETBSD_CONFIGURE)
ioext = extent_create("pciio", 0x00001000, 0x0000ffff,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", 0x80000000, 0x8fffffff,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pci_configure_bus(0, ioext, memext, NULL, 0, 32);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pci_configure_bus(0, pcires, 0, 32);
pciconf_resource_fini(pcires);
#endif
pba.pba_iot = &sandpoint_io_space_tag;

16
sys/arch/sgimips/gio/pci_gio.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pci_gio.c,v 1.16 2020/06/14 01:40:05 chs Exp $ */
/* $NetBSD: pci_gio.c,v 1.17 2020/07/07 03:38:48 thorpej Exp $ */
/*
* Copyright (c) 2006 Stephen M. Rumble
@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.16 2020/06/14 01:40:05 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.17 2020/07/07 03:38:48 thorpej Exp $");
/*
* Glue for PCI devices that are connected to the GIO bus by various little
@ -43,7 +43,6 @@ __KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.16 2020/06/14 01:40:05 chs Exp $");
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/extent.h>
#include <sys/bus.h>
#include <machine/machtype.h>
@ -220,10 +219,15 @@ giopci_attach(device_t parent, device_t self, void *aux)
printf(": %s\n", gio_product_string(sc->sc_gprid));
#ifdef PCI_NETBSD_CONFIGURE
pc->pc_memext = extent_create("giopcimem", m_start, m_end,
NULL, 0, EX_WAITOK);
pci_configure_bus(pc, NULL, pc->pc_memext, NULL, 0,
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
m_start, (m_end - m_start) + 1);
pci_configure_bus(pc, pcires, 0,
mips_cache_info.mci_dcache_align);
pciconf_resource_fini(pcires);
#endif
memset(&pba, 0, sizeof(pba));

5
sys/arch/sgimips/include/pci_machdep.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pci_machdep.h,v 1.14 2015/02/18 16:47:58 macallan Exp $ */
/* $NetBSD: pci_machdep.h,v 1.15 2020/07/07 03:38:48 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@ -71,9 +71,6 @@ struct sgimips_pci_chipset {
bus_space_handle_t ioh;
void *cookie;
struct extent *pc_memext; /* PCI memory space extent */
struct extent *pc_ioext; /* PCI I/O space extent */
};
extern struct mips_bus_dma_tag pci_bus_dma_tag;

44
sys/arch/sgimips/mace/pci_mace.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pci_mace.c,v 1.22 2020/06/14 01:40:05 chs Exp $ */
/* $NetBSD: pci_mace.c,v 1.23 2020/07/07 03:38:48 thorpej Exp $ */
/*
* Copyright (c) 2001,2003 Christopher Sekiya
@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.22 2020/06/14 01:40:05 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.23 2020/07/07 03:38:48 thorpej Exp $");
#include "opt_pci.h"
#include "pci.h"
@ -56,7 +56,6 @@ __KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.22 2020/06/14 01:40:05 chs Exp $");
#include <dev/pci/pcireg.h>
#include <dev/pci/pcidevs.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <dev/pci/pciconf.h>
@ -96,6 +95,21 @@ static struct mips_bus_space pciio_mbst;
bus_space_tag_t mace_pci_memt = NULL;
bus_space_tag_t mace_pci_iot = NULL;
#define PCI_IO_START 0x00001000
#define PCI_IO_END 0x01ffffff
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#ifdef USE_HIGH_PCI
#define PCI_MEM_START 0x80000000
#define PCI_MEM_END 0xffffffff
#else /* ! USE_HIGH_PCI */
/* XXX no idea why we limit ourselves to only half of the 32MB window */
#define PCI_MEM_START 0x80100000
#define PCI_MEM_END 0x81ffffff
#endif /* USE_HIGH_PCI */
#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
static int
macepci_match(device_t parent, cfdata_t match, void *aux)
{
@ -161,20 +175,18 @@ macepci_attach(device_t parent, device_t self, void *aux)
bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control);
#if NPCI > 0
#ifdef USE_HIGH_PCI
pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff,
NULL, 0, EX_WAITOK);
pc->pc_memext = extent_create("macepcimem", 0x80000000, 0xffffffff,
NULL, 0, EX_WAITOK);
#else
pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff,
NULL, 0, EX_WAITOK);
/* XXX no idea why we limit ourselves to only half of the 32MB window */
pc->pc_memext = extent_create("macepcimem", 0x80100000, 0x81ffffff,
NULL, 0, EX_WAITOK);
#endif /* USE_HIGH_PCI */
pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
struct pciconf_resources *pcires = pciconf_resource_init();
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
pci_configure_bus(pc, pcires, 0,
mips_cache_info.mci_dcache_align);
pciconf_resource_fini(pcires);
memset(&pba, 0, sizeof pba);
pba.pba_iot = mace_pci_iot;
pba.pba_memt = mace_pci_memt;

25
sys/arch/sh3/dev/shpcic.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: shpcic.c,v 1.19 2020/06/14 01:40:05 chs Exp $ */
/* $NetBSD: shpcic.c,v 1.20 2020/07/07 03:38:48 thorpej Exp $ */
/*-
* Copyright (C) 2005 NONAKA Kimihiro <nonaka@netbsd.org>
@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: shpcic.c,v 1.19 2020/06/14 01:40:05 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: shpcic.c,v 1.20 2020/07/07 03:38:48 thorpej Exp $");
#include "opt_pci.h"
@ -34,7 +34,6 @@ __KERNEL_RCSID(0, "$NetBSD: shpcic.c,v 1.19 2020/06/14 01:40:05 chs Exp $");
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <dev/pci/pcireg.h>
@ -127,9 +126,6 @@ static void
shpcic_attach(device_t parent, device_t self, void *aux)
{
struct pcibus_attach_args pba;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
pcireg_t id, class;
char devinfo[256];
@ -226,17 +222,16 @@ shpcic_attach(device_t parent, device_t self, void *aux)
/* PCI bus */
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio",
SH4_PCIC_IO, SH4_PCIC_IO + SH4_PCIC_IO_SIZE - 1,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem",
SH4_PCIC_MEM, SH4_PCIC_MEM + SH4_PCIC_MEM_SIZE - 1,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pci_configure_bus(NULL, ioext, memext, NULL, 0, sh_cache_line_size);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
SH4_PCIC_IO, SH4_PCIC_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
SH4_PCIC_MEM, SH4_PCIC_MEM_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pci_configure_bus(NULL, pcires, 0, sh_cache_line_size);
pciconf_resource_fini(pcires);
#endif
/* PCI bus */

99
sys/dev/acpi/acpi_mcfg.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: acpi_mcfg.c,v 1.19 2020/04/13 12:08:05 jmcneill Exp $ */
/* $NetBSD: acpi_mcfg.c,v 1.20 2020/07/07 03:38:48 thorpej Exp $ */
/*-
* Copyright (C) 2015 NONAKA Kimihiro <nonaka@NetBSD.org>
@ -28,13 +28,12 @@
#include "opt_pci.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: acpi_mcfg.c,v 1.19 2020/04/13 12:08:05 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: acpi_mcfg.c,v 1.20 2020/07/07 03:38:48 thorpej Exp $");
#include <sys/param.h>
#include <sys/device.h>
#include <sys/kmem.h>
#include <sys/systm.h>
#include <sys/extent.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
@ -694,17 +693,13 @@ out:
}
#ifdef PCI_NETBSD_CONFIGURE
struct acpimcfg_resource {
struct extent *ioext;
struct extent *memext;
struct extent *pmemext;
};
static ACPI_STATUS
acpimcfg_configure_bus_cb(ACPI_RESOURCE *res, void *ctx)
{
struct acpimcfg_resource *pcires = ctx;
struct extent *ex;
struct pciconf_resources *pcires = ctx;
int type;
bus_addr_t addr;
bus_size_t size;
const char *s;
int error;
@ -722,48 +717,15 @@ acpimcfg_configure_bus_cb(ACPI_RESOURCE *res, void *ctx)
if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE &&
res->Data.Address.Info.Mem.Caching == ACPI_PREFETCHABLE_MEMORY) {
if (pcires->pmemext == NULL) {
pcires->pmemext = extent_create("pcipmem", 0, ULONG_MAX,
NULL, 0, EX_WAITOK);
error = extent_alloc_region(pcires->pmemext, 0, ULONG_MAX,
EX_WAITOK);
if (error) {
extent_destroy(pcires->pmemext);
pcires->pmemext = NULL;
return AE_NO_MEMORY;
}
}
ex = pcires->pmemext;
type = PCICONF_RESOURCE_PREFETCHABLE_MEM;
s = "prefetchable";
} else if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE &&
res->Data.Address.Info.Mem.Caching != ACPI_PREFETCHABLE_MEMORY) {
if (pcires->memext == NULL) {
pcires->memext = extent_create("pcimem", 0, ULONG_MAX,
NULL, 0, EX_WAITOK);
error = extent_alloc_region(pcires->memext, 0, ULONG_MAX,
EX_WAITOK);
if (error) {
extent_destroy(pcires->memext);
pcires->memext = NULL;
return AE_NO_MEMORY;
}
}
ex = pcires->memext;
type = PCICONF_RESOURCE_MEM;
s = "non-prefetchable";
} else {
KASSERT(res->Data.Address.ResourceType == ACPI_IO_RANGE);
if (pcires->ioext == NULL) {
pcires->ioext = extent_create("pciio", 0, ULONG_MAX,
NULL, 0, EX_WAITOK);
error = extent_alloc_region(pcires->ioext, 0, ULONG_MAX,
EX_WAITOK);
if (error) {
extent_destroy(pcires->ioext);
pcires->ioext = NULL;
return AE_NO_MEMORY;
}
}
ex = pcires->ioext;
type = PCICONF_RESOURCE_IO;
s = "i/o";
}
@ -774,10 +736,8 @@ acpimcfg_configure_bus_cb(ACPI_RESOURCE *res, void *ctx)
res->Data.Address16.Address.Minimum,
res->Data.Address16.Address.AddressLength,
s);
error = extent_free(ex, res->Data.Address16.Address.Minimum,
res->Data.Address16.Address.AddressLength, EX_WAITOK);
if (error)
return AE_NO_MEMORY;
addr = res->Data.Address16.Address.Minimum;
size = res->Data.Address16.Address.AddressLength;
break;
case ACPI_RESOURCE_TYPE_ADDRESS32:
aprint_debug(
@ -785,10 +745,8 @@ acpimcfg_configure_bus_cb(ACPI_RESOURCE *res, void *ctx)
res->Data.Address32.Address.Minimum,
res->Data.Address32.Address.AddressLength,
s);
error = extent_free(ex, res->Data.Address32.Address.Minimum,
res->Data.Address32.Address.AddressLength, EX_WAITOK);
if (error)
return AE_NO_MEMORY;
addr = res->Data.Address32.Address.Minimum;
size = res->Data.Address32.Address.AddressLength;
break;
case ACPI_RESOURCE_TYPE_ADDRESS64:
aprint_debug(
@ -796,21 +754,24 @@ acpimcfg_configure_bus_cb(ACPI_RESOURCE *res, void *ctx)
res->Data.Address64.Address.Minimum,
res->Data.Address64.Address.AddressLength,
s);
error = extent_free(ex, res->Data.Address64.Address.Minimum,
res->Data.Address64.Address.AddressLength, EX_WAITOK);
if (error)
return AE_NO_MEMORY;
addr = res->Data.Address64.Address.Minimum;
size = res->Data.Address64.Address.AddressLength;
break;
default:
return AE_OK;
}
return AE_OK;
error = pciconf_resource_add(pcires, type, addr, size);
return error == 0 ? AE_OK : AE_NO_MEMORY;
}
int
acpimcfg_configure_bus(device_t self, pci_chipset_tag_t pc, ACPI_HANDLE handle,
int bus, int cacheline_size)
{
struct acpimcfg_resource res;
struct pciconf_resources *pcires;
struct mcfg_segment *seg;
struct mcfg_bus *mb;
bus_space_handle_t bsh[256];
@ -823,6 +784,8 @@ acpimcfg_configure_bus(device_t self, pci_chipset_tag_t pc, ACPI_HANDLE handle,
if (seg == NULL)
return ENOENT;
pcires = pciconf_resource_init();
/*
* Map config space for all possible busses and mark them valid during
* configuration so pci_configure_bus can access them through our chipset
@ -855,15 +818,14 @@ acpimcfg_configure_bus(device_t self, pci_chipset_tag_t pc, ACPI_HANDLE handle,
memset(mb->valid_devs, 0xff, sizeof(mb->valid_devs));
}
memset(&res, 0, sizeof(res));
rv = AcpiWalkResources(handle, "_CRS", acpimcfg_configure_bus_cb, &res);
rv = AcpiWalkResources(handle, "_CRS", acpimcfg_configure_bus_cb,
pcires);
if (ACPI_FAILURE(rv)) {
error = ENXIO;
goto cleanup;
}
error = pci_configure_bus(pc, res.ioext, res.memext, res.pmemext, bus,
cacheline_size);
error = pci_configure_bus(pc, pcires, bus, cacheline_size);
cleanup:
/*
@ -879,12 +841,7 @@ cleanup:
bus_space_unmap(seg->ms_bst, bsh[b], ACPIMCFG_SIZE_PER_BUS);
}
if (res.ioext)
extent_destroy(res.ioext);
if (res.memext)
extent_destroy(res.memext);
if (res.pmemext)
extent_destroy(res.pmemext);
pciconf_resource_fini(pcires);
return error;
}

27
sys/dev/ic/cpc700.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpc700.c,v 1.20 2020/06/14 01:40:06 chs Exp $ */
/* $NetBSD: cpc700.c,v 1.21 2020/07/07 03:38:49 thorpej Exp $ */
/*
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@ -50,13 +50,12 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpc700.c,v 1.20 2020/06/14 01:40:06 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpc700.c,v 1.21 2020/07/07 03:38:49 thorpej Exp $");
#include "pci.h"
#include "opt_pci.h"
#include <sys/param.h>
#include <sys/extent.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/systm.h>
@ -88,6 +87,14 @@ static bus_space_handle_t the_cpc_handle;
#define INL(a) bus_space_read_stream_4(the_cpc_tag, the_cpc_handle, (a))
#define OUTL(a, d) bus_space_write_stream_4(the_cpc_tag, the_cpc_handle, (a), d)
#define PCI_IO_START CPC_PCI_IO_START
#define PCI_IO_END CPC_PCI_IO_END
#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
#define PCI_MEM_START CPC_PCI_MEM_BASE
#define PCI_MEM_END CPC_PCI_MEM_END
#define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
static int
cpc_print(void *aux, const char *pnp)
{
@ -141,7 +148,6 @@ cpc_attach(device_t self, pci_chipset_tag_t pc, bus_space_tag_t mem,
{ NULL, 0 }
};
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext, *memext;
#ifdef PCI_CONFIGURE_VERBOSE
extern int pci_conf_debug;
@ -190,15 +196,14 @@ cpc_attach(device_t self, pci_chipset_tag_t pc, bus_space_tag_t mem,
pci_conf_write(pc, tag, CPC_BRIDGE_OPTIONS2, v);
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
ioext = extent_create("pciio", CPC_PCI_IO_START, CPC_PCI_IO_END,
NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", CPC_PCI_MEM_BASE, CPC_PCI_MEM_END,
NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pci_configure_bus(0, ioext, memext, NULL, 0, 32);
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
PCI_IO_START, PCI_IO_SIZE);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
PCI_MEM_START, PCI_MEM_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
pci_configure_bus(0, pcires, 0, 32);
#endif
config_found_ia(self, "pcibus", &aa.pba, pcibusprint);

21
sys/dev/marvell/gtpci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: gtpci.c,v 1.33 2020/06/14 01:40:06 chs Exp $ */
/* $NetBSD: gtpci.c,v 1.34 2020/07/07 03:38:49 thorpej Exp $ */
/*
* Copyright (c) 2008, 2009 KIYOHARA Takashi
* All rights reserved.
@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.33 2020/06/14 01:40:06 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.34 2020/07/07 03:38:49 thorpej Exp $");
#include "opt_pci.h"
#include "pci.h"
@ -35,7 +35,6 @@ __KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.33 2020/06/14 01:40:06 chs Exp $");
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/errno.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <prop/proplib.h>
@ -446,22 +445,22 @@ gtpci_pci_config(struct gtpci_softc *sc, bus_space_tag_t iot,
int cacheline_size)
{
struct pcibus_attach_args pba;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext = NULL, *memext = NULL;
#endif
uint32_t p2pc, command;
p2pc = GTPCI_READ(sc, GTPCI_P2PC);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio", iostart, ioend, NULL, 0, EX_WAITOK);
memext = extent_create("pcimem", memstart, memend, NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pci_configure_bus(pc, ioext, memext, NULL,
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
iostart, (ioend - iostart) + 1);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
memstart, (memend - memstart) + 1);
pci_configure_bus(pc, pcires,
GTPCI_P2PC_BUSNUMBER(p2pc), cacheline_size);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif
pba.pba_iot = iot;

21
sys/dev/marvell/mvpex.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mvpex.c,v 1.19 2020/06/14 01:40:06 chs Exp $ */
/* $NetBSD: mvpex.c,v 1.20 2020/07/07 03:38:49 thorpej Exp $ */
/*
* Copyright (c) 2008 KIYOHARA Takashi
* All rights reserved.
@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mvpex.c,v 1.19 2020/06/14 01:40:06 chs Exp $");
__KERNEL_RCSID(0, "$NetBSD: mvpex.c,v 1.20 2020/07/07 03:38:49 thorpej Exp $");
#include "opt_pci.h"
#include "pci.h"
@ -35,7 +35,6 @@ __KERNEL_RCSID(0, "$NetBSD: mvpex.c,v 1.19 2020/06/14 01:40:06 chs Exp $");
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/errno.h>
#include <sys/extent.h>
#include <sys/evcnt.h>
#include <sys/malloc.h>
#include <sys/systm.h>
@ -409,22 +408,22 @@ mvpex_pci_config(struct mvpex_softc *sc, bus_space_tag_t iot,
int cacheline_size)
{
struct pcibus_attach_args pba;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext = NULL, *memext = NULL;
#endif
uint32_t stat;
stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pexio", iostart, ioend, NULL, 0, EX_WAITOK);
memext = extent_create("pexmem", memstart, memend, NULL, 0, EX_WAITOK);
struct pciconf_resources *pcires = pciconf_resource_init();
pci_configure_bus(pc, ioext, memext, NULL,
pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
iostart, (ioend - iostart) + 1);
pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
memstart, (memend - memstart) + 1);
pci_configure_bus(pc, pcires,
MVPEX_STAT_PEXBUSNUM(stat), cacheline_size);
extent_destroy(ioext);
extent_destroy(memext);
pciconf_resource_fini(pcires);
#endif
pba.pba_iot = iot;

351
sys/dev/pci/pciconf.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pciconf.c,v 1.46 2020/02/02 14:45:14 jmcneill Exp $ */
/* $NetBSD: pciconf.c,v 1.47 2020/07/07 03:38:49 thorpej Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -65,23 +65,23 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.46 2020/02/02 14:45:14 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.47 2020/07/07 03:38:49 thorpej Exp $");
#include "opt_pci.h"
#include <sys/param.h>
#include <sys/extent.h>
#include <sys/queue.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/kmem.h>
#include <sys/vmem.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pciconf.h>
#include <dev/pci/pcidevs.h>
#include <dev/pci/pccbbreg.h>
int pci_conf_debug = 0;
int pci_conf_debug = 1;
#if !defined(MIN)
#define MIN(a,b) (((a)<(b))?(a):(b))
@ -95,6 +95,28 @@ int pci_conf_debug = 0;
struct _s_pciconf_bus_t; /* Forward declaration */
struct pciconf_resource {
vmem_t *arena;
bus_addr_t min_addr;
bus_addr_t max_addr;
bus_size_t total_size;
};
#define PCICONF_RESOURCE_NTYPES 3
CTASSERT(PCICONF_RESOURCE_IO < PCICONF_RESOURCE_NTYPES);
CTASSERT(PCICONF_RESOURCE_MEM < PCICONF_RESOURCE_NTYPES);
CTASSERT(PCICONF_RESOURCE_PREFETCHABLE_MEM < PCICONF_RESOURCE_NTYPES);
static const char *pciconf_resource_names[] = {
[PCICONF_RESOURCE_IO] = "pci-io",
[PCICONF_RESOURCE_MEM] = "pci-mem",
[PCICONF_RESOURCE_PREFETCHABLE_MEM] = "pci-pmem",
};
struct pciconf_resources {
struct pciconf_resource resources[PCICONF_RESOURCE_NTYPES];
};
typedef struct _s_pciconf_dev_t {
int ipin;
int iline;
@ -149,9 +171,9 @@ typedef struct _s_pciconf_bus_t {
bus_size_t mem_total;
bus_size_t pmem_total;
struct extent *ioext;
struct extent *memext;
struct extent *pmemext;
struct pciconf_resource io_res;
struct pciconf_resource mem_res;
struct pciconf_resource pmem_res;
pci_chipset_tag_t pc;
struct _s_pciconf_bus_t *parent_bus;
@ -165,13 +187,57 @@ static int setup_iowins(pciconf_bus_t *);
static int setup_memwins(pciconf_bus_t *);
static int configure_bridge(pciconf_dev_t *);
static int configure_bus(pciconf_bus_t *);
static uint64_t pci_allocate_range(struct extent *, uint64_t, int, bool);
static uint64_t pci_allocate_range(struct pciconf_resource *, uint64_t, int,
bool);
static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t);
static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t);
static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int);
static void print_tag(pci_chipset_tag_t, pcitag_t);
static vmem_t *
create_vmem_arena(const char *name, bus_addr_t start, bus_size_t size,
int flags)
{
KASSERT(start < VMEM_ADDR_MAX);
KASSERT(size == 0 ||
(VMEM_ADDR_MAX - start) >= (size - 1));
return vmem_create(name, start, size,
1, /*quantum*/
NULL, /*importfn*/
NULL, /*releasefn*/
NULL, /*source*/
0, /*qcache_max*/
flags,
IPL_NONE);
}
static int
init_range_resource(struct pciconf_resource *r, const char *name,
bus_addr_t start, bus_addr_t size)
{
r->arena = create_vmem_arena(name, start, size, VM_NOSLEEP);
if (r->arena == NULL)
return ENOMEM;
r->min_addr = start;
r->max_addr = start + (size - 1);
r->total_size = size;
return 0;
}
static void
fini_range_resource(struct pciconf_resource *r)
{
if (r->arena) {
vmem_xfreeall(r->arena);
vmem_destroy(r->arena);
}
memset(r, 0, sizeof(*r));
}
static void
print_tag(pci_chipset_tag_t pc, pcitag_t tag)
{
@ -339,9 +405,10 @@ query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev)
pb->swiz = parent->swiz + dev;
pb->ioext = NULL;
pb->memext = NULL;
pb->pmemext = NULL;
memset(&pb->io_res, 0, sizeof(pb->io_res));
memset(&pb->mem_res, 0, sizeof(pb->mem_res));
memset(&pb->pmem_res, 0, sizeof(pb->pmem_res));
pb->pc = parent->pc;
pb->io_total = pb->mem_total = pb->pmem_total = 0;
@ -709,56 +776,48 @@ pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func,
/************************************************************************/
/************************************************************************/
static uint64_t
pci_allocate_range(struct extent * const ex, const uint64_t amt,
pci_allocate_range(struct pciconf_resource * const r, const uint64_t amt,
const int align, const bool ok64 __used_only_lp64)
{
int r;
u_long addr;
u_long end = ex->ex_end;
vmem_size_t const size = (vmem_size_t) amt;
vmem_addr_t result;
int error;
#ifdef _LP64
/*
* If a 64-bit range is not OK:
* ==> If the start of the range is > 4GB, allocation not possible.
* ==> If the end of the range is > (4GB-1), constrain the end.
*
* If a 64-bit range IS OK, then we prefer allocating above 4GB.
*
* XXX We guard this with _LP64 because extent maps use u_long
* XXX We guard this with _LP64 because vmem uses uintptr_t
* internally.
*/
if (!ok64) {
if (ex->ex_start >= (1UL << 32)) {
printf("PCI: 32-BIT RESTRICTION, RANGE BEGINS AT %#lx\n",
ex->ex_start);
return ~0ULL;
}
if (end > 0xffffffffUL) {
end = 0xffffffffUL;
}
} else if (end > (1UL << 32)) {
u_long start4g = ex->ex_start;
if (start4g < (1UL << 32)) {
start4g = (1UL << 32);
}
r = extent_alloc_subregion(ex, start4g, end, amt, align, 0,
EX_NOWAIT, &addr);
if (r == 0) {
return addr;
error = vmem_xalloc(r->arena, size, align, 0, 0,
VMEM_ADDR_MIN, 0xffffffffUL,
VM_BESTFIT | VM_NOSLEEP,
&result);
} else {
error = vmem_xalloc(r->arena, size, align, 0, 0,
(1UL << 32), VMEM_ADDR_MAX,
VM_BESTFIT | VM_NOSLEEP,
&result);
if (error) {
error = vmem_xalloc(r->arena, size, align, 0, 0,
VMEM_ADDR_MIN, VMEM_ADDR_MAX,
VM_BESTFIT | VM_NOSLEEP,
&result);
}
}
#else
error = vmem_xalloc(r->arena, size, align, 0, 0,
VMEM_ADDR_MIN, 0xffffffffUL,
VM_BESTFIT | VM_NOSLEEP,
&result);
#endif /* _L64 */
r = extent_alloc_subregion(ex, ex->ex_start, end, amt, align, 0,
EX_NOWAIT, &addr);
if (r) {
printf("extent_alloc_subregion(%p, %#lx, %#lx, %#" PRIx64 ", %#x) returned %d\n",
ex, ex->ex_start, end, amt, align, r);
extent_print(ex);
if (error)
return ~0ULL;
}
return addr;
return result;
}
static int
@ -766,19 +825,20 @@ setup_iowins(pciconf_bus_t *pb)
{
pciconf_win_t *pi;
pciconf_dev_t *pd;
int error;
for (pi = pb->pciiowin; pi < &pb->pciiowin[pb->niowin]; pi++) {
if (pi->size == 0)
continue;
pd = pi->dev;
if (pb->ioext == NULL) {
if (pb->io_res.arena == NULL) {
/* Bus has no IO ranges, disable IO BAR */
pi->address = 0;
pd->enable &= ~PCI_CONF_ENABLE_IO;
goto write_ioaddr;
}
pi->address = pci_allocate_range(pb->ioext, pi->size,
pi->address = pci_allocate_range(&pb->io_res, pi->size,
pi->align, false);
if (~pi->address == 0) {
print_tag(pd->pc, pd->tag);
@ -787,12 +847,11 @@ setup_iowins(pciconf_bus_t *pb)
return -1;
}
if (pd->ppb && pi->reg == 0) {
pd->ppb->ioext = extent_create("pciconf", pi->address,
pi->address + pi->size, NULL, 0,
EX_NOWAIT);
if (pd->ppb->ioext == NULL) {
error = init_range_resource(&pd->ppb->io_res,
"ppb-io", pi->address, pi->size);
if (error) {
print_tag(pd->pc, pd->tag);
printf("Failed to alloc I/O ext. for bus %d\n",
printf("Failed to alloc I/O arena for bus %d\n",
pd->ppb->busno);
return -1;
}
@ -822,8 +881,9 @@ setup_memwins(pciconf_bus_t *pb)
pciconf_win_t *pm;
pciconf_dev_t *pd;
pcireg_t base;
struct extent *ex;
struct pciconf_resource *r;
bool ok64;
int error;
for (pm = pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin]; pm++) {
if (pm->size == 0)
@ -832,10 +892,10 @@ setup_memwins(pciconf_bus_t *pb)
ok64 = false;
pd = pm->dev;
if (pm->prefetch) {
ex = pb->pmemext;
r = &pb->pmem_res;
ok64 = pb->pmem_64bit;
} else {
ex = pb->memext;
r = &pb->mem_res;
ok64 = pb->mem_64bit && pd->ppb == NULL;
}
@ -852,7 +912,7 @@ setup_memwins(pciconf_bus_t *pb)
PCI_MAPREG_MEM_TYPE_64BIT;
}
pm->address = pci_allocate_range(ex, pm->size, pm->align,
pm->address = pci_allocate_range(r, pm->size, pm->align,
ok64);
if (~pm->address == 0) {
print_tag(pd->pc, pd->tag);
@ -863,19 +923,18 @@ setup_memwins(pciconf_bus_t *pb)
return -1;
}
if (pd->ppb && pm->reg == 0) {
ex = extent_create("pciconf", pm->address,
pm->address + pm->size, NULL, 0, EX_NOWAIT);
if (ex == NULL) {
const char *name = pm->prefetch ? "ppb-pmem"
: "ppb-mem";
r = pm->prefetch ? &pd->ppb->pmem_res
: &pd->ppb->mem_res;
error = init_range_resource(r, name,
pm->address, pm->size);
if (error) {
print_tag(pd->pc, pd->tag);
printf("Failed to alloc MEM ext. for bus %d\n",
printf("Failed to alloc MEM arena for bus %d\n",
pd->ppb->busno);
return -1;
}
if (pm->prefetch)
pd->ppb->pmemext = ex;
else
pd->ppb->memext = ex;
continue;
}
if (!ok64 && pm->address > 0xFFFFFFFFULL) {
@ -928,21 +987,21 @@ setup_memwins(pciconf_bus_t *pb)
}
static bool
constrain_bridge_mem_range(struct extent * const ex,
constrain_bridge_mem_range(struct pciconf_resource * const r,
u_long * const base,
u_long * const limit,
const bool ok64 __used_only_lp64)
{
*base = ex->ex_start;
*limit = ex->ex_end;
*base = r->min_addr;
*limit = r->max_addr;
#ifdef _LP64
if (!ok64) {
if (ex->ex_start >= (1UL << 32)) {
if (r->min_addr >= (1UL << 32)) {
return true;
}
if (ex->ex_end > 0xffffffffUL) {
if (r->max_addr > 0xffffffffUL) {
*limit = 0xffffffffUL;
}
}
@ -967,9 +1026,9 @@ configure_bridge(pciconf_dev_t *pd)
pb = pd->ppb;
/* Configure I/O base & limit*/
if (pb->ioext) {
io_base = pb->ioext->ex_start;
io_limit = pb->ioext->ex_end;
if (pb->io_res.arena) {
io_base = pb->io_res.min_addr;
io_limit = pb->io_res.max_addr;
} else {
io_base = 0x1000; /* 4K */
io_limit = 0x0000;
@ -998,8 +1057,8 @@ configure_bridge(pciconf_dev_t *pd)
/* Configure mem base & limit */
bad_range = false;
if (pb->memext) {
bad_range = constrain_bridge_mem_range(pb->memext,
if (pb->mem_res.arena) {
bad_range = constrain_bridge_mem_range(&pb->mem_res,
&mem_base,
&mem_limit,
false);
@ -1023,8 +1082,8 @@ configure_bridge(pciconf_dev_t *pd)
mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG);
isprefetchmem64 = PCI_BRIDGE_PREFETCHMEM_64BITS(mem);
bad_range = false;
if (pb->pmemext) {
bad_range = constrain_bridge_mem_range(pb->pmemext,
if (pb->pmem_res.arena) {
bad_range = constrain_bridge_mem_range(&pb->pmem_res,
&mem_base,
&mem_limit,
isprefetchmem64);
@ -1058,12 +1117,10 @@ configure_bridge(pciconf_dev_t *pd)
rv = configure_bus(pb);
if (pb->ioext)
extent_destroy(pb->ioext);
if (pb->memext)
extent_destroy(pb->memext);
if (pb->pmemext)
extent_destroy(pb->pmemext);
fini_range_resource(&pb->io_res);
fini_range_resource(&pb->mem_res);
fini_range_resource(&pb->pmem_res);
if (rv == 0) {
cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG);
cmd &= ~PCI_BRIDGE_CONTROL; /* Clear control bit first */
@ -1191,27 +1248,20 @@ configure_bus(pciconf_bus_t *pb)
}
static bool
mem_region_ok64(struct extent * const ex __used_only_lp64)
mem_region_ok64(struct pciconf_resource * const r __used_only_lp64)
{
bool rv = false;
#ifdef _LP64
/*
* XXX We need to guard this with _LP64 because
* extent maps use u_long internally.
* XXX We need to guard this with _LP64 because vmem uses
* uintptr_t internally.
*/
u_long addr64;
if (ex->ex_end > (1UL << 32) &&
extent_alloc_subregion(ex, MAX((1UL << 32), ex->ex_start),
ex->ex_end,
1 /* size */,
1 /* alignment */,
0 /* boundary */,
EX_NOWAIT,
&addr64) == 0) {
(void) extent_free(ex, addr64,
1 /* size */,
EX_NOWAIT);
vmem_size_t result;
if (vmem_xalloc(r->arena, 1/*size*/, 1/*align*/, 0/*phase*/,
0/*nocross*/, (1UL << 32), VMEM_ADDR_MAX,
VM_INSTANTFIT | VM_NOSLEEP, &result) == 0) {
vmem_free(r->arena, result, 1);
rv = true;
}
#endif /* _LP64 */
@ -1219,6 +1269,81 @@ mem_region_ok64(struct extent * const ex __used_only_lp64)
return rv;
}
/*
* pciconf_resource_init:
*
* Allocate and initilize a pci configuration resources container.
*/
struct pciconf_resources *
pciconf_resource_init(void)
{
struct pciconf_resources *rs;
rs = kmem_zalloc(sizeof(*rs), KM_SLEEP);
return (rs);
}
/*
* pciconf_resource_fini:
*
* Dispose of a pci configuration resources container.
*/
void
pciconf_resource_fini(struct pciconf_resources *rs)
{
int i;
for (i = 0; i < PCICONF_RESOURCE_NTYPES; i++) {
fini_range_resource(&rs->resources[i]);
}
kmem_free(rs, sizeof(*rs));
}
/*
* pciconf_resource_add:
*
* Add a pci configuration resource to a container.
*/
int
pciconf_resource_add(struct pciconf_resources *rs, int type,
bus_addr_t start, bus_size_t size)
{
bus_addr_t end = start + (size - 1);
struct pciconf_resource *r;
int error;
bool first;
if (size == 0 || end <= start)
return EINVAL;
if (type < 0 || type >= PCICONF_RESOURCE_NTYPES)
return EINVAL;
r = &rs->resources[type];
first = r->arena == NULL;
if (first) {
r->arena = create_vmem_arena(pciconf_resource_names[type],
0, 0, VM_SLEEP);
r->min_addr = VMEM_ADDR_MAX;
r->max_addr = VMEM_ADDR_MIN;
}
error = vmem_add(r->arena, start, size, VM_SLEEP);
if (error == 0) {
if (start < r->min_addr)
r->min_addr = start;
if (end > r->max_addr)
r->max_addr = end;
}
r->total_size += size;
return 0;
}
/*
* Let's configure the PCI bus.
* This consists of basically scanning for all existing devices,
@ -1247,9 +1372,8 @@ mem_region_ok64(struct extent * const ex __used_only_lp64)
* bridges are probed and configured recursively.
*/
int
pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext,
struct extent *memext, struct extent *pmemext, int firstbus,
int cacheline_size)
pci_configure_bus(pci_chipset_tag_t pc, struct pciconf_resources *rs,
int firstbus, int cacheline_size)
{
pciconf_bus_t *pb;
int rv;
@ -1262,19 +1386,22 @@ pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext,
pb->parent_bus = NULL;
pb->swiz = 0;
pb->io_32bit = 1;
pb->ioext = ioext;
pb->memext = memext;
if (pmemext == NULL)
pb->pmemext = memext;
else
pb->pmemext = pmemext;
pb->io_res = rs->resources[PCICONF_RESOURCE_IO];
pb->mem_res = rs->resources[PCICONF_RESOURCE_MEM];
if (pb->mem_res.arena == NULL)
pb->mem_res = rs->resources[PCICONF_RESOURCE_PREFETCHABLE_MEM];
pb->pmem_res = rs->resources[PCICONF_RESOURCE_PREFETCHABLE_MEM];
if (pb->pmem_res.arena == NULL)
pb->pmem_res = rs->resources[PCICONF_RESOURCE_MEM];
/*
* Probe the memory region extent maps to see
* if allocation of 64-bit addresses is possible.
* Probe the memory region arenas to see if allocation of
* 64-bit addresses is possible.
*/
pb->mem_64bit = mem_region_ok64(pb->memext);
pb->pmem_64bit = mem_region_ok64(pb->pmemext);
pb->mem_64bit = mem_region_ok64(&pb->mem_res);
pb->pmem_64bit = mem_region_ok64(&pb->pmem_res);
pb->pc = pc;
pb->io_total = pb->mem_total = pb->pmem_total = 0;

31
sys/dev/pci/pciconf.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pciconf.h,v 1.13 2020/06/17 13:09:16 thorpej Exp $ */
/* $NetBSD: pciconf.h,v 1.14 2020/07/07 03:38:49 thorpej Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -35,15 +35,30 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/extent.h>
#ifndef _DEV_PCI_PCICONF_H_
#define _DEV_PCI_PCICONF_H_
#include <sys/vmem.h>
struct pciconf_resources;
#define PCICONF_RESOURCE_IO 0
#define PCICONF_RESOURCE_MEM 1
#define PCICONF_RESOURCE_PREFETCHABLE_MEM 2
struct pciconf_resources *
pciconf_resource_init(void);
void pciconf_resource_fini(struct pciconf_resources *);
int pciconf_resource_add(struct pciconf_resources *, int,
bus_addr_t, bus_size_t);
/*
* args: pci_chipset_tag_t, io_extent, mem_extent, pmem_extent
* where pmem_extent is "pre-fetchable" memory -- if NULL, mem_extent will
* be used for both
* args: pci_chipset_tag_t, resources, firstbus, cacheline_size
* If no prefetchable memory resources are available, plain memory resources
* will be used for both.
*/
int pci_configure_bus(pci_chipset_tag_t, struct extent *,
struct extent *, struct extent *, int, int);
int pci_configure_bus(pci_chipset_tag_t, struct pciconf_resources *,
int, int);
/* Defined in machdep code. Returns the interrupt line to set */
/* args: chipset_tag, bus, dev, ipin, swiz, ptr to interrupt line */
@ -62,3 +77,5 @@ void pci_conf_interrupt(pci_chipset_tag_t, int, int, int, int, int *);
#define PCI_CONF_ENABLE_ROM 0x0100
#define PCI_CONF_DEFAULT 0x00ff
#define PCI_CONF_ALL 0x01ff
#endif /* _DEV_PCI_PCICONF_H_ */