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Add some dsb instructions to avoid Cortex A7 errata

This commit is contained in:
skrll 2014-10-29 23:01:46 +00:00
parent 3f1b0de1f2
commit ca7dddc968
1 changed files with 2 additions and 0 deletions
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2
sys/arch/arm/arm/cpufunc_asm_armv7.S
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@ -377,6 +377,7 @@ ENTRY_NP(armv7_dcache_inv_all)
b 1b b 1b
.Lnext_level_inv: .Lnext_level_inv:
dsb
mrc p15, 1, r0, c0, c0, 1 @ read CLIDR mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
ubfx ip, r0, #24, #3 @ narrow to LoC ubfx ip, r0, #24, #3 @ narrow to LoC
add r3, r3, #2 @ go to next level add r3, r3, #2 @ go to next level
@ -437,6 +438,7 @@ ENTRY_NP(armv7_dcache_wbinv_all)
b 1b b 1b
.Lnext_level_wbinv: .Lnext_level_wbinv:
dsb
mrc p15, 1, r0, c0, c0, 1 @ read CLIDR mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
ubfx ip, r0, #24, #3 @ narrow to LoC ubfx ip, r0, #24, #3 @ narrow to LoC
add r3, r3, #2 @ go to next level add r3, r3, #2 @ go to next level