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Reorganized, machine-independent z8530 driver, based on the sparc/sun3 zs.

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Uses autoconfig to attach keyboard, mouse, or tty.  (See z8530.doc)
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gwr 1996-01-24 01:07:21 +00:00
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76
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$NetBSD: z8530.doc,v 1.1 1996/01/24 01:07:21 gwr Exp $
Here are the results of my reorganization work on the zs driver.
Everything compiles and appears to work.
Enjoy!
Gordon Ross
----------------------------------------------------------------
This design has a "zs controller" named "zsc" with three
flavors of child drivers that can be attached above it.
The three child drivers are:
zstty: normal RS-232 line
kbd: sun keyboard
ms: sun mouse
Note that the machine-dependent parts are:
arch/sun3/include/z8530var.h
arch/sun3/dev/zs.c
(replicate those for new systems)
The Sun hardware dependent parts (Sun3 and SPARC) are:
kd* sun keyboard/display console stuff
event* sun "firm event" stuff
----------------------------------------------------------------
Here is how the autoconfig looks on a sun3:
zsc0 at obio0 addr 0x0 level 6 softpri 3
kbd0 at zsc0 channel 0
ms0 at zsc0 channel 1
zsc1 at obio0 addr 0x20000 level 6 softpri 3
zstty0 at zsc1 channel 0 (console)
zstty1 at zsc1 channel 1
----------------------------------------------------------------
Config lines:
In any config file (i.e. GENERIC, NEW_ZS, ...)
Note {kbd,ms} are sun-specific.
#
# New console (zs) stuff
#
zsc0 at obio? addr ?
zsc1 at obio? addr ?
kbd0 at zsc0 channel 0
ms0 at zsc0 channel 1
zstty* at zsc? channel ?
----------------------------------------------------------------
In conf/files.sun3
#
# Console (zs) related stuff
#
device zsc at obio {channel = -1}
file arch/sun3/dev/zs.c zsc needs-flag
file dev/ic/z8530sc.c zsc
device zstty at zsc: tty
file dev/ic/z8530tty.c zstty needs-flag
define zsevent
file dev/sun/event.c zsevent
device kbd at zsc: zsevent
file dev/sun/kbd.c kbd needs-flag
file dev/sun/kbd_tables.c kbd
file arch/sun3/dev/kd.c kbd
device ms at zsc: zsevent
file dev/sun/ms.c ms needs-flag

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/* $NetBSD: z8530sc.c,v 1.1 1996/01/24 01:07:23 gwr Exp $ */
/*
* Copyright (c) 1994 Gordon W. Ross
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)zs.c 8.1 (Berkeley) 7/19/93
*/
/*
* Zilog Z8530 Dual UART driver (common part)
*
* This file contains the machine-independent parts of the
* driver common to tty and keyboard/mouse sub-drivers.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/proc.h>
#include <sys/device.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/ioctl.h>
#include <sys/tty.h>
#include <sys/time.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <dev/ic/z8530reg.h>
#include <machine/z8530var.h>
int
zs_break(cs, set)
struct zs_chanstate *cs;
int set;
{
int s;
s = splzs();
if (set) {
cs->cs_preg[5] |= ZSWR5_BREAK;
cs->cs_creg[5] |= ZSWR5_BREAK;
} else {
cs->cs_preg[5] &= ~ZSWR5_BREAK;
cs->cs_creg[5] &= ~ZSWR5_BREAK;
}
ZS_WRITE(cs, 5, cs->cs_creg[5]);
splx(s);
}
/*
* Compute the current baud rate given a ZSCC channel.
*/
int
zs_getspeed(cs)
struct zs_chanstate *cs;
{
int tconst;
tconst = ZS_READ(cs, 12);
tconst |= ZS_READ(cs, 13) << 8;
return (TCONST_TO_BPS(cs->cs_pclk_div16, tconst));
}
/*
* drain on-chip fifo
*/
void
zs_iflush(cs)
struct zs_chanstate *cs;
{
u_char c, rr0, rr1;
for (;;) {
/* Is there input available? */
rr0 = *(cs->cs_reg_csr);
ZS_DELAY();
if ((rr0 & ZSRR0_RX_READY) == 0)
break;
/* Read the data. */
c = *(cs->cs_reg_data);
ZS_DELAY();
/* Need to read status register too? */
rr1 = ZS_READ(cs, 1);
if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
/* Clear the receive error. */
*(cs->cs_reg_csr) = ZSWR0_RESET_ERRORS;
ZS_DELAY();
}
}
}
/*
* Write the given register set to the given zs channel in the proper order.
* The channel must not be transmitting at the time. The receiver will
* be disabled for the time it takes to write all the registers.
* Call this with interrupts disabled.
*/
void
zs_loadchannelregs(cs)
struct zs_chanstate *cs;
{
u_char *reg;
int i;
/* Copy "pending" regs to "current" */
bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16);
reg = cs->cs_creg; /* current regs */
*(cs->cs_reg_csr) = ZSM_RESET_ERR; /* XXX: reset error condition */
ZS_DELAY();
#if 1
/*
* XXX: Is this really a good idea?
* XXX: Should go elsewhere! -gwr
*/
zs_iflush(cs); /* XXX */
#endif
/* baud clock divisor, stop bits, parity */
ZS_WRITE(cs, 4, reg[4]);
/* misc. TX/RX control bits */
ZS_WRITE(cs, 10, reg[10]);
/* char size, enable (RX/TX) */
ZS_WRITE(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);
ZS_WRITE(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);
/* interrupt enables: TX, TX, STATUS */
ZS_WRITE(cs, 1, reg[1]);
#if 0
/*
* Registers 2 and 9 are special because they are
* actually common to both channels, but must be
* programmed through channel A. The "zsc" attach
* function takes care of setting these registers
* and they should not be touched thereafter.
*/
/* interrupt vector */
ZS_WRITE(cs, 2, reg[2]);
/* master interrupt control */
ZS_WRITE(cs, 9, reg[9]);
#endif
/* clock mode control */
ZS_WRITE(cs, 11, reg[11]);
/* baud rate (lo/hi) */
ZS_WRITE(cs, 12, reg[12]);
ZS_WRITE(cs, 13, reg[13]);
/* Misc. control bits */
ZS_WRITE(cs, 14, reg[14]);
/* which lines cause status interrupts */
ZS_WRITE(cs, 15, reg[15]);
/* char size, enable (RX/TX)*/
ZS_WRITE(cs, 3, reg[3]);
ZS_WRITE(cs, 5, reg[5]);
}
/*
* ZS hardware interrupt. Scan all ZS channels. NB: we know here that
* channels are kept in (A,B) pairs.
*
* Do just a little, then get out; set a software interrupt if more
* work is needed.
*
* We deliberately ignore the vectoring Zilog gives us, and match up
* only the number of `reset interrupt under service' operations, not
* the order.
*/
int
zsc_intr_hard(arg)
void *arg;
{
register struct zsc_softc *zsc = arg;
register struct zs_chanstate *cs_a;
register struct zs_chanstate *cs_b;
register int rval, soft;
register u_char rr3;
cs_a = &zsc->zsc_cs[0];
cs_b = &zsc->zsc_cs[1];
rval = 0;
soft = 0;
/* Note: only channel A has an RR3 */
rr3 = ZS_READ(cs_a, 3);
/* Handle receive interrupts first. */
if (rr3 & ZSRR3_IP_A_RX)
(*cs_a->cs_ops->zsop_rxint)(cs_a);
if (rr3 & ZSRR3_IP_B_RX)
(*cs_b->cs_ops->zsop_rxint)(cs_b);
/* Handle transmit done interrupts. */
if (rr3 & ZSRR3_IP_A_TX)
(*cs_a->cs_ops->zsop_txint)(cs_a);
if (rr3 & ZSRR3_IP_B_TX)
(*cs_b->cs_ops->zsop_txint)(cs_b);
/* Handle status interrupts. */
if (rr3 & ZSRR3_IP_A_STAT)
(*cs_a->cs_ops->zsop_stint)(cs_a);
if (rr3 & ZSRR3_IP_B_STAT)
(*cs_b->cs_ops->zsop_stint)(cs_b);
/* Clear interrupt. */
if (rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX | ZSRR3_IP_A_STAT)) {
*(cs_a->cs_reg_csr) = ZSWR0_CLR_INTR;
ZS_DELAY();
rval |= 1;
}
if (rr3 & (ZSRR3_IP_B_RX | ZSRR3_IP_B_TX | ZSRR3_IP_B_STAT)) {
*(cs_b->cs_reg_csr) = ZSWR0_CLR_INTR;
ZS_DELAY();
rval |= 2;
}
if ((cs_a->cs_softreq) || (cs_b->cs_softreq))
{
/* This is a machine-dependent function. */
zsc_req_softint(zsc);
}
return (rval);
}
/*
* ZS software interrupt. Scan all channels for deferred interrupts.
*/
int
zsc_intr_soft(arg)
void *arg;
{
register struct zsc_softc *zsc = arg;
register struct zs_chanstate *cs;
register int req, rval, s, unit;
rval = 0;
for (unit = 0; unit < 2; unit++) {
cs = &zsc->zsc_cs[unit];
s = splzs();
req = cs->cs_softreq;
cs->cs_softreq = 0;
splx(s);
if (req) {
(*cs->cs_ops->zsop_softint)(cs);
rval = 1;
}
}
return (rval);
}
static int
zsnull_intr(cs)
struct zs_chanstate *cs;
{
ZS_WRITE(cs, 1, 0);
ZS_WRITE(cs, 15, 0);
}
static int
zsnull_softint(cs)
struct zs_chanstate *cs;
{
}
struct zsops zsops_null = {
zsnull_intr, /* receive char available */
zsnull_intr, /* external/status */
zsnull_intr, /* xmit buffer empty */
zsnull_softint, /* process software interrupt */
};

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/* $NetBSD: z8530sc.h,v 1.1 1996/01/24 01:07:24 gwr Exp $ */
/*
* Copyright (c) 1994 Gordon W. Ross
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)zsvar.h 8.1 (Berkeley) 6/11/93
*/
/*
* Function vector - per channel
*/
struct zsops {
int (*zsop_rxint)(); /* receive char available */
int (*zsop_stint)(); /* external/status */
int (*zsop_txint)(); /* xmit buffer empty */
int (*zsop_softint)(); /* process software interrupt */
};
extern struct zsops zsops_null;
/*
* Software state, per zs channel.
*/
struct zs_chanstate {
/* Pointers to the device registers. */
volatile u_char *cs_reg_csr; /* ctrl, status, and reg. number. */
volatile u_char *cs_reg_data; /* data or numbered register */
int cs_channel; /* sub-unit number */
void *cs_private; /* sub-driver data pointer */
struct zsops *cs_ops;
int cs_pclk_div16; /* PCLK / 16 */
int cs_defspeed; /* default baud rate (from PROM) */
/*
* We must keep a copy of the write registers as they are
* mostly write-only and we sometimes need to set and clear
* individual bits (e.g., in WR3). Not all of these are
* needed but 16 bytes is cheap and this makes the addressing
* simpler. Unfortunately, we can only write to some registers
* when the chip is not actually transmitting, so whenever
* we are expecting a `transmit done' interrupt the preg array
* is allowed to `get ahead' of the current values. In a
* few places we must change the current value of a register,
* rather than (or in addition to) the pending value; for these
* cs_creg[] contains the current value.
*/
u_char cs_creg[16]; /* current values */
u_char cs_preg[16]; /* pending values */
u_char cs_heldchange; /* change pending (creg != preg) */
u_char cs_rr0; /* last rr0 processed */
char cs_softreq; /* need soft interrupt call */
char cs__spare;
};
struct zsc_softc {
struct device zsc_dev; /* required first: base device */
struct zs_chanstate zsc_cs[2]; /* channel A and B soft state */
};
struct zsc_attach_args {
int channel; /* two serial channels per zsc */
int hwflags;
};
#define ZS_HWFLAG_CONSOLE 1

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/* $NetBSD: z8530var.h,v 1.1 1996/01/24 01:07:24 gwr Exp $ */
/*
* Copyright (c) 1994 Gordon W. Ross
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)zsvar.h 8.1 (Berkeley) 6/11/93
*/
/*
* Function vector - per channel
*/
struct zsops {
int (*zsop_rxint)(); /* receive char available */
int (*zsop_stint)(); /* external/status */
int (*zsop_txint)(); /* xmit buffer empty */
int (*zsop_softint)(); /* process software interrupt */
};
extern struct zsops zsops_null;
/*
* Software state, per zs channel.
*/
struct zs_chanstate {
/* Pointers to the device registers. */
volatile u_char *cs_reg_csr; /* ctrl, status, and reg. number. */
volatile u_char *cs_reg_data; /* data or numbered register */
int cs_channel; /* sub-unit number */
void *cs_private; /* sub-driver data pointer */
struct zsops *cs_ops;
int cs_pclk_div16; /* PCLK / 16 */
int cs_defspeed; /* default baud rate (from PROM) */
/*
* We must keep a copy of the write registers as they are
* mostly write-only and we sometimes need to set and clear
* individual bits (e.g., in WR3). Not all of these are
* needed but 16 bytes is cheap and this makes the addressing
* simpler. Unfortunately, we can only write to some registers
* when the chip is not actually transmitting, so whenever
* we are expecting a `transmit done' interrupt the preg array
* is allowed to `get ahead' of the current values. In a
* few places we must change the current value of a register,
* rather than (or in addition to) the pending value; for these
* cs_creg[] contains the current value.
*/
u_char cs_creg[16]; /* current values */
u_char cs_preg[16]; /* pending values */
u_char cs_heldchange; /* change pending (creg != preg) */
u_char cs_rr0; /* last rr0 processed */
char cs_softreq; /* need soft interrupt call */
char cs__spare;
};
struct zsc_softc {
struct device zsc_dev; /* required first: base device */
struct zs_chanstate zsc_cs[2]; /* channel A and B soft state */
};
struct zsc_attach_args {
int channel; /* two serial channels per zsc */
int hwflags;
};
#define ZS_HWFLAG_CONSOLE 1