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bugfixes:

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o SCI accesses SCI registers (not SCIF) correctly
 o If there is serial inputs in boot time, it could hangup in interrupt routine
 o some cleanups(KNF)
This commit is contained in:
msaitoh 2000-02-22 01:37:11 +00:00
parent 93b37b7f07
commit c956cdcabe
2 changed files with 262 additions and 272 deletions
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264
sys/arch/sh3/dev/sci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sci.c,v 1.5 2000/01/07 10:50:14 msaitoh Exp $ */ /* $NetBSD: sci.c,v 1.6 2000/02/22 01:37:11 msaitoh Exp $ */
/*- /*-
* Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved.
@ -237,6 +237,12 @@ u_int sci_rbuf_lowat = (SCI_RING_SIZE * 3) / 4;
#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
int sciconscflag = CONMODE; int sciconscflag = CONMODE;
#ifdef SCICN_SPEED
int scicn_speed = SCICN_SPEED;
#else
int scicn_speed = 9600;
#endif
#define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
#ifndef __GENERIC_SOFT_INTERRUPTS #ifndef __GENERIC_SOFT_INTERRUPTS
@ -290,7 +296,7 @@ WaitFor(mSec)
SHREG_TSTR |= TSTR_STR2; SHREG_TSTR |= TSTR_STR2;
/* wait for under flag ON of channel2 */ /* wait for under flag ON of channel2 */
while ((SHREG_TCR2 & 0x0100) == 0) while ((SHREG_TCR2 & TCR_UNF) == 0)
; ;
/* stop channel2 */ /* stop channel2 */
@ -315,7 +321,7 @@ InitializeSci(bps)
SHREG_SCSMR = 0x00; /* Async,8bit,NonParity,Even,1Stop,NoMulti */ SHREG_SCSMR = 0x00; /* Async,8bit,NonParity,Even,1Stop,NoMulti */
/* Bit Rate Register */ /* Bit Rate Register */
SHREG_SCBRR = divrnd(PCLOCK, 32 * bps) -1; SHREG_SCBRR = divrnd(PCLOCK, 32 * bps) - 1;
/* /*
* wait 1mSec, because Send/Recv must begin 1 bit period after * wait 1mSec, because Send/Recv must begin 1 bit period after
@ -326,7 +332,7 @@ InitializeSci(bps)
/* Send permission, Recieve permission ON */ /* Send permission, Recieve permission ON */
SHREG_SCSCR = SCSCR_TE | SCSCR_RE; SHREG_SCSCR = SCSCR_TE | SCSCR_RE;
/*Serial Status Register */ /* Serial Status Register */
SHREG_SCSSR &= SCSSR_TDRE; /* Clear Status */ SHREG_SCSSR &= SCSSR_TDRE; /* Clear Status */
#if 0 #if 0
@ -354,7 +360,7 @@ PutcSci(c)
/* clear ready flag */ /* clear ready flag */
SHREG_SCSSR &= ~SCSSR_TDRE; SHREG_SCSSR &= ~SCSSR_TDRE;
if (c == '\n'){ if (c == '\n') {
while ((SHREG_SCSSR & SCSSR_TDRE) == NULL) while ((SHREG_SCSSR & SCSSR_TDRE) == NULL)
; ;
@ -375,7 +381,7 @@ PutStrSci(s)
#if 0 #if 0
static int SciInit = 0; static int SciInit = 0;
if (SciInit == 0) { if (SciInit == 0) {
InitializeSci(SCICN_SPEED); InitializeSci(scicn_speed);
SciInit = 1; SciInit = 1;
} }
#endif #endif
@ -429,11 +435,11 @@ GetStrSci(s, size)
int size; int size;
{ {
for(; size ; size--){ for(; size ; size--) {
*s = GetcSci(); *s = GetcSci();
if (*s & 0x80) if (*s & 0x80)
return -1; return -1;
if (*s == CR){ if (*s == CR) {
*s = 0; *s = 0;
break; break;
} }
@ -793,7 +799,7 @@ sciopen(dev, flag, mode, p)
*/ */
t.c_ispeed = 0; t.c_ispeed = 0;
if (ISSET(sc->sc_hwflags, SCI_HW_CONSOLE)) { if (ISSET(sc->sc_hwflags, SCI_HW_CONSOLE)) {
t.c_ospeed = SCICN_SPEED; t.c_ospeed = scicn_speed;
t.c_cflag = sciconscflag; t.c_cflag = sciconscflag;
} else { } else {
t.c_ospeed = TTYDEF_SPEED; t.c_ospeed = TTYDEF_SPEED;
@ -994,9 +1000,9 @@ sci_break(sc, onoff)
{ {
if (onoff) if (onoff)
SHREG_SCSSR2 &= ~SCSSR2_TDFE; SHREG_SCSSR &= ~SCSSR_TDRE;
else else
SHREG_SCSSR2 |= SCSSR2_TDFE; SHREG_SCSSR |= SCSSR_TDRE;
#if 0 /* XXX */ #if 0 /* XXX */
if (!sc->sc_heldchange) { if (!sc->sc_heldchange) {
@ -1282,148 +1288,142 @@ sciintr(arg)
put = sc->sc_rbput; put = sc->sc_rbput;
cc = sc->sc_rbavail; cc = sc->sc_rbavail;
do { ssr = SHREG_SCSSR;
ssr = SHREG_SCSSR;
#if defined(DDB) || defined(KGDB) #if defined(DDB) || defined(KGDB)
if (ISSET(ssr, SCSSR_BRK)) { if (ISSET(ssr, SCSSR_BRK)) {
#ifdef DDB #ifdef DDB
if (ISSET(sc->sc_hwflags, SCI_HW_CONSOLE)) { if (ISSET(sc->sc_hwflags, SCI_HW_CONSOLE)) {
console_debugger(); console_debugger();
continue; }
}
#endif #endif
#ifdef KGDB #ifdef KGDB
if (ISSET(sc->sc_hwflags, SCI_HW_KGDB)) { if (ISSET(sc->sc_hwflags, SCI_HW_KGDB)) {
kgdb_connect(1); kgdb_connect(1);
continue;
}
#endif
} }
#endif
}
#endif /* DDB || KGDB */ #endif /* DDB || KGDB */
if ((SHREG_SCSSR & SCSSR_RDRF) != 0) { if ((SHREG_SCSSR & SCSSR_RDRF) != 0) {
if (cc > 0){ if (cc > 0) {
put[0] = SHREG_SCRDR; put[0] = SHREG_SCRDR;
put[1] = SHREG_SCSSR & 0x00ff; put[1] = SHREG_SCSSR & 0x00ff;
SHREG_SCSSR &= ~SCSSR_RDRF; SHREG_SCSSR &= ~SCSSR_RDRF;
put += 2; put += 2;
if (put >= end) if (put >= end)
put = sc->sc_rbuf; put = sc->sc_rbuf;
cc--; cc--;
}
/*
* Current string of incoming characters ended because
* no more data was available or we ran out of space.
* Schedule a receive event if any data was received.
* If we're out of space, turn off receive interrupts.
*/
sc->sc_rbput = put;
sc->sc_rbavail = cc;
if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
sc->sc_rx_ready = 1;
/*
* See if we are in danger of overflowing a buffer. If
* so, use hardware flow control to ease the pressure.
*/
if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
cc < sc->sc_r_hiwat) {
SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
#if 0
sci_hwiflow(sc);
#endif
}
/*
* If we're out of space, disable receive interrupts
* until the queue has drained a bit.
*/
if (!cc) {
SHREG_SCSCR &= ~SCSCR_RIE;
}
} else {
if (SHREG_SCSSR & SCSSR_RDRF) {
SHREG_SCSCR &= ~(SCSCR_TIE | SCSCR_RIE);
continue;
}
} }
#if 0 /*
msr = bus_space_read_1(iot, ioh, sci_msr); * Current string of incoming characters ended because
delta = msr ^ sc->sc_msr; * no more data was available or we ran out of space.
sc->sc_msr = msr; * Schedule a receive event if any data was received.
if (ISSET(delta, sc->sc_msr_mask)) { * If we're out of space, turn off receive interrupts.
SET(sc->sc_msr_delta, delta); */
sc->sc_rbput = put;
sc->sc_rbavail = cc;
if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
sc->sc_rx_ready = 1;
/* /*
* Pulse-per-second clock signal on edge of DCD? * See if we are in danger of overflowing a buffer. If
*/ * so, use hardware flow control to ease the pressure.
if (ISSET(delta, sc->sc_ppsmask)) { */
struct timeval tv; if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
if (ISSET(msr, sc->sc_ppsmask) == cc < sc->sc_r_hiwat) {
sc->sc_ppsassert) { SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
/* XXX nanotime() */ #if 0
microtime(&tv); sci_hwiflow(sc);
TIMEVAL_TO_TIMESPEC(&tv, #endif
&sc->ppsinfo.assert_timestamp); }
if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
timespecadd(&sc->ppsinfo.assert_timestamp, /*
* If we're out of space, disable receive interrupts
* until the queue has drained a bit.
*/
if (!cc) {
SHREG_SCSCR &= ~SCSCR_RIE;
}
} else {
if (SHREG_SCSSR & SCSSR_RDRF) {
SHREG_SCSCR &= ~(SCSCR_TIE | SCSCR_RIE);
}
}
#if 0
msr = bus_space_read_1(iot, ioh, sci_msr);
delta = msr ^ sc->sc_msr;
sc->sc_msr = msr;
if (ISSET(delta, sc->sc_msr_mask)) {
SET(sc->sc_msr_delta, delta);
/*
* Pulse-per-second clock signal on edge of DCD?
*/
if (ISSET(delta, sc->sc_ppsmask)) {
struct timeval tv;
if (ISSET(msr, sc->sc_ppsmask) ==
sc->sc_ppsassert) {
/* XXX nanotime() */
microtime(&tv);
TIMEVAL_TO_TIMESPEC(&tv,
&sc->ppsinfo.assert_timestamp);
if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
timespecadd(&sc->ppsinfo.assert_timestamp,
&sc->ppsparam.assert_offset, &sc->ppsparam.assert_offset,
&sc->ppsinfo.assert_timestamp); &sc->ppsinfo.assert_timestamp);
TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
} }
#ifdef PPS_SYNC #ifdef PPS_SYNC
if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
hardpps(&tv, tv.tv_usec); hardpps(&tv, tv.tv_usec);
#endif #endif
sc->ppsinfo.assert_sequence++; sc->ppsinfo.assert_sequence++;
sc->ppsinfo.current_mode = sc->ppsinfo.current_mode =
sc->ppsparam.mode; sc->ppsparam.mode;
} else if (ISSET(msr, sc->sc_ppsmask) == } else if (ISSET(msr, sc->sc_ppsmask) ==
sc->sc_ppsclear) { sc->sc_ppsclear) {
/* XXX nanotime() */ /* XXX nanotime() */
microtime(&tv); microtime(&tv);
TIMEVAL_TO_TIMESPEC(&tv, TIMEVAL_TO_TIMESPEC(&tv,
&sc->ppsinfo.clear_timestamp); &sc->ppsinfo.clear_timestamp);
if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
timespecadd(&sc->ppsinfo.clear_timestamp, timespecadd(&sc->ppsinfo.clear_timestamp,
&sc->ppsparam.clear_offset, &sc->ppsparam.clear_offset,
&sc->ppsinfo.clear_timestamp); &sc->ppsinfo.clear_timestamp);
TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
} }
#ifdef PPS_SYNC #ifdef PPS_SYNC
if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
hardpps(&tv, tv.tv_usec); hardpps(&tv, tv.tv_usec);
#endif #endif
sc->ppsinfo.clear_sequence++; sc->ppsinfo.clear_sequence++;
sc->ppsinfo.current_mode = sc->ppsinfo.current_mode =
sc->ppsparam.mode; sc->ppsparam.mode;
}
} }
/*
* Stop output immediately if we lose the output
* flow control signal or carrier detect.
*/
if (ISSET(~msr, sc->sc_msr_mask)) {
sc->sc_tbc = 0;
sc->sc_heldtbc = 0;
#ifdef SCI_DEBUG
if (sci_debug)
scistatus(sc, "sciintr ");
#endif
}
sc->sc_st_check = 1;
} }
/*
* Stop output immediately if we lose the output
* flow control signal or carrier detect.
*/
if (ISSET(~msr, sc->sc_msr_mask)) {
sc->sc_tbc = 0;
sc->sc_heldtbc = 0;
#ifdef SCI_DEBUG
if (sci_debug)
scistatus(sc, "sciintr ");
#endif
}
sc->sc_st_check = 1;
}
#endif #endif
} while (SHREG_SCSSR & SCSSR_RDRF);
/* /*
* Done handling any receive interrupts. See if data can be * Done handling any receive interrupts. See if data can be
@ -1509,13 +1509,7 @@ scicninit(cp)
struct consdev *cp; struct consdev *cp;
{ {
InitializeSci(SCICN_SPEED); InitializeSci(scicn_speed);
#if 0
sci_intr_init(); /* XXX msaitoh */
#endif
sci_puts("sci initialized.\n\r");
} }
#define sci_getc GetcSci #define sci_getc GetcSci

270
sys/arch/sh3/dev/scif.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: scif.c,v 1.6 2000/01/07 10:50:14 msaitoh Exp $ */ /* $NetBSD: scif.c,v 1.7 2000/02/22 01:37:11 msaitoh Exp $ */
/*- /*-
* Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved.
@ -239,6 +239,12 @@ u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4;
#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
int scifconscflag = CONMODE; int scifconscflag = CONMODE;
#ifdef SCIFCN_SPEED
unsigned int scifcn_speed = SCIFCN_SPEED;
#else
unsigned int scifcn_speed = 9600;
#endif
#define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
#ifndef __GENERIC_SOFT_INTERRUPTS #ifndef __GENERIC_SOFT_INTERRUPTS
@ -291,7 +297,7 @@ WaitFor(mSec)
SHREG_TSTR |= TSTR_STR2; SHREG_TSTR |= TSTR_STR2;
/* wait for under flag ON of channel2 */ /* wait for under flag ON of channel2 */
while ((SHREG_TCR2 & 0x0100) == 0) while ((SHREG_TCR2 & TCR_UNF) == 0)
; ;
/* stop channel2 */ /* stop channel2 */
@ -317,13 +323,16 @@ InitializeScif(bps)
#else #else
SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST; SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST;
#endif #endif
/*Serial Mode Register */ /* Serial Mode Register */
SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */ SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */
/*Bit Rate Register */ /* Bit Rate Register */
SHREG_SCBRR2 = divrnd(PCLOCK, 32 * bps) -1; SHREG_SCBRR2 = divrnd(PCLOCK, 32 * bps) - 1;
/*wait 1mSec, because Send/Recv must begin 1 bit period after BRR is set. */ /*
* wait 1mSec, because Send/Recv must begin 1 bit period after
* BRR is set.
*/
WaitFor(1); WaitFor(1);
#if 0 #if 0
@ -335,7 +344,7 @@ InitializeScif(bps)
/* Send permission, Recieve permission ON */ /* Send permission, Recieve permission ON */
SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE; SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE;
/*Serial Status Register */ /* Serial Status Register */
SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */ SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */
} }
@ -360,7 +369,7 @@ PutcScif(c)
/* clear ready flag */ /* clear ready flag */
SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND); SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND);
if (c == '\n'){ if (c == '\n') {
while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL)
; ;
@ -450,11 +459,11 @@ GetStrScif(s, size)
int size; int size;
{ {
for (; size ; size--){ for (; size ; size--) {
*s = GetcScif(); *s = GetcScif();
if (*s & 0x80) if (*s & 0x80)
return -1; return -1;
if (*s == CR){ if (*s == CR) {
*s = 0; *s = 0;
break; break;
} }
@ -831,7 +840,7 @@ scifopen(dev, flag, mode, p)
*/ */
t.c_ispeed = 0; t.c_ispeed = 0;
if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
t.c_ospeed = SCIFCN_SPEED; /* XXX (msaitoh) */ t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */
t.c_cflag = scifconscflag; t.c_cflag = scifconscflag;
} else { } else {
t.c_ospeed = TTYDEF_SPEED; t.c_ospeed = TTYDEF_SPEED;
@ -1327,159 +1336,152 @@ scifintr(arg)
put = sc->sc_rbput; put = sc->sc_rbput;
cc = sc->sc_rbavail; cc = sc->sc_rbavail;
do { ssr2 = SHREG_SCSSR2;
if (ISSET(ssr2, SCSSR2_BRK)) {
ssr2 = SHREG_SCSSR2; SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR);
if (ISSET(ssr2, SCSSR2_BRK)) {
SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR);
#if defined(DDB) || defined(KGDB) #if defined(DDB) || defined(KGDB)
#ifdef DDB #ifdef DDB
if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
console_debugger(); console_debugger();
continue; }
}
#endif #endif
#ifdef KGDB #ifdef KGDB
if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) {
kgdb_connect(1); kgdb_connect(1);
continue; }
}
#endif #endif
#endif /* DDB || KGDB */ #endif /* DDB || KGDB */
continue; }
count = SHREG_SCFDR2 & SCFDR2_RECVCNT;
if (count != 0) {
while ((cc > 0) && (count > 0)) {
put[0] = SHREG_SCFRDR2;
put[1] = (u_char)(SHREG_SCSSR2 & 0x00ff);
SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR);
put += 2;
if (put >= end)
put = sc->sc_rbuf;
cc--;
count--;
} }
count = SHREG_SCFDR2 & SCFDR2_RECVCNT;
if (count != 0) {
while ((cc > 0) && (count > 0)){
put[0] = SHREG_SCFRDR2;
put[1] = (u_char)(SHREG_SCSSR2 & 0x00ff);
SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR); /*
* Current string of incoming characters ended because
* no more data was available or we ran out of space.
* Schedule a receive event if any data was received.
* If we're out of space, turn off receive interrupts.
*/
sc->sc_rbput = put;
sc->sc_rbavail = cc;
if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
sc->sc_rx_ready = 1;
put += 2; /*
if (put >= end) * See if we are in danger of overflowing a buffer. If
put = sc->sc_rbuf; * so, use hardware flow control to ease the pressure.
cc--; */
count--; if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
} cc < sc->sc_r_hiwat) {
SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
/*
* Current string of incoming characters ended because
* no more data was available or we ran out of space.
* Schedule a receive event if any data was received.
* If we're out of space, turn off receive interrupts.
*/
sc->sc_rbput = put;
sc->sc_rbavail = cc;
if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
sc->sc_rx_ready = 1;
/*
* See if we are in danger of overflowing a buffer. If
* so, use hardware flow control to ease the pressure.
*/
if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
cc < sc->sc_r_hiwat) {
SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
#if 0 #if 0
scif_hwiflow(sc); scif_hwiflow(sc);
#endif #endif
}
/*
* If we're out of space, disable receive interrupts
* until the queue has drained a bit.
*/
if (!cc) {
SHREG_SCSCR2 &= ~SCSCR2_RIE;
}
} else {
if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) {
SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE);
continue;
}
} }
#if 0 /*
msr = bus_space_read_1(iot, ioh, scif_msr); * If we're out of space, disable receive interrupts
delta = msr ^ sc->sc_msr; * until the queue has drained a bit.
sc->sc_msr = msr; */
if (ISSET(delta, sc->sc_msr_mask)) { if (!cc) {
SET(sc->sc_msr_delta, delta); SHREG_SCSCR2 &= ~SCSCR2_RIE;
}
} else {
if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) {
SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE);
}
}
/* #if 0
* Pulse-per-second clock signal on edge of DCD? msr = bus_space_read_1(iot, ioh, scif_msr);
*/ delta = msr ^ sc->sc_msr;
if (ISSET(delta, sc->sc_ppsmask)) { sc->sc_msr = msr;
struct timeval tv; if (ISSET(delta, sc->sc_msr_mask)) {
if (ISSET(msr, sc->sc_ppsmask) == SET(sc->sc_msr_delta, delta);
sc->sc_ppsassert) {
/* XXX nanotime() */ /*
microtime(&tv); * Pulse-per-second clock signal on edge of DCD?
TIMEVAL_TO_TIMESPEC(&tv, */
&sc->ppsinfo.assert_timestamp); if (ISSET(delta, sc->sc_ppsmask)) {
if (sc->ppsparam.mode & PPS_OFFSETASSERT) { struct timeval tv;
timespecadd(&sc->ppsinfo.assert_timestamp, if (ISSET(msr, sc->sc_ppsmask) ==
sc->sc_ppsassert) {
/* XXX nanotime() */
microtime(&tv);
TIMEVAL_TO_TIMESPEC(&tv,
&sc->ppsinfo.assert_timestamp);
if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
timespecadd(&sc->ppsinfo.assert_timestamp,
&sc->ppsparam.assert_offset, &sc->ppsparam.assert_offset,
&sc->ppsinfo.assert_timestamp); &sc->ppsinfo.assert_timestamp);
TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
} }
#ifdef PPS_SYNC #ifdef PPS_SYNC
if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
hardpps(&tv, tv.tv_usec); hardpps(&tv, tv.tv_usec);
#endif #endif
sc->ppsinfo.assert_sequence++; sc->ppsinfo.assert_sequence++;
sc->ppsinfo.current_mode = sc->ppsinfo.current_mode =
sc->ppsparam.mode; sc->ppsparam.mode;
} else if (ISSET(msr, sc->sc_ppsmask) == } else if (ISSET(msr, sc->sc_ppsmask) ==
sc->sc_ppsclear) { sc->sc_ppsclear) {
/* XXX nanotime() */ /* XXX nanotime() */
microtime(&tv); microtime(&tv);
TIMEVAL_TO_TIMESPEC(&tv, TIMEVAL_TO_TIMESPEC(&tv,
&sc->ppsinfo.clear_timestamp); &sc->ppsinfo.clear_timestamp);
if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
timespecadd(&sc->ppsinfo.clear_timestamp, timespecadd(&sc->ppsinfo.clear_timestamp,
&sc->ppsparam.clear_offset, &sc->ppsparam.clear_offset,
&sc->ppsinfo.clear_timestamp); &sc->ppsinfo.clear_timestamp);
TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
} }
#ifdef PPS_SYNC #ifdef PPS_SYNC
if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
hardpps(&tv, tv.tv_usec); hardpps(&tv, tv.tv_usec);
#endif #endif
sc->ppsinfo.clear_sequence++; sc->ppsinfo.clear_sequence++;
sc->ppsinfo.current_mode = sc->ppsinfo.current_mode =
sc->ppsparam.mode; sc->ppsparam.mode;
}
} }
/*
* Stop output immediately if we lose the output
* flow control signal or carrier detect.
*/
if (ISSET(~msr, sc->sc_msr_mask)) {
sc->sc_tbc = 0;
sc->sc_heldtbc = 0;
#ifdef SCIF_DEBUG
if (scif_debug)
scifstatus(sc, "scifintr ");
#endif
}
sc->sc_st_check = 1;
} }
/*
* Stop output immediately if we lose the output
* flow control signal or carrier detect.
*/
if (ISSET(~msr, sc->sc_msr_mask)) {
sc->sc_tbc = 0;
sc->sc_heldtbc = 0;
#ifdef SCIF_DEBUG
if (scif_debug)
scifstatus(sc, "scifintr ");
#endif
}
sc->sc_st_check = 1;
}
#endif #endif
} while (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR));
/* /*
* Done handling any receive interrupts. See if data can be * Done handling any receive interrupts. See if data can be
* transmitted as well. Schedule tx done event if no data left * transmitted as well. Schedule tx done event if no data left
* and tty was marked busy. * and tty was marked busy.
*/ */
if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16){ /* XXX (msaitoh) */ if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */
/* /*
* If we've delayed a parameter change, do it now, and restart * If we've delayed a parameter change, do it now, and restart
* output. * output.
@ -1570,13 +1572,7 @@ scifcninit(cp)
struct consdev *cp; struct consdev *cp;
{ {
InitializeScif(SCIFCN_SPEED); InitializeScif(scifcn_speed);
#if 0
scif_intr_init(); /* XXX msaitoh */
#endif
scif_puts("scif initialized.\n\r");
} }
#define scif_getc GetcScif #define scif_getc GetcScif