bugfixes:
o SCI accesses SCI registers (not SCIF) correctly o If there is serial inputs in boot time, it could hangup in interrupt routine o some cleanups(KNF)
This commit is contained in:
msaitoh
parent
93b37b7f07
commit
c956cdcabe
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@ -1,4 +1,4 @@
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/* $NetBSD: sci.c,v 1.5 2000/01/07 10:50:14 msaitoh Exp $ */
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/* $NetBSD: sci.c,v 1.6 2000/02/22 01:37:11 msaitoh Exp $ */
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/*-
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* Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved.
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@ -237,6 +237,12 @@ u_int sci_rbuf_lowat = (SCI_RING_SIZE * 3) / 4;
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#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
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int sciconscflag = CONMODE;
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#ifdef SCICN_SPEED
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int scicn_speed = SCICN_SPEED;
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#else
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int scicn_speed = 9600;
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#endif
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#define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
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#ifndef __GENERIC_SOFT_INTERRUPTS
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@ -290,7 +296,7 @@ WaitFor(mSec)
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SHREG_TSTR |= TSTR_STR2;
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/* wait for under flag ON of channel2 */
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while ((SHREG_TCR2 & 0x0100) == 0)
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while ((SHREG_TCR2 & TCR_UNF) == 0)
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;
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/* stop channel2 */
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@ -315,7 +321,7 @@ InitializeSci(bps)
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SHREG_SCSMR = 0x00; /* Async,8bit,NonParity,Even,1Stop,NoMulti */
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/* Bit Rate Register */
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SHREG_SCBRR = divrnd(PCLOCK, 32 * bps) -1;
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SHREG_SCBRR = divrnd(PCLOCK, 32 * bps) - 1;
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/*
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* wait 1mSec, because Send/Recv must begin 1 bit period after
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@ -326,7 +332,7 @@ InitializeSci(bps)
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/* Send permission, Recieve permission ON */
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SHREG_SCSCR = SCSCR_TE | SCSCR_RE;
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/*Serial Status Register */
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/* Serial Status Register */
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SHREG_SCSSR &= SCSSR_TDRE; /* Clear Status */
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#if 0
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@ -354,7 +360,7 @@ PutcSci(c)
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/* clear ready flag */
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SHREG_SCSSR &= ~SCSSR_TDRE;
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if (c == '\n'){
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if (c == '\n') {
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while ((SHREG_SCSSR & SCSSR_TDRE) == NULL)
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;
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@ -375,7 +381,7 @@ PutStrSci(s)
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#if 0
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static int SciInit = 0;
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if (SciInit == 0) {
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InitializeSci(SCICN_SPEED);
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InitializeSci(scicn_speed);
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SciInit = 1;
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}
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#endif
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@ -429,11 +435,11 @@ GetStrSci(s, size)
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int size;
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{
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for(; size ; size--){
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for(; size ; size--) {
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*s = GetcSci();
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if (*s & 0x80)
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return -1;
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if (*s == CR){
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if (*s == CR) {
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*s = 0;
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break;
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}
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@ -793,7 +799,7 @@ sciopen(dev, flag, mode, p)
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*/
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t.c_ispeed = 0;
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if (ISSET(sc->sc_hwflags, SCI_HW_CONSOLE)) {
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t.c_ospeed = SCICN_SPEED;
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t.c_ospeed = scicn_speed;
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t.c_cflag = sciconscflag;
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} else {
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t.c_ospeed = TTYDEF_SPEED;
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@ -994,9 +1000,9 @@ sci_break(sc, onoff)
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{
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if (onoff)
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SHREG_SCSSR2 &= ~SCSSR2_TDFE;
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SHREG_SCSSR &= ~SCSSR_TDRE;
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else
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SHREG_SCSSR2 |= SCSSR2_TDFE;
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SHREG_SCSSR |= SCSSR_TDRE;
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#if 0 /* XXX */
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if (!sc->sc_heldchange) {
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@ -1282,148 +1288,142 @@ sciintr(arg)
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put = sc->sc_rbput;
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cc = sc->sc_rbavail;
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do {
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ssr = SHREG_SCSSR;
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ssr = SHREG_SCSSR;
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#if defined(DDB) || defined(KGDB)
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if (ISSET(ssr, SCSSR_BRK)) {
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if (ISSET(ssr, SCSSR_BRK)) {
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#ifdef DDB
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if (ISSET(sc->sc_hwflags, SCI_HW_CONSOLE)) {
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console_debugger();
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continue;
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}
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if (ISSET(sc->sc_hwflags, SCI_HW_CONSOLE)) {
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console_debugger();
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}
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#endif
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#ifdef KGDB
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if (ISSET(sc->sc_hwflags, SCI_HW_KGDB)) {
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kgdb_connect(1);
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continue;
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}
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#endif
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if (ISSET(sc->sc_hwflags, SCI_HW_KGDB)) {
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kgdb_connect(1);
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}
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#endif
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}
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#endif /* DDB || KGDB */
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if ((SHREG_SCSSR & SCSSR_RDRF) != 0) {
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if (cc > 0){
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put[0] = SHREG_SCRDR;
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put[1] = SHREG_SCSSR & 0x00ff;
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if ((SHREG_SCSSR & SCSSR_RDRF) != 0) {
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if (cc > 0) {
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put[0] = SHREG_SCRDR;
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put[1] = SHREG_SCSSR & 0x00ff;
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SHREG_SCSSR &= ~SCSSR_RDRF;
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SHREG_SCSSR &= ~SCSSR_RDRF;
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put += 2;
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if (put >= end)
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put = sc->sc_rbuf;
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cc--;
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}
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/*
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* Current string of incoming characters ended because
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* no more data was available or we ran out of space.
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* Schedule a receive event if any data was received.
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* If we're out of space, turn off receive interrupts.
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*/
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sc->sc_rbput = put;
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sc->sc_rbavail = cc;
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if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
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sc->sc_rx_ready = 1;
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/*
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* See if we are in danger of overflowing a buffer. If
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* so, use hardware flow control to ease the pressure.
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*/
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if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
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cc < sc->sc_r_hiwat) {
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SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
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#if 0
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sci_hwiflow(sc);
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#endif
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}
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/*
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* If we're out of space, disable receive interrupts
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* until the queue has drained a bit.
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*/
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if (!cc) {
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SHREG_SCSCR &= ~SCSCR_RIE;
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}
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} else {
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if (SHREG_SCSSR & SCSSR_RDRF) {
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SHREG_SCSCR &= ~(SCSCR_TIE | SCSCR_RIE);
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continue;
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}
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put += 2;
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if (put >= end)
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put = sc->sc_rbuf;
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cc--;
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}
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#if 0
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msr = bus_space_read_1(iot, ioh, sci_msr);
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delta = msr ^ sc->sc_msr;
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sc->sc_msr = msr;
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if (ISSET(delta, sc->sc_msr_mask)) {
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SET(sc->sc_msr_delta, delta);
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/*
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* Current string of incoming characters ended because
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* no more data was available or we ran out of space.
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* Schedule a receive event if any data was received.
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* If we're out of space, turn off receive interrupts.
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*/
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sc->sc_rbput = put;
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sc->sc_rbavail = cc;
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if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
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sc->sc_rx_ready = 1;
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/*
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* Pulse-per-second clock signal on edge of DCD?
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*/
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if (ISSET(delta, sc->sc_ppsmask)) {
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struct timeval tv;
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if (ISSET(msr, sc->sc_ppsmask) ==
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sc->sc_ppsassert) {
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/* XXX nanotime() */
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microtime(&tv);
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TIMEVAL_TO_TIMESPEC(&tv,
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&sc->ppsinfo.assert_timestamp);
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if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
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timespecadd(&sc->ppsinfo.assert_timestamp,
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/*
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* See if we are in danger of overflowing a buffer. If
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* so, use hardware flow control to ease the pressure.
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*/
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if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
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cc < sc->sc_r_hiwat) {
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SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
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#if 0
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sci_hwiflow(sc);
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#endif
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}
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/*
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* If we're out of space, disable receive interrupts
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* until the queue has drained a bit.
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*/
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if (!cc) {
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SHREG_SCSCR &= ~SCSCR_RIE;
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}
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} else {
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if (SHREG_SCSSR & SCSSR_RDRF) {
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SHREG_SCSCR &= ~(SCSCR_TIE | SCSCR_RIE);
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}
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}
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#if 0
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msr = bus_space_read_1(iot, ioh, sci_msr);
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delta = msr ^ sc->sc_msr;
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sc->sc_msr = msr;
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if (ISSET(delta, sc->sc_msr_mask)) {
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SET(sc->sc_msr_delta, delta);
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/*
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* Pulse-per-second clock signal on edge of DCD?
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*/
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if (ISSET(delta, sc->sc_ppsmask)) {
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struct timeval tv;
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if (ISSET(msr, sc->sc_ppsmask) ==
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sc->sc_ppsassert) {
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/* XXX nanotime() */
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microtime(&tv);
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TIMEVAL_TO_TIMESPEC(&tv,
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&sc->ppsinfo.assert_timestamp);
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if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
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timespecadd(&sc->ppsinfo.assert_timestamp,
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&sc->ppsparam.assert_offset,
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&sc->ppsinfo.assert_timestamp);
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TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
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}
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TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
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}
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#ifdef PPS_SYNC
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if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
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hardpps(&tv, tv.tv_usec);
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if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
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hardpps(&tv, tv.tv_usec);
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#endif
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sc->ppsinfo.assert_sequence++;
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sc->ppsinfo.current_mode =
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sc->ppsparam.mode;
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sc->ppsinfo.assert_sequence++;
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sc->ppsinfo.current_mode =
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sc->ppsparam.mode;
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} else if (ISSET(msr, sc->sc_ppsmask) ==
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sc->sc_ppsclear) {
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/* XXX nanotime() */
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microtime(&tv);
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TIMEVAL_TO_TIMESPEC(&tv,
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&sc->ppsinfo.clear_timestamp);
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if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
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timespecadd(&sc->ppsinfo.clear_timestamp,
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} else if (ISSET(msr, sc->sc_ppsmask) ==
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sc->sc_ppsclear) {
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/* XXX nanotime() */
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microtime(&tv);
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TIMEVAL_TO_TIMESPEC(&tv,
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&sc->ppsinfo.clear_timestamp);
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if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
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timespecadd(&sc->ppsinfo.clear_timestamp,
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&sc->ppsparam.clear_offset,
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&sc->ppsinfo.clear_timestamp);
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TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
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}
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TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
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}
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#ifdef PPS_SYNC
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if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
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hardpps(&tv, tv.tv_usec);
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if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
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hardpps(&tv, tv.tv_usec);
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#endif
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sc->ppsinfo.clear_sequence++;
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sc->ppsinfo.current_mode =
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sc->ppsparam.mode;
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}
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sc->ppsinfo.clear_sequence++;
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sc->ppsinfo.current_mode =
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sc->ppsparam.mode;
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}
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/*
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* Stop output immediately if we lose the output
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* flow control signal or carrier detect.
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*/
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if (ISSET(~msr, sc->sc_msr_mask)) {
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sc->sc_tbc = 0;
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sc->sc_heldtbc = 0;
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#ifdef SCI_DEBUG
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if (sci_debug)
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scistatus(sc, "sciintr ");
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#endif
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}
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sc->sc_st_check = 1;
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}
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/*
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* Stop output immediately if we lose the output
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* flow control signal or carrier detect.
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*/
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if (ISSET(~msr, sc->sc_msr_mask)) {
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sc->sc_tbc = 0;
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sc->sc_heldtbc = 0;
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#ifdef SCI_DEBUG
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if (sci_debug)
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scistatus(sc, "sciintr ");
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#endif
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}
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sc->sc_st_check = 1;
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}
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#endif
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} while (SHREG_SCSSR & SCSSR_RDRF);
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/*
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* Done handling any receive interrupts. See if data can be
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@ -1509,13 +1509,7 @@ scicninit(cp)
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struct consdev *cp;
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{
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InitializeSci(SCICN_SPEED);
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#if 0
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sci_intr_init(); /* XXX msaitoh */
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#endif
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sci_puts("sci initialized.\n\r");
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InitializeSci(scicn_speed);
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}
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#define sci_getc GetcSci
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@ -1,4 +1,4 @@
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/* $NetBSD: scif.c,v 1.6 2000/01/07 10:50:14 msaitoh Exp $ */
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/* $NetBSD: scif.c,v 1.7 2000/02/22 01:37:11 msaitoh Exp $ */
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/*-
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* Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved.
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@ -239,6 +239,12 @@ u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4;
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#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
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int scifconscflag = CONMODE;
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#ifdef SCIFCN_SPEED
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unsigned int scifcn_speed = SCIFCN_SPEED;
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#else
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unsigned int scifcn_speed = 9600;
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#endif
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#define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
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#ifndef __GENERIC_SOFT_INTERRUPTS
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@ -291,7 +297,7 @@ WaitFor(mSec)
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SHREG_TSTR |= TSTR_STR2;
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/* wait for under flag ON of channel2 */
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while ((SHREG_TCR2 & 0x0100) == 0)
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while ((SHREG_TCR2 & TCR_UNF) == 0)
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;
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/* stop channel2 */
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@ -317,13 +323,16 @@ InitializeScif(bps)
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#else
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SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST;
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#endif
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/*Serial Mode Register */
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/* Serial Mode Register */
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SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */
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/*Bit Rate Register */
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SHREG_SCBRR2 = divrnd(PCLOCK, 32 * bps) -1;
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/* Bit Rate Register */
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SHREG_SCBRR2 = divrnd(PCLOCK, 32 * bps) - 1;
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/*wait 1mSec, because Send/Recv must begin 1 bit period after BRR is set. */
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/*
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* wait 1mSec, because Send/Recv must begin 1 bit period after
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* BRR is set.
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*/
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WaitFor(1);
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#if 0
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@ -335,7 +344,7 @@ InitializeScif(bps)
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/* Send permission, Recieve permission ON */
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SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE;
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/*Serial Status Register */
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/* Serial Status Register */
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SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */
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}
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@ -360,7 +369,7 @@ PutcScif(c)
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/* clear ready flag */
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SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND);
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if (c == '\n'){
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if (c == '\n') {
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while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL)
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;
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@ -450,11 +459,11 @@ GetStrScif(s, size)
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int size;
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{
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for (; size ; size--){
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for (; size ; size--) {
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*s = GetcScif();
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if (*s & 0x80)
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return -1;
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if (*s == CR){
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if (*s == CR) {
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*s = 0;
|
||||
break;
|
||||
}
|
||||
|
|
@ -831,7 +840,7 @@ scifopen(dev, flag, mode, p)
|
|||
*/
|
||||
t.c_ispeed = 0;
|
||||
if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
|
||||
t.c_ospeed = SCIFCN_SPEED; /* XXX (msaitoh) */
|
||||
t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */
|
||||
t.c_cflag = scifconscflag;
|
||||
} else {
|
||||
t.c_ospeed = TTYDEF_SPEED;
|
||||
|
|
@ -1327,159 +1336,152 @@ scifintr(arg)
|
|||
put = sc->sc_rbput;
|
||||
cc = sc->sc_rbavail;
|
||||
|
||||
do {
|
||||
|
||||
ssr2 = SHREG_SCSSR2;
|
||||
if (ISSET(ssr2, SCSSR2_BRK)) {
|
||||
SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR);
|
||||
ssr2 = SHREG_SCSSR2;
|
||||
if (ISSET(ssr2, SCSSR2_BRK)) {
|
||||
SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR);
|
||||
#if defined(DDB) || defined(KGDB)
|
||||
#ifdef DDB
|
||||
if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
|
||||
console_debugger();
|
||||
continue;
|
||||
}
|
||||
if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
|
||||
console_debugger();
|
||||
}
|
||||
#endif
|
||||
#ifdef KGDB
|
||||
if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) {
|
||||
kgdb_connect(1);
|
||||
continue;
|
||||
}
|
||||
if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) {
|
||||
kgdb_connect(1);
|
||||
}
|
||||
#endif
|
||||
#endif /* DDB || KGDB */
|
||||
continue;
|
||||
}
|
||||
count = SHREG_SCFDR2 & SCFDR2_RECVCNT;
|
||||
if (count != 0) {
|
||||
while ((cc > 0) && (count > 0)) {
|
||||
put[0] = SHREG_SCFRDR2;
|
||||
put[1] = (u_char)(SHREG_SCSSR2 & 0x00ff);
|
||||
|
||||
SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR);
|
||||
|
||||
put += 2;
|
||||
if (put >= end)
|
||||
put = sc->sc_rbuf;
|
||||
cc--;
|
||||
count--;
|
||||
}
|
||||
count = SHREG_SCFDR2 & SCFDR2_RECVCNT;
|
||||
if (count != 0) {
|
||||
while ((cc > 0) && (count > 0)){
|
||||
put[0] = SHREG_SCFRDR2;
|
||||
put[1] = (u_char)(SHREG_SCSSR2 & 0x00ff);
|
||||
|
||||
SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR);
|
||||
/*
|
||||
* Current string of incoming characters ended because
|
||||
* no more data was available or we ran out of space.
|
||||
* Schedule a receive event if any data was received.
|
||||
* If we're out of space, turn off receive interrupts.
|
||||
*/
|
||||
sc->sc_rbput = put;
|
||||
sc->sc_rbavail = cc;
|
||||
if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
|
||||
sc->sc_rx_ready = 1;
|
||||
|
||||
put += 2;
|
||||
if (put >= end)
|
||||
put = sc->sc_rbuf;
|
||||
cc--;
|
||||
count--;
|
||||
}
|
||||
|
||||
/*
|
||||
* Current string of incoming characters ended because
|
||||
* no more data was available or we ran out of space.
|
||||
* Schedule a receive event if any data was received.
|
||||
* If we're out of space, turn off receive interrupts.
|
||||
*/
|
||||
sc->sc_rbput = put;
|
||||
sc->sc_rbavail = cc;
|
||||
if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
|
||||
sc->sc_rx_ready = 1;
|
||||
|
||||
/*
|
||||
* See if we are in danger of overflowing a buffer. If
|
||||
* so, use hardware flow control to ease the pressure.
|
||||
*/
|
||||
if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
|
||||
cc < sc->sc_r_hiwat) {
|
||||
SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
|
||||
/*
|
||||
* See if we are in danger of overflowing a buffer. If
|
||||
* so, use hardware flow control to ease the pressure.
|
||||
*/
|
||||
if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
|
||||
cc < sc->sc_r_hiwat) {
|
||||
SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
|
||||
#if 0
|
||||
scif_hwiflow(sc);
|
||||
scif_hwiflow(sc);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* If we're out of space, disable receive interrupts
|
||||
* until the queue has drained a bit.
|
||||
*/
|
||||
if (!cc) {
|
||||
SHREG_SCSCR2 &= ~SCSCR2_RIE;
|
||||
}
|
||||
} else {
|
||||
if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) {
|
||||
SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
msr = bus_space_read_1(iot, ioh, scif_msr);
|
||||
delta = msr ^ sc->sc_msr;
|
||||
sc->sc_msr = msr;
|
||||
if (ISSET(delta, sc->sc_msr_mask)) {
|
||||
SET(sc->sc_msr_delta, delta);
|
||||
/*
|
||||
* If we're out of space, disable receive interrupts
|
||||
* until the queue has drained a bit.
|
||||
*/
|
||||
if (!cc) {
|
||||
SHREG_SCSCR2 &= ~SCSCR2_RIE;
|
||||
}
|
||||
} else {
|
||||
if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) {
|
||||
SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Pulse-per-second clock signal on edge of DCD?
|
||||
*/
|
||||
if (ISSET(delta, sc->sc_ppsmask)) {
|
||||
struct timeval tv;
|
||||
if (ISSET(msr, sc->sc_ppsmask) ==
|
||||
sc->sc_ppsassert) {
|
||||
/* XXX nanotime() */
|
||||
microtime(&tv);
|
||||
TIMEVAL_TO_TIMESPEC(&tv,
|
||||
&sc->ppsinfo.assert_timestamp);
|
||||
if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
|
||||
timespecadd(&sc->ppsinfo.assert_timestamp,
|
||||
#if 0
|
||||
msr = bus_space_read_1(iot, ioh, scif_msr);
|
||||
delta = msr ^ sc->sc_msr;
|
||||
sc->sc_msr = msr;
|
||||
if (ISSET(delta, sc->sc_msr_mask)) {
|
||||
SET(sc->sc_msr_delta, delta);
|
||||
|
||||
/*
|
||||
* Pulse-per-second clock signal on edge of DCD?
|
||||
*/
|
||||
if (ISSET(delta, sc->sc_ppsmask)) {
|
||||
struct timeval tv;
|
||||
if (ISSET(msr, sc->sc_ppsmask) ==
|
||||
sc->sc_ppsassert) {
|
||||
/* XXX nanotime() */
|
||||
microtime(&tv);
|
||||
TIMEVAL_TO_TIMESPEC(&tv,
|
||||
&sc->ppsinfo.assert_timestamp);
|
||||
if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
|
||||
timespecadd(&sc->ppsinfo.assert_timestamp,
|
||||
&sc->ppsparam.assert_offset,
|
||||
&sc->ppsinfo.assert_timestamp);
|
||||
TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
|
||||
}
|
||||
TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
|
||||
}
|
||||
|
||||
#ifdef PPS_SYNC
|
||||
if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
|
||||
hardpps(&tv, tv.tv_usec);
|
||||
if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
|
||||
hardpps(&tv, tv.tv_usec);
|
||||
#endif
|
||||
sc->ppsinfo.assert_sequence++;
|
||||
sc->ppsinfo.current_mode =
|
||||
sc->ppsparam.mode;
|
||||
sc->ppsinfo.assert_sequence++;
|
||||
sc->ppsinfo.current_mode =
|
||||
sc->ppsparam.mode;
|
||||
|
||||
} else if (ISSET(msr, sc->sc_ppsmask) ==
|
||||
sc->sc_ppsclear) {
|
||||
/* XXX nanotime() */
|
||||
microtime(&tv);
|
||||
TIMEVAL_TO_TIMESPEC(&tv,
|
||||
&sc->ppsinfo.clear_timestamp);
|
||||
if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
|
||||
timespecadd(&sc->ppsinfo.clear_timestamp,
|
||||
} else if (ISSET(msr, sc->sc_ppsmask) ==
|
||||
sc->sc_ppsclear) {
|
||||
/* XXX nanotime() */
|
||||
microtime(&tv);
|
||||
TIMEVAL_TO_TIMESPEC(&tv,
|
||||
&sc->ppsinfo.clear_timestamp);
|
||||
if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
|
||||
timespecadd(&sc->ppsinfo.clear_timestamp,
|
||||
&sc->ppsparam.clear_offset,
|
||||
&sc->ppsinfo.clear_timestamp);
|
||||
TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
|
||||
}
|
||||
TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
|
||||
}
|
||||
|
||||
#ifdef PPS_SYNC
|
||||
if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
|
||||
hardpps(&tv, tv.tv_usec);
|
||||
if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
|
||||
hardpps(&tv, tv.tv_usec);
|
||||
#endif
|
||||
sc->ppsinfo.clear_sequence++;
|
||||
sc->ppsinfo.current_mode =
|
||||
sc->ppsparam.mode;
|
||||
}
|
||||
sc->ppsinfo.clear_sequence++;
|
||||
sc->ppsinfo.current_mode =
|
||||
sc->ppsparam.mode;
|
||||
}
|
||||
|
||||
/*
|
||||
* Stop output immediately if we lose the output
|
||||
* flow control signal or carrier detect.
|
||||
*/
|
||||
if (ISSET(~msr, sc->sc_msr_mask)) {
|
||||
sc->sc_tbc = 0;
|
||||
sc->sc_heldtbc = 0;
|
||||
#ifdef SCIF_DEBUG
|
||||
if (scif_debug)
|
||||
scifstatus(sc, "scifintr ");
|
||||
#endif
|
||||
}
|
||||
|
||||
sc->sc_st_check = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Stop output immediately if we lose the output
|
||||
* flow control signal or carrier detect.
|
||||
*/
|
||||
if (ISSET(~msr, sc->sc_msr_mask)) {
|
||||
sc->sc_tbc = 0;
|
||||
sc->sc_heldtbc = 0;
|
||||
#ifdef SCIF_DEBUG
|
||||
if (scif_debug)
|
||||
scifstatus(sc, "scifintr ");
|
||||
#endif
|
||||
}
|
||||
|
||||
sc->sc_st_check = 1;
|
||||
}
|
||||
#endif
|
||||
} while (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR));
|
||||
|
||||
/*
|
||||
* Done handling any receive interrupts. See if data can be
|
||||
* transmitted as well. Schedule tx done event if no data left
|
||||
* and tty was marked busy.
|
||||
*/
|
||||
if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16){ /* XXX (msaitoh) */
|
||||
if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */
|
||||
/*
|
||||
* If we've delayed a parameter change, do it now, and restart
|
||||
* output.
|
||||
|
|
@ -1570,13 +1572,7 @@ scifcninit(cp)
|
|||
struct consdev *cp;
|
||||
{
|
||||
|
||||
InitializeScif(SCIFCN_SPEED);
|
||||
|
||||
#if 0
|
||||
scif_intr_init(); /* XXX msaitoh */
|
||||
#endif
|
||||
|
||||
scif_puts("scif initialized.\n\r");
|
||||
InitializeScif(scifcn_speed);
|
||||
}
|
||||
|
||||
#define scif_getc GetcScif
|
||||
|
|
|
|||
Loading…
Reference in New Issue