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Add MI softintr(9) support with common mips/softintr.c.

This commit is contained in:
tsutsui 2003-05-25 14:02:47 +00:00
parent 51260decbe
commit c9058cdc00
10 changed files with 173 additions and 165 deletions
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3
sys/arch/newsmips/apbus/zs_ap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: zs_ap.c,v 1.14 2003/05/09 17:39:12 tsutsui Exp $ */
/* $NetBSD: zs_ap.c,v 1.15 2003/05/25 14:02:47 tsutsui Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -311,6 +311,7 @@ zs_ap_attach(parent, self, aux)
if (!didintr) {
didintr = 1;
zsc->zsc_si = softintr_establish(IPL_SOFTSERIAL, zssoft, zsc);
apbus_intr_establish(1, /* interrupt level ( 0 or 1 ) */
NEWS5000_INT1_SCC,
0, /* priority */

4
sys/arch/newsmips/conf/files.newsmips
View File

@ -1,4 +1,4 @@
# $NetBSD: files.newsmips,v 1.21 2002/10/26 13:50:38 jdolecek Exp $
# $NetBSD: files.newsmips,v 1.22 2003/05/25 14:02:48 tsutsui Exp $
# NEWSMIPS-specific configuration info
@ -98,6 +98,8 @@ file arch/newsmips/newsmips/cpu_cons.c
file dev/clock_subr.c
file dev/cons.c
file arch/mips/mips/softintr.c
#
# Machine-independent SCSI driver.
#

31
sys/arch/newsmips/dev/zs.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.17 2003/04/26 18:43:20 tsutsui Exp $ */
/* $NetBSD: zs.c,v 1.18 2003/05/25 14:02:48 tsutsui Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -84,8 +84,6 @@ zs_print(aux, name)
return UNCONF;
}
static volatile int zssoftpending;
/*
* Our ZS chips all share a common, autovectored interrupt,
* so we have to look at all of them on each interrupt.
@ -97,20 +95,16 @@ zshard(arg)
struct zsc_softc *zsc;
int unit, rval, softreq;
rval = softreq = 0;
rval = 0;
for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
zsc = zsc_cd.cd_devs[unit];
if (zsc == NULL)
continue;
rval |= zsc_intr_hard(zsc);
softreq |= zsc->zsc_cs[0]->cs_softreq;
softreq = zsc->zsc_cs[0]->cs_softreq;
softreq |= zsc->zsc_cs[1]->cs_softreq;
}
/* We are at splzs here, so no need to lock. */
if (softreq && (zssoftpending == 0)) {
zssoftpending = 1;
setsoftserial();
if (softreq)
softintr_schedule(zsc->zsc_si);
}
return rval;
@ -126,19 +120,6 @@ zssoft(arg)
struct zsc_softc *zsc;
int s, unit;
/* This is not the only ISR on this IPL. */
if (zssoftpending == 0)
return;
/*
* The soft intr. bit will be set by zshard only if
* the variable zssoftpending is zero. The order of
* these next two statements prevents our clearing
* the soft intr bit just after zshard has set it.
*/
/* clearsoftnet(); */
zssoftpending = 0;
/* Make sure we call the tty layer at spltty. */
s = spltty();
for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
@ -214,7 +195,7 @@ zs_set_modes(cs, cflag)
* Therefore, NEVER set the HFC bit, and instead use the
* status interrupt to detect CTS changes.
*/
s = splzs();
s = splserial();
cs->cs_rr0_pps = 0;
if ((cflag & (CLOCAL | MDMBUF)) != 0) {
cs->cs_rr0_dcd = 0;

3
sys/arch/newsmips/dev/zs_hb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: zs_hb.c,v 1.15 2003/05/10 09:46:25 tsutsui Exp $ */
/* $NetBSD: zs_hb.c,v 1.16 2003/05/25 14:02:48 tsutsui Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -296,6 +296,7 @@ zs_hb_attach(parent, self, aux)
if (!didintr) {
didintr = 1;
zsc->zsc_si = softintr_establish(IPL_SOFTSERIAL, zssoft, zsc);
hb_intr_establish(intlevel, INTST1_SCC, IPL_SERIAL,
zshard_hb, NULL);
}

184
sys/arch/newsmips/include/intr.h
View File

@ -1,7 +1,11 @@
/* $NetBSD: intr.h,v 1.12 2003/05/10 09:46:25 tsutsui Exp $ */
/* $NetBSD: intr.h,v 1.13 2003/05/25 14:02:48 tsutsui Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -13,39 +17,65 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Jonathan Stone for
* the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
#define IPL_NONE 0 /* disable only this interrupt */
#define IPL_BIO 1 /* disable block I/O interrupts */
#define IPL_NET 2 /* disable network interrupts */
#define IPL_TTY 3 /* disable terminal interrupts */
#define IPL_CLOCK 4 /* disable clock interrupts */
#define IPL_STATCLOCK 5 /* disable profiling interrupts */
#define IPL_SERIAL 6 /* disable serial hardware interrupts */
#define IPL_HIGH 7 /* disable all interrupts */
#define IPL_SOFT 1 /* generic software interrupts (SI 0) */
#define IPL_SOFTCLOCK 2 /* clock software interrupts (SI 0) */
#define IPL_SOFTNET 3 /* network software interrupts (SI 1) */
#define IPL_SOFTSERIAL 4 /* serial software interrupts (SI 1) */
#define IPL_BIO 5 /* disable block I/O interrupts */
#define IPL_NET 6 /* disable network interrupts */
#define IPL_TTY 7 /* disable terminal interrupts */
#define IPL_SERIAL 7 /* disable serial hardware interrupts */
#define IPL_CLOCK 8 /* disable clock interrupts */
#define IPL_STATCLOCK 8 /* disable profiling interrupts */
#define IPL_HIGH 8 /* disable all interrupts */
#define _IPL_NSOFT 4
#define _IPL_N 9
#define _IPL_SI0_FIRST IPL_SOFT
#define _IPL_SI0_LAST IPL_SOFTCLOCK
#define _IPL_SI1_FIRST IPL_SOFTNET
#define _IPL_SI1_LAST IPL_SOFTSERIAL
#define IPL_SOFTNAMES { \
"misc", \
"clock", \
"net", \
"serial", \
}
#ifdef _KERNEL
#ifndef _LOCORE
#include <sys/device.h>
#include <mips/cpuregs.h>
extern const u_int32_t ipl_sr_bits[_IPL_N];
extern int _splraise __P((int));
extern int _spllower __P((int));
@ -55,53 +85,26 @@ extern void _splnone __P((void));
extern void _setsoftintr __P((int));
extern void _clrsoftintr __P((int));
/*
* software simulated interrupt
*/
#define SIR_NET 0x01
#define SIR_SERIAL 0x02
#define setsoft(x) do { \
extern u_int ssir; \
int s; \
\
s = splhigh(); \
ssir |= (x); \
_setsoftintr(MIPS_SOFT_INT_MASK_1); \
splx(s); \
} while (0)
#define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0)
#define setsoftnet() setsoft(SIR_NET)
#define setsoftserial() setsoft(SIR_SERIAL)
/*
* nesting interrupt masks.
*/
#define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0
#define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
#define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
#define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
#define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
#define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
#define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
#define splhigh() _splraise(ipl_sr_bits[IPL_HIGH])
#define spl0() (void)_spllower(0)
#define splx(s) (void)_splset(s)
#define splbio() _splraise(MIPS_INT_MASK_SPL0)
#define splnet() _splraise(MIPS_INT_MASK_SPL1)
#define spltty() _splraise(MIPS_INT_MASK_SPL1)
#define splvm() _splraise(MIPS_INT_MASK_SPL1)
#define splclock() _splraise(MIPS_INT_MASK_SPL2)
#define splstatclock() _splraise(MIPS_INT_MASK_SPL2)
#define splhigh() _splraise(MIPS_INT_MASK_SPL2)
#define splsched() splhigh()
#define spllock() splhigh()
#define splbio() _splraise(ipl_sr_bits[IPL_BIO])
#define splnet() _splraise(ipl_sr_bits[IPL_NET])
#define spltty() _splraise(ipl_sr_bits[IPL_TTY])
#define splserial() _splraise(ipl_sr_bits[IPL_SERIAL])
#define splvm() spltty()
#define splclock() _splraise(ipl_sr_bits[IPL_CLOCK])
#define splstatclock() splclock()
#define splsoftclock() _splraise(MIPS_INT_MASK_SPL_SOFT0)
#define splsoftnet() _splraise(MIPS_INT_MASK_SPL_SOFT1)
#define spllowersoftclock() _spllower(MIPS_INT_MASK_SPL_SOFT0)
#define splsched() splclock()
#define spllock() splhigh()
#define splsoft() _splraise(ipl_sr_bits[IPL_SOFT])
#define splsoftclock() _splraise(ipl_sr_bits[IPL_SOFTCLOCK])
#define splsoftnet() _splraise(ipl_sr_bits[IPL_SOFTNET])
#define splsoftserial() _splraise(ipl_sr_bits[IPL_SOFTSERIAL])
#define spllowersoftclock() _spllower(ipl_sr_bits[IPL_SOFTCLOCK])
struct newsmips_intrhand {
LIST_ENTRY(newsmips_intrhand) ih_q;
@ -117,33 +120,38 @@ struct newsmips_intr {
LIST_HEAD(,newsmips_intrhand) intr_q;
};
#include <mips/softintr.h>
/*
* Index into intrcnt[], which is defined in locore
*/
#define SOFTCLOCK_INTR 0
#define SOFTNET_INTR 1
#define SERIAL0_INTR 2
#define SERIAL1_INTR 3
#define SERIAL2_INTR 4
#define LANCE_INTR 5
#define SCSI_INTR 6
#define ERROR_INTR 7
#define HARDCLOCK_INTR 8
#define FPU_INTR 9
#define SLOT1_INTR 10
#define SLOT2_INTR 11
#define SLOT3_INTR 12
#define FLOPPY_INTR 13
#define STRAY_INTR 14
#define SERIAL0_INTR 0
#define SERIAL1_INTR 1
#define SERIAL2_INTR 2
#define LANCE_INTR 3
#define SCSI_INTR 4
#define ERROR_INTR 5
#define HARDCLOCK_INTR 6
#define FPU_INTR 7
#define SLOT1_INTR 8
#define SLOT2_INTR 9
#define SLOT3_INTR 10
#define FLOPPY_INTR 11
#define STRAY_INTR 12
extern u_int intrcnt[];
/* handle i/o device interrupts */
extern void news3400_intr __P((u_int, u_int, u_int, u_int));
extern void news5000_intr __P((u_int, u_int, u_int, u_int));
#ifdef news3400
void news3400_intr __P((u_int, u_int, u_int, u_int));
#endif
#ifdef news5000
void news5000_intr __P((u_int, u_int, u_int, u_int));
#endif
void (*hardware_intr) __P((u_int, u_int, u_int, u_int));
extern void (*enable_intr) __P((void));
extern void (*disable_intr) __P((void));
void (*enable_intr) __P((void));
void (*disable_intr) __P((void));
#endif /* !_LOCORE */
#endif /* _KERNEL */

3
sys/arch/newsmips/include/types.h
View File

@ -1,8 +1,9 @@
/* $NetBSD: types.h,v 1.5 2002/08/05 02:13:15 simonb Exp $ */
/* $NetBSD: types.h,v 1.6 2003/05/25 14:02:48 tsutsui Exp $ */
#include <mips/types.h>
#define __BROKEN_CONFIG_UNIT_USAGE
#define __HAVE_GENERIC_SOFT_INTERRUPTS
/* MIPS specific options */
#define __HAVE_BOOTINFO_H

7
sys/arch/newsmips/include/z8530var.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: z8530var.h,v 1.4 2003/04/26 18:43:20 tsutsui Exp $ */
/* $NetBSD: z8530var.h,v 1.5 2003/05/25 14:02:48 tsutsui Exp $ */
/*
* Copyright (c) 1994 Gordon W. Ross
@ -52,6 +52,7 @@ struct zsc_softc {
struct zs_chanstate *zsc_cs[2]; /* channel A and B soft state */
/* Machine-dependent part follows... */
struct zs_chanstate zsc_cs_store[2];
void *zsc_si; /* softinterrupt handle */
};
/*
@ -76,6 +77,4 @@ void zssoft __P((void*));
int zs_get_speed __P((struct zs_chanstate *));
void (*zs_delay) __P((void));
/* Zilog Serial hardware interrupts (level 1) */
#define splzs cpu_spl1
extern int splzs(void);
#define splzs() splserial()

3
sys/arch/newsmips/newsmips/autoconf.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: autoconf.c,v 1.16 2002/09/25 22:21:15 thorpej Exp $ */
/* $NetBSD: autoconf.c,v 1.17 2003/05/25 14:02:49 tsutsui Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -98,6 +98,7 @@ cpu_configure()
/*
* Kick off autoconfiguration
*/
softintr_init();
_splnone(); /* enable all interrupts */
splhigh(); /* ...then disable device interrupts */

6
sys/arch/newsmips/newsmips/locore_machdep.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_machdep.S,v 1.9 2003/04/26 18:40:00 tsutsui Exp $ */
/* $NetBSD: locore_machdep.S,v 1.10 2003/05/25 14:02:49 tsutsui Exp $ */
/*
* Copyright (c) 1992, 1993
@ -226,8 +226,6 @@ outofworld:
.globl _C_LABEL(intrnames)
.globl _C_LABEL(eintrnames)
_C_LABEL(intrnames):
.asciiz "softclock"
.asciiz "softnet"
.asciiz "serial0"
.asciiz "serial1"
.asciiz "serial2"
@ -246,7 +244,7 @@ _C_LABEL(intrnames):
_C_LABEL(eintrnames):
.align 2
_C_LABEL(intrcnt):
.word 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0
.word 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0
_C_LABEL(eintrcnt):
.word 0 # This shouldn't be needed but with 4.4bsd's as, the eintrcnt
# label ends end up in a different section otherwise.

94
sys/arch/newsmips/newsmips/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.69 2003/04/26 18:50:19 tsutsui Exp $ */
/* $NetBSD: machdep.c,v 1.70 2003/05/25 14:02:49 tsutsui Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -43,7 +43,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.69 2003/04/26 18:50:19 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.70 2003/05/25 14:02:49 tsutsui Exp $");
/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
@ -78,6 +78,7 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.69 2003/04/26 18:50:19 tsutsui Exp $")
#include <ufs/mfs/mfs_extern.h> /* mfs_initminiroot() */
#include <machine/cpu.h>
#include <machine/intr.h>
#include <machine/reg.h>
#include <machine/psl.h>
#include <machine/pte.h>
@ -129,13 +130,8 @@ phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
int mem_cluster_cnt;
struct idrom idrom;
void (*enable_intr) __P((void));
void (*disable_intr) __P((void));
void (*readmicrotime) __P((struct timeval *tvp));
static void (*hardware_intr) __P((u_int, u_int, u_int, u_int));
u_int ssir;
/*
* Local functions.
*/
@ -159,6 +155,51 @@ extern void stacktrace __P((void)); /*XXX*/
*/
int safepri = MIPS3_PSL_LOWIPL; /* XXX */
/*
* This is a mask of bits to clear in the SR when we go to a
* given interrupt priority level.
*/
const u_int32_t ipl_sr_bits[_IPL_N] = {
0, /* IPL_NONE */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1|
MIPS_INT_MASK_0, /* IPL_BIO */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1|
MIPS_INT_MASK_0|
MIPS_INT_MASK_1, /* IPL_NET */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1|
MIPS_INT_MASK_0|
MIPS_INT_MASK_1, /* IPL_{TTY,SERIAL} */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1|
MIPS_INT_MASK_0|
MIPS_INT_MASK_1|
MIPS_INT_MASK_2, /* IPL_{CLOCK,HIGH} */
};
const u_int32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
};
extern struct user *proc0paddr;
extern u_long bootdev;
extern char edata[], end[];
@ -651,10 +692,6 @@ delay(n)
DELAY(n);
}
#include "zsc.h"
int zssoft __P((void));
void
cpu_intr(status, cause, pc, ipending)
u_int32_t status;
@ -662,39 +699,18 @@ cpu_intr(status, cause, pc, ipending)
u_int32_t pc;
u_int32_t ipending;
{
uvmexp.intrs++;
/* device interrupts */
(*hardware_intr)(status, cause, pc, ipending);
/* software simulated interrupt */
if ((ipending & MIPS_SOFT_INT_MASK_1) ||
(ssir && (status & MIPS_SOFT_INT_MASK_1))) {
/* software interrupts */
ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0);
if (ipending == 0)
return;
#define DO_SIR(bit, fn) \
do { \
if (n & (bit)) { \
uvmexp.softs++; \
fn; \
} \
} while (0)
_clrsoftintr(ipending);
unsigned n;
n = ssir; ssir = 0;
_clrsoftintr(MIPS_SOFT_INT_MASK_1);
#if NZSC > 0
DO_SIR(SIR_SERIAL, zssoft());
#endif
DO_SIR(SIR_NET, netintr());
#undef DO_SIR
}
/* 'softclock' interrupt */
if (ipending & MIPS_SOFT_INT_MASK_0) {
_clrsoftintr(MIPS_SOFT_INT_MASK_0);
uvmexp.softs++;
intrcnt[SOFTCLOCK_INTR]++;
softclock(NULL);
}
softintr_dispatch(ipending);
}