From c8c2e04113b3a70c156491d5f3504d5b0493bffe Mon Sep 17 00:00:00 2001 From: paulus Date: Thu, 25 Nov 1993 01:25:55 +0000 Subject: [PATCH] Machine-dependent files with shared-library support for the m68k architecture. This directory should be able to used for all m68k-based machines. --- gnu/usr.bin/gcc2/arch/m68k/Makefile | 3 + gnu/usr.bin/gcc2/arch/m68k/aux-output.c | 2248 ++++++ gnu/usr.bin/gcc2/arch/m68k/config.h | 50 + gnu/usr.bin/gcc2/arch/m68k/ctype.h | 66 + gnu/usr.bin/gcc2/arch/m68k/insn-attr.h | 19 + gnu/usr.bin/gcc2/arch/m68k/insn-attrtab.c | 14 + gnu/usr.bin/gcc2/arch/m68k/insn-codes.h | 184 + gnu/usr.bin/gcc2/arch/m68k/insn-config.h | 12 + gnu/usr.bin/gcc2/arch/m68k/insn-emit.c | 1897 +++++ gnu/usr.bin/gcc2/arch/m68k/insn-extract.c | 558 ++ gnu/usr.bin/gcc2/arch/m68k/insn-flags.h | 537 ++ gnu/usr.bin/gcc2/arch/m68k/insn-opinit.c | 221 + gnu/usr.bin/gcc2/arch/m68k/insn-output.c | 7826 +++++++++++++++++++++ gnu/usr.bin/gcc2/arch/m68k/insn-peep.c | 410 ++ gnu/usr.bin/gcc2/arch/m68k/insn-recog.c | 6589 +++++++++++++++++ gnu/usr.bin/gcc2/arch/m68k/m68k.h | 1796 +++++ gnu/usr.bin/gcc2/arch/m68k/md | 5628 +++++++++++++++ gnu/usr.bin/gcc2/arch/m68k/tconfig.h | 50 + gnu/usr.bin/gcc2/arch/m68k/tm.h | 94 + 19 files changed, 28202 insertions(+) create mode 100644 gnu/usr.bin/gcc2/arch/m68k/Makefile create mode 100644 gnu/usr.bin/gcc2/arch/m68k/aux-output.c create mode 100644 gnu/usr.bin/gcc2/arch/m68k/config.h create mode 100644 gnu/usr.bin/gcc2/arch/m68k/ctype.h create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-attr.h create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-attrtab.c create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-codes.h create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-config.h create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-emit.c create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-extract.c create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-flags.h create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-opinit.c create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-output.c create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-peep.c create mode 100644 gnu/usr.bin/gcc2/arch/m68k/insn-recog.c create mode 100644 gnu/usr.bin/gcc2/arch/m68k/m68k.h create mode 100644 gnu/usr.bin/gcc2/arch/m68k/md create mode 100644 gnu/usr.bin/gcc2/arch/m68k/tconfig.h create mode 100644 gnu/usr.bin/gcc2/arch/m68k/tm.h diff --git a/gnu/usr.bin/gcc2/arch/m68k/Makefile b/gnu/usr.bin/gcc2/arch/m68k/Makefile new file mode 100644 index 000000000000..87648d6dd50a --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/Makefile @@ -0,0 +1,3 @@ +# $Id: Makefile,v 1.1 1993/11/25 01:25:55 paulus Exp $ + +.include diff --git a/gnu/usr.bin/gcc2/arch/m68k/aux-output.c b/gnu/usr.bin/gcc2/arch/m68k/aux-output.c new file mode 100644 index 000000000000..7b724d08116b --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/aux-output.c @@ -0,0 +1,2248 @@ +/* Subroutines for insn-output.c for Motorola 68000 family. + Copyright (C) 1987, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef lint +static char rcsid[] = "$Id: aux-output.c,v 1.1 1993/11/25 01:25:57 paulus Exp $"; +#endif /* not lint */ + +/* Some output-actions in m68k.md need these. */ +#include +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "output.h" +#include "insn-attr.h" + +/* Needed for use_return_insn. */ +#include "flags.h" + +#ifdef SUPPORT_SUN_FPA + +/* Index into this array by (register number >> 3) to find the + smallest class which contains that register. */ +enum reg_class regno_reg_class[] + = { DATA_REGS, ADDR_REGS, FP_REGS, + LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS }; + +#endif /* defined SUPPORT_SUN_FPA */ + +/* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END, + if SGS_SWITCH_TABLE. */ +int switch_table_difference_label_flag; + +static rtx find_addr_reg (); +rtx legitimize_pic_address (); + + +/* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the + function at any time during the compilation process. In the future + we should try and eliminate the USE if we can easily determine that + all PIC references were deleted from the current function. That would + save an address register */ + +finalize_pic () +{ + if (flag_pic && current_function_uses_pic_offset_table) + emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx)); +} + + +/* This function generates the assembly code for function entry. + STREAM is a stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. + Refer to the array `regs_ever_live' to determine which registers + to save; `regs_ever_live[I]' is nonzero if register number I + is ever used in the function. This function is responsible for + knowing which registers should not be saved even if used. */ + + +/* Note that the order of the bit mask for fmovem is the opposite + of the order for movem! */ + + +void +output_function_prologue (stream, size) + FILE *stream; + int size; +{ + register int regno; + register int mask = 0; + int num_saved_regs = 0; + extern char call_used_regs[]; + int fsize = (size + 3) & -4; + + + if (frame_pointer_needed) + { + /* Adding negative number is faster on the 68040. */ + if (fsize < 0x8000 && !TARGET_68040) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tlink.w %s,%0I%d\n", + reg_names[FRAME_POINTER_REGNUM], -fsize); +#else + asm_fprintf (stream, "\tlink %s,%0I%d\n", + reg_names[FRAME_POINTER_REGNUM], -fsize); +#endif + } + else if (TARGET_68020) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tlink.l %s,%0I%d\n", + reg_names[FRAME_POINTER_REGNUM], -fsize); +#else + asm_fprintf (stream, "\tlink %s,%0I%d\n", + reg_names[FRAME_POINTER_REGNUM], -fsize); +#endif + } + else + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n", + reg_names[FRAME_POINTER_REGNUM], -fsize); +#else + asm_fprintf (stream, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n", + reg_names[FRAME_POINTER_REGNUM], -fsize); +#endif + } + } + else if (fsize) + { + /* Adding negative number is faster on the 68040. */ + if (fsize + 4 < 0x8000) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", - (fsize + 4)); +#else + asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", - (fsize + 4)); +#endif + } + else + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", - (fsize + 4)); +#else + asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", - (fsize + 4)); +#endif + } + } +#ifdef SUPPORT_SUN_FPA + for (regno = 24; regno < 56; regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tfpmovd %s,-(%Rsp)\n", + reg_names[regno]); +#else + asm_fprintf (stream, "\tfpmoved %s,%Rsp@-\n", + reg_names[regno]); +#endif + } +#endif + for (regno = 16; regno < 24; regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + mask |= 1 << (regno - 16); + if ((mask & 0xff) != 0) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tfmovm %0I0x%x,-(%Rsp)\n", mask & 0xff); +#else + asm_fprintf (stream, "\tfmovem %0I0x%x,%Rsp@-\n", mask & 0xff); +#endif + } + mask = 0; + for (regno = 0; regno < 16; regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + { + mask |= 1 << (15 - regno); + num_saved_regs++; + } + if (frame_pointer_needed) + { + mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM)); + num_saved_regs--; + } + +#if NEED_PROBE + fprintf (stream, "\ttstl sp@(%d)\n", NEED_PROBE - num_saved_regs * 4); +#endif + + if (num_saved_regs <= 2) + { + /* Store each separately in the same order moveml uses. + Using two movel instructions instead of a single moveml + is about 15% faster for the 68020 and 68030 at no expense + in code size */ + + int i; + + /* Undo the work from above. */ + for (i = 0; i< 16; i++) + if (mask & (1 << i)) + asm_fprintf (stream, +#ifdef MOTOROLA + "\t%Omove.l %s,-(%Rsp)\n", +#else + "\tmovel %s,%Rsp@-\n", +#endif + reg_names[15 - i]); + } + else if (mask) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask); +#else + asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@-\n", mask); +#endif + } + if (flag_pic && current_function_uses_pic_offset_table) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n", + reg_names[PIC_OFFSET_TABLE_REGNUM]); +#else + asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n", + reg_names[PIC_OFFSET_TABLE_REGNUM]); + asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n", + reg_names[PIC_OFFSET_TABLE_REGNUM], + reg_names[PIC_OFFSET_TABLE_REGNUM]); +#endif + } +} + +/* Return true if this function's epilogue can be output as RTL. */ + +int +use_return_insn () +{ + int regno; + + if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) + return 0; + + /* Copied from output_function_epilogue (). We should probably create a + separate layout routine to perform the common work. */ + + for (regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + return 0; + + return 1; +} + +/* This function generates the assembly code for function exit, + on machines that need it. Args are same as for FUNCTION_PROLOGUE. + + The function epilogue should not depend on the current stack pointer! + It should use the frame pointer only, if there is a frame pointer. + This is mandatory because of alloca; we also take advantage of it to + omit stack adjustments before returning. */ + +void +output_function_epilogue (stream, size) + FILE *stream; + int size; +{ + register int regno; + register int mask, fmask; + register int nregs; + int offset, foffset, fpoffset; + extern char call_used_regs[]; + int fsize = (size + 3) & -4; + int big = 0; + rtx insn = get_last_insn (); + + /* If the last insn was a BARRIER, we don't have to write any code. */ + if (GET_CODE (insn) == NOTE) + insn = prev_nonnote_insn (insn); + if (insn && GET_CODE (insn) == BARRIER) + { + /* Output just a no-op so that debuggers don't get confused + about which function the pc is in at this address. */ + asm_fprintf (stream, "\tnop\n"); + return; + } + +#ifdef FUNCTION_EXTRA_EPILOGUE + FUNCTION_EXTRA_EPILOGUE (stream, size); +#endif + nregs = 0; fmask = 0; fpoffset = 0; +#ifdef SUPPORT_SUN_FPA + for (regno = 24 ; regno < 56 ; regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + nregs++; + fpoffset = nregs * 8; +#endif + nregs = 0; + for (regno = 16; regno < 24; regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + { + nregs++; + fmask |= 1 << (23 - regno); + } + foffset = fpoffset + nregs * 12; + nregs = 0; mask = 0; + if (frame_pointer_needed) + regs_ever_live[FRAME_POINTER_REGNUM] = 0; + for (regno = 0; regno < 16; regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + { + nregs++; + mask |= 1 << regno; + } + offset = foffset + nregs * 4; + if (offset + fsize >= 0x8000 + && frame_pointer_needed + && (mask || fmask || fpoffset)) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra0\n", -fsize); +#else + asm_fprintf (stream, "\tmovel %0I%d,%Ra0\n", -fsize); +#endif + fsize = 0, big = 1; + } + if (nregs <= 2) + { + /* Restore each separately in the same order moveml does. + Using two movel instructions instead of a single moveml + is about 15% faster for the 68020 and 68030 at no expense + in code size. */ + + int i; + + /* Undo the work from above. */ + for (i = 0; i< 16; i++) + if (mask & (1 << i)) + { + if (big) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\t%Omove.l -%d(%s,%Ra0.l),%s\n", + offset + fsize, + reg_names[FRAME_POINTER_REGNUM], + reg_names[i]); +#else + asm_fprintf (stream, "\tmovel %s@(-%d,%Ra0:l),%s\n", + reg_names[FRAME_POINTER_REGNUM], + offset + fsize, reg_names[i]); +#endif + } + else if (! frame_pointer_needed) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\t%Omove.l (%Rsp)+,%s\n", + reg_names[i]); +#else + asm_fprintf (stream, "\tmovel %Rsp@+,%s\n", + reg_names[i]); +#endif + } + else + { +#ifdef MOTOROLA + asm_fprintf (stream, "\t%Omove.l -%d(%s),%s\n", + offset + fsize, + reg_names[FRAME_POINTER_REGNUM], + reg_names[i]); +#else + asm_fprintf (stream, "\tmovel %s@(-%d),%s\n", + reg_names[FRAME_POINTER_REGNUM], + offset + fsize, reg_names[i]); +#endif + } + offset = offset - 4; + } + } + else if (mask) + { + if (big) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra0.l),%0I0x%x\n", + offset + fsize, + reg_names[FRAME_POINTER_REGNUM], + mask); +#else + asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra0:l),%0I0x%x\n", + reg_names[FRAME_POINTER_REGNUM], + offset + fsize, mask); +#endif + } + else if (! frame_pointer_needed) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask); +#else + asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask); +#endif + } + else + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n", + offset + fsize, + reg_names[FRAME_POINTER_REGNUM], + mask); +#else + asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n", + reg_names[FRAME_POINTER_REGNUM], + offset + fsize, mask); +#endif + } + } + if (fmask) + { + if (big) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tfmovm -%d(%s,%Ra0.l),%0I0x%x\n", + foffset + fsize, + reg_names[FRAME_POINTER_REGNUM], + fmask); +#else + asm_fprintf (stream, "\tfmovem %s@(-%d,%Ra0:l),%0I0x%x\n", + reg_names[FRAME_POINTER_REGNUM], + foffset + fsize, fmask); +#endif + } + else if (! frame_pointer_needed) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask); +#else + asm_fprintf (stream, "\tfmovem %Rsp@+,%0I0x%x\n", fmask); +#endif + } + else + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tfmovm -%d(%s),%0I0x%x\n", + foffset + fsize, + reg_names[FRAME_POINTER_REGNUM], + fmask); +#else + asm_fprintf (stream, "\tfmovem %s@(-%d),%0I0x%x\n", + reg_names[FRAME_POINTER_REGNUM], + foffset + fsize, fmask); +#endif + } + } + if (fpoffset != 0) + for (regno = 55; regno >= 24; regno--) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + { + if (big) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tfpmovd -%d(%s,%Ra0.l), %s\n", + fpoffset + fsize, + reg_names[FRAME_POINTER_REGNUM], + reg_names[regno]); +#else + asm_fprintf (stream, "\tfpmoved %s@(-%d,%Ra0:l), %s\n", + reg_names[FRAME_POINTER_REGNUM], + fpoffset + fsize, reg_names[regno]); +#endif + } + else if (! frame_pointer_needed) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tfpmovd (%Rsp)+,%s\n", + reg_names[regno]); +#else + asm_fprintf (stream, "\tfpmoved %Rsp@+, %s\n", + reg_names[regno]); +#endif + } + else + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tfpmovd -%d(%s), %s\n", + fpoffset + fsize, + reg_names[FRAME_POINTER_REGNUM], + reg_names[regno]); +#else + asm_fprintf (stream, "\tfpmoved %s@(-%d), %s\n", + reg_names[FRAME_POINTER_REGNUM], + fpoffset + fsize, reg_names[regno]); +#endif + } + fpoffset -= 8; + } + if (frame_pointer_needed) + fprintf (stream, "\tunlk %s\n", + reg_names[FRAME_POINTER_REGNUM]); + else if (fsize) + { + if (fsize + 4 < 0x8000) + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", fsize + 4); +#else + asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", fsize + 4); +#endif + } + else + { +#ifdef MOTOROLA + asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", fsize + 4); +#else + asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", fsize + 4); +#endif + } + } + if (current_function_pops_args) + asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args); + else + fprintf (stream, "\trts\n"); +} + +/* Similar to general_operand, but exclude stack_pointer_rtx. */ + +int +not_sp_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + return op != stack_pointer_rtx && general_operand (op, mode); +} + +/* Return TRUE if X is a valid comparison operator for the dbcc + instruction. + + Note it rejects floating point comparison operators. + (In the future we could use Fdbcc). + + It also rejects some comparisons when CC_NO_OVERFLOW is set. */ + +int +valid_dbcc_comparison_p (x, mode) + rtx x; + enum machine_mode mode; +{ + /* We could add support for these in the future */ + if (cc_prev_status.flags & CC_IN_68881) + return 0; + + switch (GET_CODE (x)) + { + + case EQ: case NE: case GTU: case LTU: + case GEU: case LEU: + return 1; + + /* Reject some when CC_NO_OVERFLOW is set. This may be over + conservative */ + case GT: case LT: case GE: case LE: + return ! (cc_prev_status.flags & CC_NO_OVERFLOW); + default: + return 0; + } +} + +/* Output a dbCC; jCC sequence. Note we do not handle the + floating point version of this sequence (Fdbcc). We also + do not handle alternative conditions when CC_NO_OVERFLOW is + set. It is assumed that valid_dbcc_comparison_p will kick + those out before we get here. */ + +output_dbcc_and_branch (operands) + rtx *operands; +{ + + switch (GET_CODE (operands[3])) + { + case EQ: +#ifdef MOTOROLA + output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands); +#else + output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands); +#endif + break; + + case NE: +#ifdef MOTOROLA + output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands); +#else + output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands); +#endif + break; + + case GT: +#ifdef MOTOROLA + output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands); +#else + output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands); +#endif + break; + + case GTU: +#ifdef MOTOROLA + output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands); +#else + output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands); +#endif + break; + + case LT: +#ifdef MOTOROLA + output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands); +#else + output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands); +#endif + break; + + case LTU: +#ifdef MOTOROLA + output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands); +#else + output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands); +#endif + break; + + case GE: +#ifdef MOTOROLA + output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands); +#else + output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands); +#endif + break; + + case GEU: +#ifdef MOTOROLA + output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands); +#else + output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands); +#endif + break; + + case LE: +#ifdef MOTOROLA + output_asm_insn ("dble %0,%l1\n\tjble %l2", operands); +#else + output_asm_insn ("dble %0,%l1\n\tjle %l2", operands); +#endif + break; + + case LEU: +#ifdef MOTOROLA + output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands); +#else + output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands); +#endif + break; + + default: + abort (); + } + + /* If the decrement is to be done in SImode, then we have + to compensate for the fact that dbcc decrements in HImode. */ + switch (GET_MODE (operands[0])) + { + case SImode: +#ifdef MOTOROLA + output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands); +#else + output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands); +#endif + break; + + case HImode: + break; + + default: + abort (); + } +} + +char * +output_btst (operands, countop, dataop, insn, signpos) + rtx *operands; + rtx countop, dataop; + rtx insn; + int signpos; +{ + operands[0] = countop; + operands[1] = dataop; + + if (GET_CODE (countop) == CONST_INT) + { + register int count = INTVAL (countop); + /* If COUNT is bigger than size of storage unit in use, + advance to the containing unit of same size. */ + if (count > signpos) + { + int offset = (count & ~signpos) / 8; + count = count & signpos; + operands[1] = dataop = adj_offsettable_operand (dataop, offset); + } + if (count == signpos) + cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; + else + cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; + + /* These three statements used to use next_insns_test_no... + but it appears that this should do the same job. */ + if (count == 31 + && next_insn_tests_no_inequality (insn)) + return "tst%.l %1"; + if (count == 15 + && next_insn_tests_no_inequality (insn)) + return "tst%.w %1"; + if (count == 7 + && next_insn_tests_no_inequality (insn)) + return "tst%.b %1"; + + cc_status.flags = CC_NOT_NEGATIVE; + } + return "btst %0,%1"; +} + +/* Returns 1 if OP is either a symbol reference or a sum of a symbol + reference and a constant. */ + +int +symbolic_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + switch (GET_CODE (op)) + { + case SYMBOL_REF: + case LABEL_REF: + return 1; + + case CONST: + op = XEXP (op, 0); + return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF + || GET_CODE (XEXP (op, 0)) == LABEL_REF) + && GET_CODE (XEXP (op, 1)) == CONST_INT); + +#if 0 /* Deleted, with corresponding change in m68k.h, + so as to fit the specs. No CONST_DOUBLE is ever symbolic. */ + case CONST_DOUBLE: + return GET_MODE (op) == mode; +#endif + + default: + return 0; + } +} + + +/* Legitimize PIC addresses. If the address is already + position-independent, we return ORIG. Newly generated + position-independent addresses go to REG. If we need more + than one register, we lose. + + An address is legitimized by making an indirect reference + through the Global Offset Table with the name of the symbol + used as an offset. + + The assembler and linker are responsible for placing the + address of the symbol in the GOT. The function prologue + is responsible for initializing a5 to the starting address + of the GOT. + + The assembler is also responsible for translating a symbol name + into a constant displacement from the start of the GOT. + + A quick example may make things a little clearer: + + When not generating PIC code to store the value 12345 into _foo + we would generate the following code: + + movel #12345, _foo + + When generating PIC two transformations are made. First, the compiler + loads the address of foo into a register. So the first transformation makes: + + lea _foo, a0 + movel #12345, a0@ + + The code in movsi will intercept the lea instruction and call this + routine which will transform the instructions into: + + movel a5@(_foo:w), a0 + movel #12345, a0@ + + + That (in a nutshell) is how *all* symbol and label references are + handled. */ + +rtx +legitimize_pic_address (orig, mode, reg) + rtx orig, reg; + enum machine_mode mode; +{ + rtx pic_ref = orig; + + /* First handle a simple SYMBOL_REF or LABEL_REF */ + if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) + { + if (reg == 0) + abort (); + + pic_ref = gen_rtx (MEM, Pmode, + gen_rtx (PLUS, Pmode, + pic_offset_table_rtx, orig)); + current_function_uses_pic_offset_table = 1; + RTX_UNCHANGING_P (pic_ref) = 1; + emit_move_insn (reg, pic_ref); + return reg; + } + else if (GET_CODE (orig) == CONST) + { + rtx base, offset; + + /* Make sure this is CONST has not already been legitimized */ + if (GET_CODE (XEXP (orig, 0)) == PLUS + && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) + return orig; + + if (reg == 0) + abort (); + + /* legitimize both operands of the PLUS */ + if (GET_CODE (XEXP (orig, 0)) == PLUS) + { + base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); + orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, + base == reg ? 0 : reg); + } + else abort (); + + if (GET_CODE (orig) == CONST_INT) + return plus_constant_for_output (base, INTVAL (orig)); + pic_ref = gen_rtx (PLUS, Pmode, base, orig); + /* Likewise, should we set special REG_NOTEs here? */ + } + return pic_ref; +} + + +/* Return the best assembler insn template + for moving operands[1] into operands[0] as a fullword. */ + +static char * +singlemove_string (operands) + rtx *operands; +{ +#ifdef SUPPORT_SUN_FPA + if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1])) + return "fpmoves %1,%0"; +#endif + if (DATA_REG_P (operands[0]) + && GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) < 128 + && INTVAL (operands[1]) >= -128) + { +#if defined (MOTOROLA) && !defined (CRDS) + return "moveq%.l %1,%0"; +#else + return "moveq %1,%0"; +#endif + } + if (operands[1] != const0_rtx) + return "move%.l %1,%0"; + if (! ADDRESS_REG_P (operands[0])) + return "clr%.l %0"; + return "sub%.l %0,%0"; +} + + +/* Output assembler code to perform a doubleword move insn + with operands OPERANDS. */ + +char * +output_move_double (operands) + rtx *operands; +{ + enum + { + REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP + } optype0, optype1; + rtx latehalf[2]; + rtx middlehalf[2]; + rtx addreg0 = 0, addreg1 = 0; + int size = GET_MODE_SIZE (GET_MODE (operands[0])); + + middlehalf[0] = 0; + middlehalf[1] = 0; + + /* First classify both operands. */ + + if (REG_P (operands[0])) + optype0 = REGOP; + else if (offsettable_memref_p (operands[0])) + optype0 = OFFSOP; + else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) + optype0 = POPOP; + else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + optype0 = PUSHOP; + else if (GET_CODE (operands[0]) == MEM) + optype0 = MEMOP; + else + optype0 = RNDOP; + + if (REG_P (operands[1])) + optype1 = REGOP; + else if (CONSTANT_P (operands[1])) + optype1 = CNSTOP; + else if (offsettable_memref_p (operands[1])) + optype1 = OFFSOP; + else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) + optype1 = POPOP; + else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) + optype1 = PUSHOP; + else if (GET_CODE (operands[1]) == MEM) + optype1 = MEMOP; + else + optype1 = RNDOP; + + /* Check for the cases that the operand constraints are not + supposed to allow to happen. Abort if we get one, + because generating code for these cases is painful. */ + + if (optype0 == RNDOP || optype1 == RNDOP) + abort (); + + /* If one operand is decrementing and one is incrementing + decrement the former register explicitly + and change that operand into ordinary indexing. */ + + if (optype0 == PUSHOP && optype1 == POPOP) + { + operands[0] = XEXP (XEXP (operands[0], 0), 0); + if (size == 12) + output_asm_insn ("sub%.l %#12,%0", operands); + else + output_asm_insn ("subq%.l %#8,%0", operands); + if (GET_MODE (operands[1]) == XFmode) + operands[0] = gen_rtx (MEM, XFmode, operands[0]); + else if (GET_MODE (operands[0]) == DFmode) + operands[0] = gen_rtx (MEM, DFmode, operands[0]); + else + operands[0] = gen_rtx (MEM, DImode, operands[0]); + optype0 = OFFSOP; + } + if (optype0 == POPOP && optype1 == PUSHOP) + { + operands[1] = XEXP (XEXP (operands[1], 0), 0); + if (size == 12) + output_asm_insn ("sub%.l %#12,%1", operands); + else + output_asm_insn ("subq%.l %#8,%1", operands); + if (GET_MODE (operands[1]) == XFmode) + operands[1] = gen_rtx (MEM, XFmode, operands[1]); + else if (GET_MODE (operands[1]) == DFmode) + operands[1] = gen_rtx (MEM, DFmode, operands[1]); + else + operands[1] = gen_rtx (MEM, DImode, operands[1]); + optype1 = OFFSOP; + } + + /* If an operand is an unoffsettable memory ref, find a register + we can increment temporarily to make it refer to the second word. */ + + if (optype0 == MEMOP) + addreg0 = find_addr_reg (XEXP (operands[0], 0)); + + if (optype1 == MEMOP) + addreg1 = find_addr_reg (XEXP (operands[1], 0)); + + /* Ok, we can do one word at a time. + Normally we do the low-numbered word first, + but if either operand is autodecrementing then we + do the high-numbered word first. + + In either case, set up in LATEHALF the operands to use + for the high-numbered word and in some cases alter the + operands in OPERANDS to be suitable for the low-numbered word. */ + + if (size == 12) + { + if (optype0 == REGOP) + { + latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); + middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + } + else if (optype0 == OFFSOP) + { + middlehalf[0] = adj_offsettable_operand (operands[0], 4); + latehalf[0] = adj_offsettable_operand (operands[0], size - 4); + } + else + { + middlehalf[0] = operands[0]; + latehalf[0] = operands[0]; + } + + if (optype1 == REGOP) + { + latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); + middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + } + else if (optype1 == OFFSOP) + { + middlehalf[1] = adj_offsettable_operand (operands[1], 4); + latehalf[1] = adj_offsettable_operand (operands[1], size - 4); + } + else if (optype1 == CNSTOP) + { + if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + REAL_VALUE_TYPE r; + long l[3]; + + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); + REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); + operands[1] = GEN_INT (l[0]); + middlehalf[1] = GEN_INT (l[1]); + latehalf[1] = GEN_INT (l[2]); + } + else if (CONSTANT_P (operands[1])) + { + /* actually, no non-CONST_DOUBLE constant should ever + appear here. */ + abort (); + if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0) + latehalf[1] = constm1_rtx; + else + latehalf[1] = const0_rtx; + } + } + else + { + middlehalf[1] = operands[1]; + latehalf[1] = operands[1]; + } + } + else + /* size is not 12: */ + { + if (optype0 == REGOP) + latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + else if (optype0 == OFFSOP) + latehalf[0] = adj_offsettable_operand (operands[0], size - 4); + else + latehalf[0] = operands[0]; + + if (optype1 == REGOP) + latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + else if (optype1 == OFFSOP) + latehalf[1] = adj_offsettable_operand (operands[1], size - 4); + else if (optype1 == CNSTOP) + split_double (operands[1], &operands[1], &latehalf[1]); + else + latehalf[1] = operands[1]; + } + + /* If insn is effectively movd N(sp),-(sp) then we will do the + high word first. We should use the adjusted operand 1 (which is N+4(sp)) + for the low word as well, to compensate for the first decrement of sp. */ + if (optype0 == PUSHOP + && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM + && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) + operands[1] = latehalf[1]; + + /* If one or both operands autodecrementing, + do the two words, high-numbered first. */ + + /* Likewise, the first move would clobber the source of the second one, + do them in the other order. This happens only for registers; + such overlap can't happen in memory unless the user explicitly + sets it up, and that is an undefined circumstance. */ + + if (optype0 == PUSHOP || optype1 == PUSHOP + || (optype0 == REGOP && optype1 == REGOP + && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) + || REGNO (operands[0]) == REGNO (latehalf[1])))) + { + /* Make any unoffsettable addresses point at high-numbered word. */ + if (addreg0) + { + if (size == 12) + output_asm_insn ("addql %#8,%0", &addreg0); + else + output_asm_insn ("addql %#4,%0", &addreg0); + } + if (addreg1) + { + if (size == 12) + output_asm_insn ("addql %#8,%0", &addreg1); + else + output_asm_insn ("addql %#4,%0", &addreg1); + } + + /* Do that word. */ + output_asm_insn (singlemove_string (latehalf), latehalf); + + /* Undo the adds we just did. */ + if (addreg0) + output_asm_insn ("subql %#4,%0", &addreg0); + if (addreg1) + output_asm_insn ("subql %#4,%0", &addreg1); + + if (size == 12) + { + output_asm_insn (singlemove_string (middlehalf), middlehalf); + if (addreg0) + output_asm_insn ("subql %#4,%0", &addreg0); + if (addreg1) + output_asm_insn ("subql %#4,%0", &addreg1); + } + + /* Do low-numbered word. */ + return singlemove_string (operands); + } + + /* Normal case: do the two words, low-numbered first. */ + + output_asm_insn (singlemove_string (operands), operands); + + /* Do the middle one of the three words for long double */ + if (size == 12) + { + if (addreg0) + output_asm_insn ("addql %#4,%0", &addreg0); + if (addreg1) + output_asm_insn ("addql %#4,%0", &addreg1); + + output_asm_insn (singlemove_string (middlehalf), middlehalf); + } + + /* Make any unoffsettable addresses point at high-numbered word. */ + if (addreg0) + output_asm_insn ("addql %#4,%0", &addreg0); + if (addreg1) + output_asm_insn ("addql %#4,%0", &addreg1); + + /* Do that word. */ + output_asm_insn (singlemove_string (latehalf), latehalf); + + /* Undo the adds we just did. */ + if (addreg0) + { + if (size == 12) + output_asm_insn ("subql %#8,%0", &addreg0); + else + output_asm_insn ("subql %#4,%0", &addreg0); + } + if (addreg1) + { + if (size == 12) + output_asm_insn ("subql %#8,%0", &addreg1); + else + output_asm_insn ("subql %#4,%0", &addreg1); + } + + return ""; +} + +/* Return a REG that occurs in ADDR with coefficient 1. + ADDR can be effectively incremented by incrementing REG. */ + +static rtx +find_addr_reg (addr) + rtx addr; +{ + while (GET_CODE (addr) == PLUS) + { + if (GET_CODE (XEXP (addr, 0)) == REG) + addr = XEXP (addr, 0); + else if (GET_CODE (XEXP (addr, 1)) == REG) + addr = XEXP (addr, 1); + else if (CONSTANT_P (XEXP (addr, 0))) + addr = XEXP (addr, 1); + else if (CONSTANT_P (XEXP (addr, 1))) + addr = XEXP (addr, 0); + else + abort (); + } + if (GET_CODE (addr) == REG) + return addr; + abort (); +} + +/* Store in cc_status the expressions that the condition codes will + describe after execution of an instruction whose pattern is EXP. + Do not alter them if the instruction would not alter the cc's. */ + +/* On the 68000, all the insns to store in an address register fail to + set the cc's. However, in some cases these instructions can make it + possibly invalid to use the saved cc's. In those cases we clear out + some or all of the saved cc's so they won't be used. */ + +notice_update_cc (exp, insn) + rtx exp; + rtx insn; +{ + /* If the cc is being set from the fpa and the expression is not an + explicit floating point test instruction (which has code to deal with + this), reinit the CC. */ + if (((cc_status.value1 && FPA_REG_P (cc_status.value1)) + || (cc_status.value2 && FPA_REG_P (cc_status.value2))) + && !(GET_CODE (exp) == PARALLEL + && GET_CODE (XVECEXP (exp, 0, 0)) == SET + && XEXP (XVECEXP (exp, 0, 0), 0) == cc0_rtx)) + { + CC_STATUS_INIT; + } + else if (GET_CODE (exp) == SET) + { + if (GET_CODE (SET_SRC (exp)) == CALL) + { + CC_STATUS_INIT; + } + else if (ADDRESS_REG_P (SET_DEST (exp))) + { + if (cc_status.value1 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) + cc_status.value1 = 0; + if (cc_status.value2 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) + cc_status.value2 = 0; + } + else if (!FP_REG_P (SET_DEST (exp)) + && SET_DEST (exp) != cc0_rtx + && (FP_REG_P (SET_SRC (exp)) + || GET_CODE (SET_SRC (exp)) == FIX + || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE + || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND)) + { + CC_STATUS_INIT; + } + /* A pair of move insns doesn't produce a useful overall cc. */ + else if (!FP_REG_P (SET_DEST (exp)) + && !FP_REG_P (SET_SRC (exp)) + && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 + && (GET_CODE (SET_SRC (exp)) == REG + || GET_CODE (SET_SRC (exp)) == MEM + || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) + { + CC_STATUS_INIT; + } + else if (GET_CODE (SET_SRC (exp)) == CALL) + { + CC_STATUS_INIT; + } + else if (XEXP (exp, 0) != pc_rtx) + { + cc_status.flags = 0; + cc_status.value1 = XEXP (exp, 0); + cc_status.value2 = XEXP (exp, 1); + } + } + else if (GET_CODE (exp) == PARALLEL + && GET_CODE (XVECEXP (exp, 0, 0)) == SET) + { + if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0))) + CC_STATUS_INIT; + else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx) + { + cc_status.flags = 0; + cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0); + cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1); + } + } + else + CC_STATUS_INIT; + if (cc_status.value2 != 0 + && ADDRESS_REG_P (cc_status.value2) + && GET_MODE (cc_status.value2) == QImode) + CC_STATUS_INIT; + if (cc_status.value2 != 0 + && !(cc_status.value1 && FPA_REG_P (cc_status.value1))) + switch (GET_CODE (cc_status.value2)) + { + case PLUS: case MINUS: case MULT: + case DIV: case UDIV: case MOD: case UMOD: case NEG: + case ASHIFT: case LSHIFT: case ASHIFTRT: case LSHIFTRT: + case ROTATE: case ROTATERT: + if (GET_MODE (cc_status.value2) != VOIDmode) + cc_status.flags |= CC_NO_OVERFLOW; + break; + case ZERO_EXTEND: + /* (SET r1 (ZERO_EXTEND r2)) on this machine + ends with a move insn moving r2 in r2's mode. + Thus, the cc's are set for r2. + This can set N bit spuriously. */ + cc_status.flags |= CC_NOT_NEGATIVE; + } + if (cc_status.value1 && GET_CODE (cc_status.value1) == REG + && cc_status.value2 + && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) + cc_status.value2 = 0; + if (((cc_status.value1 && FP_REG_P (cc_status.value1)) + || (cc_status.value2 && FP_REG_P (cc_status.value2))) + && !((cc_status.value1 && FPA_REG_P (cc_status.value1)) + || (cc_status.value2 && FPA_REG_P (cc_status.value2)))) + cc_status.flags = CC_IN_68881; +} + +char * +output_move_const_double (operands) + rtx *operands; +{ +#ifdef SUPPORT_SUN_FPA + if (TARGET_FPA && FPA_REG_P (operands[0])) + { + int code = standard_sun_fpa_constant_p (operands[1]); + + if (code != 0) + { + static char buf[40]; + + sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff); + return buf; + } + return "fpmove%.d %1,%0"; + } + else +#endif + { + int code = standard_68881_constant_p (operands[1]); + + if (code != 0) + { + static char buf[40]; + + sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff); + return buf; + } + return "fmove%.d %1,%0"; + } +} + +char * +output_move_const_single (operands) + rtx *operands; +{ +#ifdef SUPPORT_SUN_FPA + if (TARGET_FPA) + { + int code = standard_sun_fpa_constant_p (operands[1]); + + if (code != 0) + { + static char buf[40]; + + sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff); + return buf; + } + return "fpmove%.s %1,%0"; + } + else +#endif /* defined SUPPORT_SUN_FPA */ + { + int code = standard_68881_constant_p (operands[1]); + + if (code != 0) + { + static char buf[40]; + + sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff); + return buf; + } + return "fmove%.s %f1,%0"; + } +} + +/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get + from the "fmovecr" instruction. + The value, anded with 0xff, gives the code to use in fmovecr + to get the desired constant. */ + +/* This code has been fixed for cross-compilation. */ + +static int inited_68881_table = 0; + +char *strings_68881[7] = { + "0.0", + "1.0", + "10.0", + "100.0", + "10000.0", + "1e8", + "1e16" + }; + +int codes_68881[7] = { + 0x0f, + 0x32, + 0x33, + 0x34, + 0x35, + 0x36, + 0x37 + }; + +REAL_VALUE_TYPE values_68881[7]; + +/* Set up values_68881 array by converting the decimal values + strings_68881 to binary. */ + +void +init_68881_table () +{ + int i; + REAL_VALUE_TYPE r; + enum machine_mode mode; + + mode = DFmode; + for (i = 0; i < 7; i++) + { + if (i == 6) + mode = SFmode; + r = REAL_VALUE_ATOF (strings_68881[i], mode); + values_68881[i] = r; + } + inited_68881_table = 1; +} + +int +standard_68881_constant_p (x) + rtx x; +{ + REAL_VALUE_TYPE r; + int i; + enum machine_mode mode; + + /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */ + if (TARGET_68040) + return 0; + +#ifndef REAL_ARITHMETIC +#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT + if (! flag_pretend_float) + return 0; +#endif +#endif + + if (! inited_68881_table) + init_68881_table (); + + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + + for (i = 0; i < 6; i++) + { + if (REAL_VALUES_EQUAL (r, values_68881[i])) + return (codes_68881[i]); + } + + if (GET_MODE (x) == SFmode) + return 0; + + if (REAL_VALUES_EQUAL (r, values_68881[6])) + return (codes_68881[6]); + + /* larger powers of ten in the constants ram are not used + because they are not equal to a `double' C constant. */ + return 0; +} + +/* If X is a floating-point constant, return the logarithm of X base 2, + or 0 if X is not a power of 2. */ + +int +floating_exact_log2 (x) + rtx x; +{ + REAL_VALUE_TYPE r, r1; + int i; + +#ifndef REAL_ARITHMETIC +#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT + if (! flag_pretend_float) + return 0; +#endif +#endif + + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + + if (REAL_VALUES_LESS (r, dconst0)) + return 0; + + r1 = dconst1; + i = 0; + while (REAL_VALUES_LESS (r1, r)) + { + r1 = REAL_VALUE_LDEXP (dconst1, i); + if (REAL_VALUES_EQUAL (r1, r)) + return i; + i = i + 1; + } + return 0; +} + +#ifdef SUPPORT_SUN_FPA +/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get + from the Sun FPA's constant RAM. + The value returned, anded with 0x1ff, gives the code to use in fpmove + to get the desired constant. */ + +static int inited_FPA_table = 0; + +char *strings_FPA[38] = { +/* small rationals */ + "0.0", + "1.0", + "0.5", + "-1.0", + "2.0", + "3.0", + "4.0", + "8.0", + "0.25", + "0.125", + "10.0", + "-0.5", +/* Decimal equivalents of double precision values */ + "2.718281828459045091", /* D_E */ + "6.283185307179586477", /* 2 pi */ + "3.141592653589793116", /* D_PI */ + "1.570796326794896619", /* pi/2 */ + "1.414213562373095145", /* D_SQRT2 */ + "0.7071067811865475244", /* 1/sqrt(2) */ + "-1.570796326794896619", /* -pi/2 */ + "1.442695040888963387", /* D_LOG2ofE */ + "3.321928024887362182", /* D_LOG2of10 */ + "0.6931471805599452862", /* D_LOGEof2 */ + "2.302585092994045901", /* D_LOGEof10 */ + "0.3010299956639811980", /* D_LOG10of2 */ + "0.4342944819032518167", /* D_LOG10ofE */ +/* Decimal equivalents of single precision values */ + "2.718281745910644531", /* S_E */ + "6.283185307179586477", /* 2 pi */ + "3.141592741012573242", /* S_PI */ + "1.570796326794896619", /* pi/2 */ + "1.414213538169860840", /* S_SQRT2 */ + "0.7071067811865475244", /* 1/sqrt(2) */ + "-1.570796326794896619", /* -pi/2 */ + "1.442695021629333496", /* S_LOG2ofE */ + "3.321928024291992188", /* S_LOG2of10 */ + "0.6931471824645996094", /* S_LOGEof2 */ + "2.302585124969482442", /* S_LOGEof10 */ + "0.3010300099849700928", /* S_LOG10of2 */ + "0.4342944920063018799", /* S_LOG10ofE */ +}; + + +int codes_FPA[38] = { +/* small rationals */ + 0x200, + 0xe, + 0xf, + 0x10, + 0x11, + 0xb1, + 0x12, + 0x13, + 0x15, + 0x16, + 0x17, + 0x2e, +/* double precision */ + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0x27, + 0x28, + 0x29, + 0x2a, + 0x2b, + 0x2c, + 0x2d, +/* single precision */ + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0x27, + 0x28, + 0x29, + 0x2a, + 0x2b, + 0x2c, + 0x2d + }; + +REAL_VALUE_TYPE values_FPA[38]; + +/* This code has been fixed for cross-compilation. */ + +void +init_FPA_table () +{ + enum machine_mode mode; + int i; + REAL_VALUE_TYPE r; + + mode = DFmode; + for (i = 0; i < 38; i++) + { + if (i == 25) + mode = SFmode; + r = REAL_VALUE_ATOF (strings_FPA[i], mode); + values_FPA[i] = r; + } + inited_FPA_table = 1; +} + + +int +standard_sun_fpa_constant_p (x) + rtx x; +{ + REAL_VALUE_TYPE r; + int i; + +#ifndef REAL_ARITHMETIC +#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT + if (! flag_pretend_float) + return 0; +#endif +#endif + + if (! inited_FPA_table) + init_FPA_table (); + + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + + for (i=0; i<12; i++) + { + if (REAL_VALUES_EQUAL (r, values_FPA[i])) + return (codes_FPA[i]); + } + + if (GET_MODE (x) == SFmode) + { + for (i=25; i<38; i++) + { + if (REAL_VALUES_EQUAL (r, values_FPA[i])) + return (codes_FPA[i]); + } + } + else + { + for (i=12; i<25; i++) + { + if (REAL_VALUES_EQUAL (r, values_FPA[i])) + return (codes_FPA[i]); + } + } + return 0x0; +} +#endif /* define SUPPORT_SUN_FPA */ + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand X. X is an RTL + expression. + + CODE is a value that can be used to specify one of several ways + of printing the operand. It is used when identical operands + must be printed differently depending on the context. CODE + comes from the `%' specification that was used to request + printing of the operand. If the specification was just `%DIGIT' + then CODE is 0; if the specification was `%LTR DIGIT' then CODE + is the ASCII code for LTR. + + If X is a register, this macro should print the register's name. + The names can be found in an array `reg_names' whose type is + `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. + + When the machine description has a specification `%PUNCT' (a `%' + followed by a punctuation character), this macro is called with + a null pointer for X and the punctuation character for CODE. + + The m68k specific codes are: + + '.' for dot needed in Motorola-style opcode names. + '-' for an operand pushing on the stack: + sp@-, -(sp) or -(%sp) depending on the style of syntax. + '+' for an operand pushing on the stack: + sp@+, (sp)+ or (%sp)+ depending on the style of syntax. + '@' for a reference to the top word on the stack: + sp@, (sp) or (%sp) depending on the style of syntax. + '#' for an immediate operand prefix (# in MIT and Motorola syntax + but & in SGS syntax). + '!' for the cc register (used in an `and to cc' insn). + '$' for the letter `s' in an op code, but only on the 68040. + '&' for the letter `d' in an op code, but only on the 68040. + '/' for register prefix needed by longlong.h. + + 'b' for byte insn (no effect, on the Sun; this is for the ISI). + 'd' to force memory addressing to be absolute, not relative. + 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) + 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather + than directly). Second part of 'y' below. + 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), + or print pair of registers as rx:ry. + 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs + CONST_DOUBLE's as SunFPA constant RAM registers if + possible, so it should not be used except for the SunFPA. + + */ + +void +print_operand (file, op, letter) + FILE *file; /* file to write to */ + rtx op; /* operand to print */ + int letter; /* % or 0 */ +{ + int i; + + if (letter == '.') + { +#ifdef MOTOROLA + asm_fprintf (file, "."); +#endif + } + else if (letter == '#') + { + asm_fprintf (file, "%0I"); + } + else if (letter == '-') + { +#ifdef MOTOROLA + asm_fprintf (file, "-(%Rsp)"); +#else + asm_fprintf (file, "%Rsp@-"); +#endif + } + else if (letter == '+') + { +#ifdef MOTOROLA + asm_fprintf (file, "(%Rsp)+"); +#else + asm_fprintf (file, "%Rsp@+"); +#endif + } + else if (letter == '@') + { +#ifdef MOTOROLA + asm_fprintf (file, "(%Rsp)"); +#else + asm_fprintf (file, "%Rsp@"); +#endif + } + else if (letter == '!') + { + asm_fprintf (file, "%Rfpcr"); + } + else if (letter == '$') + { + if (TARGET_68040_ONLY) + { + fprintf (file, "s"); + } + } + else if (letter == '&') + { + if (TARGET_68040_ONLY) + { + fprintf (file, "d"); + } + } + else if (letter == '/') + { + asm_fprintf (file, "%R"); + } + else if (GET_CODE (op) == REG) + { + if (REGNO (op) < 16 + && (letter == 'y' || letter == 'x') + && GET_MODE (op) == DFmode) + { + fprintf (file, "%s:%s", reg_names[REGNO (op)], + reg_names[REGNO (op)+1]); + } + else + { + fprintf (file, "%s", reg_names[REGNO (op)]); + } + } + else if (GET_CODE (op) == MEM) + { + output_address (XEXP (op, 0)); + if (letter == 'd' && ! TARGET_68020 + && CONSTANT_ADDRESS_P (XEXP (op, 0)) + && !(GET_CODE (XEXP (op, 0)) == CONST_INT + && INTVAL (XEXP (op, 0)) < 0x8000 + && INTVAL (XEXP (op, 0)) >= -0x8000)) + { + fprintf (file, ":l"); + } + } +#ifdef SUPPORT_SUN_FPA + else if ((letter == 'y' || letter == 'w') + && GET_CODE (op) == CONST_DOUBLE + && (i = standard_sun_fpa_constant_p (op))) + { + fprintf (file, "%%%d", i & 0x1ff); + } +#endif + else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) + { + REAL_VALUE_TYPE r; + REAL_VALUE_FROM_CONST_DOUBLE (r, op); + ASM_OUTPUT_FLOAT_OPERAND (letter, file, r); + } + else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) + { + REAL_VALUE_TYPE r; + REAL_VALUE_FROM_CONST_DOUBLE (r, op); + ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r); + } + else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) + { + REAL_VALUE_TYPE r; + REAL_VALUE_FROM_CONST_DOUBLE (r, op); + ASM_OUTPUT_DOUBLE_OPERAND (file, r); + } + else + { + asm_fprintf (file, "%0I"); output_addr_const (file, op); + } +} + + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand that is a memory + reference whose address is ADDR. ADDR is an RTL expression. + + Note that this contains a kludge that knows that the only reason + we have an address (plus (label_ref...) (reg...)) when not generating + PIC code is in the insn before a tablejump, and we know that m68k.md + generates a label LInnn: on such an insn. + + It is possible for PIC to generate a (plus (label_ref...) (reg...)) + and we handle that just like we would a (plus (symbol_ref...) (reg...)). + + Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" + fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results + we want. This difference can be accommodated by using an assembler + define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other + string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END + macro. See m68k/sgs.h for an example; for versions without the bug. + + They also do not like things like "pea 1.w", so we simple leave off + the .w on small constants. + + This routine is responsible for distinguishing between -fpic and -fPIC + style relocations in an address. When generating -fpic code the + offset is output in word mode (eg movel a5@(_foo:w), a0). When generating + -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */ + +void +print_operand_address (file, addr) + FILE *file; + rtx addr; +{ + register rtx reg1, reg2, breg, ireg; + rtx offset; + + switch (GET_CODE (addr)) + { + case REG: +#ifdef MOTOROLA + fprintf (file, "(%s)", reg_names[REGNO (addr)]); +#else + fprintf (file, "%s@", reg_names[REGNO (addr)]); +#endif + break; + case PRE_DEC: +#ifdef MOTOROLA + fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); +#else + fprintf (file, "%s@-", reg_names[REGNO (XEXP (addr, 0))]); +#endif + break; + case POST_INC: +#ifdef MOTOROLA + fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); +#else + fprintf (file, "%s@+", reg_names[REGNO (XEXP (addr, 0))]); +#endif + break; + case PLUS: + reg1 = reg2 = ireg = breg = offset = 0; + if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) + { + offset = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) + { + offset = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) != PLUS) + { + ; + } + else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + else if (GET_CODE (XEXP (addr, 0)) == MULT) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == MULT) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + else if (GET_CODE (XEXP (addr, 0)) == REG) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == REG) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT + || GET_CODE (addr) == SIGN_EXTEND) + { + if (reg1 == 0) + { + reg1 = addr; + } + else + { + reg2 = addr; + } + addr = 0; + } +#if 0 /* for OLD_INDEXING */ + else if (GET_CODE (addr) == PLUS) + { + if (GET_CODE (XEXP (addr, 0)) == REG) + { + reg2 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == REG) + { + reg2 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + } +#endif + if (offset != 0) + { + if (addr != 0) + { + abort (); + } + addr = offset; + } + if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND + || GET_CODE (reg1) == MULT)) + || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) + { + breg = reg2; + ireg = reg1; + } + else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) + { + breg = reg1; + ireg = reg2; + } + if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF + && ! (flag_pic && ireg == pic_offset_table_rtx)) + { + int scale = 1; + if (GET_CODE (ireg) == MULT) + { + scale = INTVAL (XEXP (ireg, 1)); + ireg = XEXP (ireg, 0); + } + if (GET_CODE (ireg) == SIGN_EXTEND) + { +#ifdef MOTOROLA +#ifdef SGS + asm_fprintf (file, "%LLD%d(%Rpc,%s.w", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (XEXP (ireg, 0))]); +#else + asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.w", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (XEXP (ireg, 0))]); +#endif +#else + asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:w", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (XEXP (ireg, 0))]); +#endif + } + else + { +#ifdef MOTOROLA +#ifdef SGS + asm_fprintf (file, "%LLD%d(%Rpc,%s.l", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (ireg)]); +#else + asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.l", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (ireg)]); +#endif +#else + asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:l", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (ireg)]); +#endif + } + if (scale != 1) + { +#ifdef MOTOROLA + fprintf (file, "*%d", scale); +#else + fprintf (file, ":%d", scale); +#endif + } + putc (')', file); + break; + } + if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF + && ! (flag_pic && breg == pic_offset_table_rtx)) + { +#ifdef MOTOROLA +#ifdef SGS + asm_fprintf (file, "%LLD%d(%Rpc,%s.l", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (breg)]); +#else + asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.l", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (breg)]); +#endif +#else + asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:l", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (breg)]); +#endif + putc (')', file); + break; + } + if (ireg != 0 || breg != 0) + { + int scale = 1; + if (breg == 0) + { + abort (); + } + if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF) + { + abort (); + } +#ifdef MOTOROLA + if (addr != 0) + { + output_addr_const (file, addr); + if (flag_pic && (breg == pic_offset_table_rtx)) + fprintf (file, "@GOT"); + } + fprintf (file, "(%s", reg_names[REGNO (breg)]); + if (ireg != 0) + { + putc (',', file); + } +#else + fprintf (file, "%s@(", reg_names[REGNO (breg)]); + if (addr != 0) + { + output_addr_const (file, addr); + if ((flag_pic == 1) && (breg == pic_offset_table_rtx)) + fprintf (file, ":w"); + if ((flag_pic == 2) && (breg == pic_offset_table_rtx)) + fprintf (file, ":l"); + } + if (addr != 0 && ireg != 0) + { + putc (',', file); + } +#endif + if (ireg != 0 && GET_CODE (ireg) == MULT) + { + scale = INTVAL (XEXP (ireg, 1)); + ireg = XEXP (ireg, 0); + } + if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) + { +#ifdef MOTOROLA + fprintf (file, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); +#else + fprintf (file, "%s:w", reg_names[REGNO (XEXP (ireg, 0))]); +#endif + } + else if (ireg != 0) + { +#ifdef MOTOROLA + fprintf (file, "%s.l", reg_names[REGNO (ireg)]); +#else + fprintf (file, "%s:l", reg_names[REGNO (ireg)]); +#endif + } + if (scale != 1) + { +#ifdef MOTOROLA + fprintf (file, "*%d", scale); +#else + fprintf (file, ":%d", scale); +#endif + } + putc (')', file); + break; + } + else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF + && ! (flag_pic && reg1 == pic_offset_table_rtx)) + { +#ifdef MOTOROLA +#ifdef SGS + asm_fprintf (file, "%LLD%d(%Rpc,%s.l)", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (reg1)]); +#else + asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.l)", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (reg1)]); +#endif +#else + asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:l)", + CODE_LABEL_NUMBER (XEXP (addr, 0)), + CODE_LABEL_NUMBER (XEXP (addr, 0)), + reg_names[REGNO (reg1)]); +#endif + break; + } + /* FALL-THROUGH (is this really what we want? */ + default: + if (GET_CODE (addr) == CONST_INT + && INTVAL (addr) < 0x8000 + && INTVAL (addr) >= -0x8000) + { +#ifdef MOTOROLA +#ifdef SGS + /* Many SGS assemblers croak on size specifiers for constants. */ + fprintf (file, "%d", INTVAL (addr)); +#else + fprintf (file, "%d.w", INTVAL (addr)); +#endif +#else + fprintf (file, "%d:w", INTVAL (addr)); +#endif + } + else + { + output_addr_const (file, addr); + } + break; + } +} + +/* Check for cases where a clr insns can be omitted from code using + strict_low_part sets. For example, the second clrl here is not needed: + clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... + + MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear + insn we are checking for redundancy. TARGET is the register set by the + clear insn. */ + +int +strict_low_part_peephole_ok (mode, first_insn, target) + enum machine_mode mode; + rtx first_insn; + rtx target; +{ + rtx p; + + p = prev_nonnote_insn (first_insn); + + while (p) + { + /* If it isn't an insn, then give up. */ + if (GET_CODE (p) != INSN) + return 0; + + if (reg_set_p (target, p)) + { + rtx set = single_set (p); + rtx dest; + + /* If it isn't an easy to recognize insn, then give up. */ + if (! set) + return 0; + + dest = SET_DEST (set); + + /* If this sets the entire target register to zero, then our + first_insn is redundant. */ + if (rtx_equal_p (dest, target) + && SET_SRC (set) == const0_rtx) + return 1; + else if (GET_CODE (dest) == STRICT_LOW_PART + && GET_CODE (XEXP (dest, 0)) == REG + && REGNO (XEXP (dest, 0)) == REGNO (target) + && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) + <= GET_MODE_SIZE (mode))) + /* This is a strict low part set which modifies less than + we are using, so it is safe. */ + ; + else + return 0; + } + + p = prev_nonnote_insn (p); + + } + + return 0; +} diff --git a/gnu/usr.bin/gcc2/arch/m68k/config.h b/gnu/usr.bin/gcc2/arch/m68k/config.h new file mode 100644 index 000000000000..354f46729b95 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/config.h @@ -0,0 +1,50 @@ +/* Configuration for GNU C-compiler for Motorola 68000 family. + Copyright (C) 1987 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + + $Id: config.h,v 1.1 1993/11/25 01:25:59 paulus Exp $ +*/ + + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +#define HOST_WORDS_BIG_ENDIAN + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ +#include "tm.h" + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +/* If compiled with GNU C, use the built-in alloca */ +#ifdef __GNUC__ +/* Use an arg in this macro because that's what some other + system does--let's avoid conflict. */ +#define alloca(x) __builtin_alloca(x) +#endif diff --git a/gnu/usr.bin/gcc2/arch/m68k/ctype.h b/gnu/usr.bin/gcc2/arch/m68k/ctype.h new file mode 100644 index 000000000000..880c4d388500 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/ctype.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 1989 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)ctype.h 5.3 (Berkeley) 4/3/91 + */ + +#ifndef _CTYPE_H_ +#define _CTYPE_H_ + +#define _U 0x01 +#define _L 0x02 +#define _N 0x04 +#define _S 0x08 +#define _P 0x10 +#define _C 0x20 +#define _X 0x40 +#define _B 0x80 + +extern char _ctype_[]; + +#define isdigit(c) ((_ctype_ + 1)[c] & _N) +#define islower(c) ((_ctype_ + 1)[c] & _L) +#define isspace(c) ((_ctype_ + 1)[c] & _S) +#define ispunct(c) ((_ctype_ + 1)[c] & _P) +#define isupper(c) ((_ctype_ + 1)[c] & _U) +#define isalpha(c) ((_ctype_ + 1)[c] & (_U|_L)) +#define isxdigit(c) ((_ctype_ + 1)[c] & (_N|_X)) +#define isalnum(c) ((_ctype_ + 1)[c] & (_U|_L|_N)) +#define isprint(c) ((_ctype_ + 1)[c] & (_P|_U|_L|_N|_B)) +#define isgraph(c) ((_ctype_ + 1)[c] & (_P|_U|_L|_N)) +#define iscntrl(c) ((_ctype_ + 1)[c] & _C) +#define isascii(c) ((unsigned)(c) <= 0177) +#define toupper(c) ((c) - 'a' + 'A') +#define tolower(c) ((c) - 'A' + 'a') +#define toascii(c) ((c) & 0177) + +#endif /* !_CTYPE_H_ */ diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-attr.h b/gnu/usr.bin/gcc2/arch/m68k/insn-attr.h new file mode 100644 index 000000000000..5fe9a2f80012 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-attr.h @@ -0,0 +1,19 @@ +/* Generated automatically by the program `genattr' +from the machine description file `md'. */ + +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif +#define HAVE_ATTR_alternative +#define get_attr_alternative(insn) which_alternative + +#define ATTR_FLAG_forward 0x1 +#define ATTR_FLAG_backward 0x2 +#define ATTR_FLAG_likely 0x4 +#define ATTR_FLAG_very_likely 0x8 +#define ATTR_FLAG_unlikely 0x10 +#define ATTR_FLAG_very_unlikely 0x20 diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-attrtab.c b/gnu/usr.bin/gcc2/arch/m68k/insn-attrtab.c new file mode 100644 index 000000000000..0e86d1f4c35a --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-attrtab.c @@ -0,0 +1,14 @@ +/* Generated automatically by the program `genattrtab' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "recog.h" +#include "regs.h" +#include "real.h" +#include "output.h" +#include "insn-attr.h" + +#define operands recog_operand + diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-codes.h b/gnu/usr.bin/gcc2/arch/m68k/insn-codes.h new file mode 100644 index 000000000000..35b48afb5612 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-codes.h @@ -0,0 +1,184 @@ +/* Generated automatically by the program `gencodes' +from the machine description file `md'. */ + +#ifndef MAX_INSN_CODE + +enum insn_code { + CODE_FOR_tstsi = 2, + CODE_FOR_tsthi = 3, + CODE_FOR_tstqi = 4, + CODE_FOR_tstsf = 5, + CODE_FOR_tstsf_fpa = 6, + CODE_FOR_tstdf = 8, + CODE_FOR_tstdf_fpa = 9, + CODE_FOR_cmpsi = 11, + CODE_FOR_cmphi = 12, + CODE_FOR_cmpqi = 13, + CODE_FOR_cmpdf = 14, + CODE_FOR_cmpdf_fpa = 15, + CODE_FOR_cmpsf = 17, + CODE_FOR_cmpsf_fpa = 18, + CODE_FOR_movsi = 28, + CODE_FOR_movhi = 30, + CODE_FOR_movstricthi = 31, + CODE_FOR_movqi = 32, + CODE_FOR_movstrictqi = 33, + CODE_FOR_movsf = 34, + CODE_FOR_movdf = 35, + CODE_FOR_movxf = 36, + CODE_FOR_movdi = 39, + CODE_FOR_pushasi = 40, + CODE_FOR_truncsiqi2 = 41, + CODE_FOR_trunchiqi2 = 42, + CODE_FOR_truncsihi2 = 43, + CODE_FOR_zero_extendhisi2 = 44, + CODE_FOR_zero_extendqihi2 = 45, + CODE_FOR_zero_extendqisi2 = 46, + CODE_FOR_extendhisi2 = 50, + CODE_FOR_extendqihi2 = 51, + CODE_FOR_extendqisi2 = 52, + CODE_FOR_extendsfdf2 = 53, + CODE_FOR_truncdfsf2 = 56, + CODE_FOR_floatsisf2 = 60, + CODE_FOR_floatsidf2 = 63, + CODE_FOR_floathisf2 = 66, + CODE_FOR_floathidf2 = 67, + CODE_FOR_floatqisf2 = 68, + CODE_FOR_floatqidf2 = 69, + CODE_FOR_fix_truncdfsi2 = 70, + CODE_FOR_fix_truncdfhi2 = 71, + CODE_FOR_fix_truncdfqi2 = 72, + CODE_FOR_ftruncdf2 = 73, + CODE_FOR_ftruncsf2 = 74, + CODE_FOR_fixsfqi2 = 75, + CODE_FOR_fixsfhi2 = 76, + CODE_FOR_fixsfsi2 = 77, + CODE_FOR_fixdfqi2 = 78, + CODE_FOR_fixdfhi2 = 79, + CODE_FOR_fixdfsi2 = 80, + CODE_FOR_addsi3 = 83, + CODE_FOR_addhi3 = 85, + CODE_FOR_addqi3 = 88, + CODE_FOR_adddf3 = 91, + CODE_FOR_addsf3 = 94, + CODE_FOR_subsi3 = 97, + CODE_FOR_subhi3 = 99, + CODE_FOR_subqi3 = 101, + CODE_FOR_subdf3 = 103, + CODE_FOR_subsf3 = 106, + CODE_FOR_mulhi3 = 109, + CODE_FOR_mulhisi3 = 110, + CODE_FOR_mulsi3 = 112, + CODE_FOR_umulhisi3 = 113, + CODE_FOR_umulsidi3 = 115, + CODE_FOR_mulsidi3 = 118, + CODE_FOR_muldf3 = 121, + CODE_FOR_mulsf3 = 124, + CODE_FOR_divhi3 = 127, + CODE_FOR_divhisi3 = 128, + CODE_FOR_udivhi3 = 130, + CODE_FOR_udivhisi3 = 131, + CODE_FOR_divdf3 = 133, + CODE_FOR_divsf3 = 136, + CODE_FOR_modhi3 = 139, + CODE_FOR_modhisi3 = 140, + CODE_FOR_umodhi3 = 142, + CODE_FOR_umodhisi3 = 143, + CODE_FOR_divmodsi4 = 145, + CODE_FOR_udivmodsi4 = 146, + CODE_FOR_andsi3 = 147, + CODE_FOR_andhi3 = 148, + CODE_FOR_andqi3 = 151, + CODE_FOR_iorsi3 = 154, + CODE_FOR_iorhi3 = 155, + CODE_FOR_iorqi3 = 158, + CODE_FOR_xorsi3 = 161, + CODE_FOR_xorhi3 = 162, + CODE_FOR_xorqi3 = 165, + CODE_FOR_negsi2 = 168, + CODE_FOR_neghi2 = 169, + CODE_FOR_negqi2 = 171, + CODE_FOR_negsf2 = 173, + CODE_FOR_negdf2 = 176, + CODE_FOR_sqrtdf2 = 179, + CODE_FOR_abssf2 = 180, + CODE_FOR_absdf2 = 183, + CODE_FOR_one_cmplsi2 = 186, + CODE_FOR_one_cmplhi2 = 187, + CODE_FOR_one_cmplqi2 = 189, + CODE_FOR_ashlsi3 = 193, + CODE_FOR_ashlhi3 = 194, + CODE_FOR_ashlqi3 = 196, + CODE_FOR_ashrsi3 = 200, + CODE_FOR_ashrhi3 = 201, + CODE_FOR_ashrqi3 = 203, + CODE_FOR_lshlsi3 = 207, + CODE_FOR_lshlhi3 = 208, + CODE_FOR_lshlqi3 = 210, + CODE_FOR_lshrsi3 = 214, + CODE_FOR_lshrhi3 = 215, + CODE_FOR_lshrqi3 = 217, + CODE_FOR_rotlsi3 = 219, + CODE_FOR_rotlhi3 = 220, + CODE_FOR_rotlqi3 = 222, + CODE_FOR_rotrsi3 = 224, + CODE_FOR_rotrhi3 = 225, + CODE_FOR_rotrqi3 = 227, + CODE_FOR_extv = 235, + CODE_FOR_extzv = 236, + CODE_FOR_insv = 240, + CODE_FOR_seq = 248, + CODE_FOR_sne = 249, + CODE_FOR_sgt = 250, + CODE_FOR_sgtu = 251, + CODE_FOR_slt = 252, + CODE_FOR_sltu = 253, + CODE_FOR_sge = 254, + CODE_FOR_sgeu = 255, + CODE_FOR_sle = 256, + CODE_FOR_sleu = 257, + CODE_FOR_beq = 258, + CODE_FOR_bne = 259, + CODE_FOR_bgt = 260, + CODE_FOR_bgtu = 261, + CODE_FOR_blt = 262, + CODE_FOR_bltu = 263, + CODE_FOR_bge = 264, + CODE_FOR_bgeu = 265, + CODE_FOR_ble = 266, + CODE_FOR_bleu = 267, + CODE_FOR_jump = 278, + CODE_FOR_tablejump = 279, + CODE_FOR_decrement_and_branch_until_zero = 285, + CODE_FOR_call = 286, + CODE_FOR_call_value = 289, + CODE_FOR_untyped_call = 292, + CODE_FOR_blockage = 293, + CODE_FOR_nop = 294, + CODE_FOR_probe = 295, + CODE_FOR_return = 296, + CODE_FOR_indirect_jump = 297, + CODE_FOR_tstxf = 318, + CODE_FOR_cmpxf = 319, + CODE_FOR_extendsfxf2 = 321, + CODE_FOR_extenddfxf2 = 322, + CODE_FOR_truncxfdf2 = 323, + CODE_FOR_truncxfsf2 = 324, + CODE_FOR_floatsixf2 = 325, + CODE_FOR_floathixf2 = 326, + CODE_FOR_floatqixf2 = 327, + CODE_FOR_ftruncxf2 = 328, + CODE_FOR_fixxfqi2 = 329, + CODE_FOR_fixxfhi2 = 330, + CODE_FOR_fixxfsi2 = 331, + CODE_FOR_addxf3 = 332, + CODE_FOR_subxf3 = 334, + CODE_FOR_mulxf3 = 336, + CODE_FOR_divxf3 = 338, + CODE_FOR_negxf2 = 340, + CODE_FOR_absxf2 = 341, + CODE_FOR_sqrtxf2 = 342, + CODE_FOR_nothing }; + +#define MAX_INSN_CODE ((int) CODE_FOR_nothing) +#endif /* MAX_INSN_CODE */ diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-config.h b/gnu/usr.bin/gcc2/arch/m68k/insn-config.h new file mode 100644 index 000000000000..7dba8866f62f --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-config.h @@ -0,0 +1,12 @@ +/* Generated automatically by the program `genconfig' +from the machine description file `md'. */ + + +#define MAX_RECOG_OPERANDS 10 + +#define MAX_DUP_OPERANDS 3 +#ifndef MAX_INSNS_PER_SPLIT +#define MAX_INSNS_PER_SPLIT 1 +#endif +#define REGISTER_CONSTRAINTS +#define HAVE_cc0 diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-emit.c b/gnu/usr.bin/gcc2/arch/m68k/insn-emit.c new file mode 100644 index 000000000000..6b2694f69d5b --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-emit.c @@ -0,0 +1,1897 @@ +/* Generated automatically by the program `genemit' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "expr.h" +#include "real.h" +#include "output.h" +#include "insn-config.h" + +#include "insn-flags.h" + +#include "insn-codes.h" + +extern char *insn_operand_constraint[][MAX_RECOG_OPERANDS]; + +extern rtx recog_operand[]; +#define operands emit_operand + +#define FAIL goto _fail + +#define DONE goto _done + +rtx +gen_tstsi (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tsthi (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tstqi (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tstsf (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + if (TARGET_FPA) + { + emit_insn (gen_tstsf_fpa (operands[0])); + DONE; + } +} + operand0 = operands[0]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, operand0)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tstsf_fpa (operand0) + rtx operand0; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, operand0), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)))); +} + +rtx +gen_tstdf (operand0) + rtx operand0; +{ + rtx operands[1]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + +{ + if (TARGET_FPA) + { + emit_insn (gen_tstsf_fpa (operands[0])); + DONE; + } +} + operand0 = operands[0]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, operand0)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_tstdf_fpa (operand0) + rtx operand0; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, operand0), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)))); +} + +rtx +gen_cmpsi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmphi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmpqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmpdf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (TARGET_FPA) + { + emit_insn (gen_cmpdf_fpa (operands[0], operands[1])); + DONE; + } +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpdf_fpa (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)))); +} + +rtx +gen_cmpsf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (TARGET_FPA) + { + emit_insn (gen_cmpsf_fpa (operands[0], operands[1])); + DONE; + } +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_cmpsf_fpa (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)))); +} + +rtx +gen_movsi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (flag_pic && symbolic_operand (operands[1], SImode)) + { + /* The source is an address which requires PIC relocation. + Call legitimize_pic_address with the source, mode, and a relocation + register (a new pseudo, or the final destination if reload_in_progress + is set). Then fall through normally */ + extern rtx legitimize_pic_address(); + rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); + operands[1] = legitimize_pic_address (operands[1], SImode, temp); + } +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_movhi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movstricthi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand0), operand1); +} + +rtx +gen_movqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movstrictqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand0), operand1); +} + +rtx +gen_movsf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movdf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movxf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (CONSTANT_P (operands[1])) + { + operands[1] = force_const_mem (XFmode, operands[1]); + if (! memory_address_p (XFmode, XEXP (operands[1], 0)) + && ! reload_in_progress) + operands[1] = change_address (operands[1], XFmode, + XEXP (operands[1], 0)); + } +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_movdi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_pushasi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_truncsiqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (TRUNCATE, QImode, operand1)); +} + +rtx +gen_trunchiqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (TRUNCATE, QImode, operand1)); +} + +rtx +gen_truncsihi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (TRUNCATE, HImode, operand1)); +} + +rtx +gen_zero_extendhisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[1] = make_safe_from (operands[1], operands[0]); + if (GET_CODE (operands[0]) == SUBREG) + operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]), + SUBREG_WORD (operands[0])); + else + operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, const0_rtx)); + emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand2), operand1)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_zero_extendqihi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[1] = make_safe_from (operands[1], operands[0]); + if (GET_CODE (operands[0]) == SUBREG) + operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]), + SUBREG_WORD (operands[0])); + else + operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, const0_rtx)); + emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand2), operand1)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_zero_extendqisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operand2; + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + operands[1] = make_safe_from (operands[1], operands[0]); + if (GET_CODE (operands[0]) == SUBREG) + operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]), + SUBREG_WORD (operands[0])); + else + operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, const0_rtx)); + emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand2), operand1)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_extendhisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, SImode, operand1)); +} + +rtx +gen_extendqihi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, HImode, operand1)); +} + +rtx +gen_extendqisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, SImode, operand1)); +} + +rtx +gen_extendsfdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_EXTEND, DFmode, operand1)); +} + +rtx +gen_truncdfsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_TRUNCATE, SFmode, operand1)); +} + +rtx +gen_floatsisf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, SFmode, operand1)); +} + +rtx +gen_floatsidf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, DFmode, operand1)); +} + +rtx +gen_floathisf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, SFmode, operand1)); +} + +rtx +gen_floathidf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, DFmode, operand1)); +} + +rtx +gen_floatqisf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, SFmode, operand1)); +} + +rtx +gen_floatqidf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, DFmode, operand1)); +} + +rtx +gen_fix_truncdfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (3, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, gen_rtx (FIX, DFmode, operand1))), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)))); +} + +rtx +gen_fix_truncdfhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (3, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, HImode, gen_rtx (FIX, DFmode, operand1))), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)))); +} + +rtx +gen_fix_truncdfqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (3, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, QImode, gen_rtx (FIX, DFmode, operand1))), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)))); +} + +rtx +gen_ftruncdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, DFmode, operand1)); +} + +rtx +gen_ftruncsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SFmode, operand1)); +} + +rtx +gen_fixsfqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, QImode, operand1)); +} + +rtx +gen_fixsfhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, HImode, operand1)); +} + +rtx +gen_fixsfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, operand1)); +} + +rtx +gen_fixdfqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, QImode, operand1)); +} + +rtx +gen_fixdfhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, HImode, operand1)); +} + +rtx +gen_fixdfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, operand1)); +} + +rtx +gen_addsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SImode, operand1, operand2)); +} + +rtx +gen_addhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, HImode, operand1, operand2)); +} + +rtx +gen_addqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, QImode, operand1, operand2)); +} + +rtx +gen_adddf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, DFmode, operand1, operand2)); +} + +rtx +gen_addsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SFmode, operand1, operand2)); +} + +rtx +gen_subsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, SImode, operand1, operand2)); +} + +rtx +gen_subhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, HImode, operand1, operand2)); +} + +rtx +gen_subqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, QImode, operand1, operand2)); +} + +rtx +gen_subdf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, DFmode, operand1, operand2)); +} + +rtx +gen_subsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, SFmode, operand1, operand2)); +} + +rtx +gen_mulhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, HImode, operand1, operand2)); +} + +rtx +gen_mulhisi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SImode, gen_rtx (SIGN_EXTEND, SImode, operand1), gen_rtx (SIGN_EXTEND, SImode, operand2))); +} + +rtx +gen_mulsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SImode, operand1, operand2)); +} + +rtx +gen_umulhisi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SImode, gen_rtx (ZERO_EXTEND, SImode, operand1), gen_rtx (ZERO_EXTEND, SImode, operand2))); +} + +rtx +gen_umulsidi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, operand0, 1), gen_rtx (MULT, SImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, operand0, 0), gen_rtx (TRUNCATE, SImode, gen_rtx (LSHIFTRT, DImode, gen_rtx (MULT, DImode, gen_rtx (ZERO_EXTEND, DImode, operand1), gen_rtx (ZERO_EXTEND, DImode, operand2)), GEN_INT (32)))))); +} + +rtx +gen_mulsidi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, operand0, 1), gen_rtx (MULT, SImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, operand0, 0), gen_rtx (TRUNCATE, SImode, gen_rtx (ASHIFT, DImode, gen_rtx (MULT, DImode, gen_rtx (SIGN_EXTEND, DImode, operand1), gen_rtx (SIGN_EXTEND, DImode, operand2)), GEN_INT (32)))))); +} + +rtx +gen_muldf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, DFmode, operand1, operand2)); +} + +rtx +gen_mulsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SFmode, operand1, operand2)); +} + +rtx +gen_divhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, HImode, operand1, operand2)); +} + +rtx +gen_divhisi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (TRUNCATE, HImode, gen_rtx (DIV, SImode, operand1, gen_rtx (SIGN_EXTEND, SImode, operand2)))); +} + +rtx +gen_udivhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, HImode, operand1, operand2)); +} + +rtx +gen_udivhisi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (TRUNCATE, HImode, gen_rtx (UDIV, SImode, operand1, gen_rtx (ZERO_EXTEND, SImode, operand2)))); +} + +rtx +gen_divdf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, DFmode, operand1, operand2)); +} + +rtx +gen_divsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, SFmode, operand1, operand2)); +} + +rtx +gen_modhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MOD, HImode, operand1, operand2)); +} + +rtx +gen_modhisi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (TRUNCATE, HImode, gen_rtx (MOD, SImode, operand1, gen_rtx (SIGN_EXTEND, SImode, operand2)))); +} + +rtx +gen_umodhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UMOD, HImode, operand1, operand2)); +} + +rtx +gen_umodhisi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (TRUNCATE, HImode, gen_rtx (UMOD, SImode, operand1, gen_rtx (ZERO_EXTEND, SImode, operand2)))); +} + +rtx +gen_divmodsi4 (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, SImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, operand3, gen_rtx (MOD, SImode, operand1, operand2)))); +} + +rtx +gen_udivmodsi4 (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, SImode, operand1, operand2)), + gen_rtx (SET, VOIDmode, operand3, gen_rtx (UMOD, SImode, operand1, operand2)))); +} + +rtx +gen_andsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, SImode, operand1, operand2)); +} + +rtx +gen_andhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, HImode, operand1, operand2)); +} + +rtx +gen_andqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, QImode, operand1, operand2)); +} + +rtx +gen_iorsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, SImode, operand1, operand2)); +} + +rtx +gen_iorhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, HImode, operand1, operand2)); +} + +rtx +gen_iorqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, QImode, operand1, operand2)); +} + +rtx +gen_xorsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, SImode, operand1, operand2)); +} + +rtx +gen_xorhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, HImode, operand1, operand2)); +} + +rtx +gen_xorqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, QImode, operand1, operand2)); +} + +rtx +gen_negsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, SImode, operand1)); +} + +rtx +gen_neghi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, HImode, operand1)); +} + +rtx +gen_negqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, QImode, operand1)); +} + +rtx +gen_negsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, SFmode, operand1)); +} + +rtx +gen_negdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, DFmode, operand1)); +} + +rtx +gen_sqrtdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SQRT, DFmode, operand1)); +} + +rtx +gen_abssf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, SFmode, operand1)); +} + +rtx +gen_absdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, DFmode, operand1)); +} + +rtx +gen_one_cmplsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, SImode, operand1)); +} + +rtx +gen_one_cmplhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, HImode, operand1)); +} + +rtx +gen_one_cmplqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, QImode, operand1)); +} + +rtx +gen_ashlsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, SImode, operand1, operand2)); +} + +rtx +gen_ashlhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, HImode, operand1, operand2)); +} + +rtx +gen_ashlqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, QImode, operand1, operand2)); +} + +rtx +gen_ashrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, SImode, operand1, operand2)); +} + +rtx +gen_ashrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, HImode, operand1, operand2)); +} + +rtx +gen_ashrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, QImode, operand1, operand2)); +} + +rtx +gen_lshlsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFT, SImode, operand1, operand2)); +} + +rtx +gen_lshlhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFT, HImode, operand1, operand2)); +} + +rtx +gen_lshlqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFT, QImode, operand1, operand2)); +} + +rtx +gen_lshrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, SImode, operand1, operand2)); +} + +rtx +gen_lshrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, HImode, operand1, operand2)); +} + +rtx +gen_lshrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, QImode, operand1, operand2)); +} + +rtx +gen_rotlsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, SImode, operand1, operand2)); +} + +rtx +gen_rotlhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, HImode, operand1, operand2)); +} + +rtx +gen_rotlqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, QImode, operand1, operand2)); +} + +rtx +gen_rotrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, SImode, operand1, operand2)); +} + +rtx +gen_rotrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, HImode, operand1, operand2)); +} + +rtx +gen_rotrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, QImode, operand1, operand2)); +} + +rtx +gen_extv (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTRACT, SImode, operand1, operand2, operand3)); +} + +rtx +gen_extzv (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTRACT, SImode, operand1, operand2, operand3)); +} + +rtx +gen_insv (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (SET, VOIDmode, gen_rtx (ZERO_EXTRACT, SImode, operand0, operand1, operand2), operand3); +} + +rtx +gen_seq (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (EQ, QImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sne (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NE, QImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sgt (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (GT, QImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sgtu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (GTU, QImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_slt (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LT, QImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sltu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LTU, QImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sge (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (GE, QImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sgeu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (GEU, QImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sle (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LE, QImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sleu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LEU, QImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_beq (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (EQ, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bne (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (NE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bgt (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GT, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bgtu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GTU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_blt (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LT, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bltu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LTU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bge (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bgeu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GEU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_ble (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bleu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LEU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_jump (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (LABEL_REF, VOIDmode, operand0)); +} + +rtx +gen_tablejump (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ +#ifdef CASE_VECTOR_PC_RELATIVE + operands[0] = gen_rtx (PLUS, SImode, pc_rtx, operands[0]); +#endif +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, pc_rtx, operand0), + gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, operand1))))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_decrement_and_branch_until_zero (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GE, VOIDmode, gen_rtx (PLUS, SImode, operand0, constm1_rtx), const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand1), pc_rtx)), + gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SImode, operand0, constm1_rtx)))); +} + +rtx +gen_call (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) + SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1; +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_call_insn (gen_rtx (CALL, VOIDmode, operand0, operand1)); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_call_value (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) + SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_call_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (CALL, VOIDmode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_untyped_call (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_call_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (3, + gen_rtx (CALL, VOIDmode, operand0, const0_rtx), + operand1, + operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_blockage () +{ + return gen_rtx (UNSPEC_VOLATILE, VOIDmode, gen_rtvec (1, + const0_rtx), 0); +} + +rtx +gen_nop () +{ + return const0_rtx; +} + +rtx +gen_probe () +{ + return gen_rtx (REG, SImode, 15); +} + +rtx +gen_return () +{ + return gen_rtx (RETURN, VOIDmode); +} + +rtx +gen_indirect_jump (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, operand0); +} + +rtx +gen_tstxf (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_cmpxf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + rtx operands[2]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + +{ + if (CONSTANT_P (operands[0])) + operands[0] = force_const_mem (XFmode, operands[0]); + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (XFmode, operands[1]); +} + operand0 = operands[0]; + operand1 = operands[1]; + emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_extendsfxf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_EXTEND, XFmode, operand1)); +} + +rtx +gen_extenddfxf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_EXTEND, XFmode, operand1)); +} + +rtx +gen_truncxfdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_TRUNCATE, DFmode, operand1)); +} + +rtx +gen_truncxfsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_TRUNCATE, SFmode, operand1)); +} + +rtx +gen_floatsixf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, XFmode, operand1)); +} + +rtx +gen_floathixf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, XFmode, operand1)); +} + +rtx +gen_floatqixf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, XFmode, operand1)); +} + +rtx +gen_ftruncxf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, XFmode, operand1)); +} + +rtx +gen_fixxfqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, QImode, operand1)); +} + +rtx +gen_fixxfhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, HImode, operand1)); +} + +rtx +gen_fixxfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, operand1)); +} + +rtx +gen_addxf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (XFmode, operands[1]); + if (CONSTANT_P (operands[2])) + operands[2] = force_const_mem (XFmode, operands[2]); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, XFmode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_subxf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (XFmode, operands[1]); + if (CONSTANT_P (operands[2])) + operands[2] = force_const_mem (XFmode, operands[2]); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, XFmode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_mulxf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (XFmode, operands[1]); + if (CONSTANT_P (operands[2])) + operands[2] = force_const_mem (XFmode, operands[2]); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, XFmode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_divxf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (XFmode, operands[1]); + if (CONSTANT_P (operands[2])) + operands[2] = force_const_mem (XFmode, operands[2]); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, XFmode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_negxf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, XFmode, operand1)); +} + +rtx +gen_absxf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, XFmode, operand1)); +} + +rtx +gen_sqrtxf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SQRT, XFmode, operand1)); +} + + + +void +add_clobbers (pattern, insn_code_number) + rtx pattern; + int insn_code_number; +{ + int i; + + switch (insn_code_number) + { + case 72: + case 71: + case 70: + XVECEXP (pattern, 0, 1) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)); + XVECEXP (pattern, 0, 2) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)); + break; + + case 18: + case 15: + case 9: + case 6: + XVECEXP (pattern, 0, 1) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)); + break; + + default: + abort (); + } +} diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-extract.c b/gnu/usr.bin/gcc2/arch/m68k/insn-extract.c new file mode 100644 index 000000000000..82338e52e321 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-extract.c @@ -0,0 +1,558 @@ +/* Generated automatically by the program `genextract' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" + +static rtx junk; +extern rtx recog_operand[]; +extern rtx *recog_operand_loc[]; +extern rtx *recog_dup_loc[]; +extern char recog_dup_num[]; +extern +#ifdef __GNUC__ +__volatile__ +#endif +void fatal_insn_not_found (); + +void +insn_extract (insn) + rtx insn; +{ + register rtx *ro = recog_operand; + register rtx **ro_loc = recog_operand_loc; + rtx pat = PATTERN (insn); + switch (INSN_CODE (insn)) + { + case -1: + fatal_insn_not_found (insn); + + case 305: + case 304: + case 303: + case 302: + case 301: + case 300: + case 299: +#if __GNUC__ > 1 && !defined (bcopy) +#define bcopy(FROM,TO,COUNT) __builtin_memcpy(TO,FROM,COUNT) +#endif + bcopy (&XVECEXP (pat, 0, 0), ro, + sizeof (rtx) * XVECLEN (pat, 0)); + break; + + case 317: + case 315: + case 309: + case 308: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XEXP (XEXP (pat, 1), 1), 1)); + break; + + case 316: + case 314: + case 313: + case 312: + case 311: + case 310: + case 307: + case 306: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 0), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 296: + case 295: + case 294: + case 293: + break; + + case 285: + case 284: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 0; + recog_dup_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0); + recog_dup_num[1] = 0; + break; + + case 283: + case 282: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 0; + recog_dup_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0); + recog_dup_num[1] = 0; + break; + + case 281: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0)); + break; + + case 280: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0)); + break; + + case 278: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + break; + + case 277: + case 276: + case 275: + case 274: + case 273: + case 272: + case 271: + case 270: + case 269: + case 268: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 2), 0)); + break; + + case 267: + case 266: + case 265: + case 264: + case 263: + case 262: + case 261: + case 260: + case 259: + case 258: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + break; + + case 247: + case 246: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 2)); + break; + + case 244: + case 243: + case 239: + case 238: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 0), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 0), 2)); + break; + + case 237: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 0), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 0), 2)); + ro[3] = *(ro_loc[3] = &XEXP (XEXP (pat, 1), 1)); + recog_dup_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 0), 0); + recog_dup_num[0] = 0; + recog_dup_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 1); + recog_dup_num[1] = 1; + recog_dup_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 0), 2); + recog_dup_num[2] = 2; + break; + + case 242: + case 241: + case 236: + case 235: + case 234: + case 233: + case 232: + case 231: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XEXP (pat, 1), 2)); + break; + + case 245: + case 240: + case 230: + case 229: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 0), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 0), 2)); + ro[3] = *(ro_loc[3] = &XEXP (pat, 1)); + break; + + case 190: + case 188: + case 172: + case 170: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + recog_dup_loc[0] = &XEXP (XEXP (pat, 1), 0); + recog_dup_num[0] = 0; + break; + + case 146: + case 145: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + recog_dup_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0); + recog_dup_num[0] = 1; + recog_dup_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1); + recog_dup_num[1] = 2; + break; + + case 144: + case 141: + case 132: + case 129: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 0), 1)); + break; + + case 143: + case 140: + case 131: + case 128: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (XEXP (pat, 1), 0), 1), 0)); + break; + + case 120: + case 117: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + recog_dup_loc[0] = &XEXP (XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0), 0), 0), 0); + recog_dup_num[0] = 1; + recog_dup_loc[1] = &XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0), 0), 1); + recog_dup_num[1] = 2; + break; + + case 119: + case 116: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 1), 0)); + recog_dup_loc[0] = &XEXP (XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0), 0), 0), 0); + recog_dup_num[0] = 1; + recog_dup_loc[1] = &XEXP (XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0), 0), 1), 0); + recog_dup_num[1] = 2; + break; + + case 114: + case 111: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 113: + case 110: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + break; + + case 167: + case 164: + case 160: + case 157: + case 153: + case 150: + case 90: + case 87: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + recog_dup_loc[0] = &XEXP (XEXP (pat, 1), 1); + recog_dup_num[0] = 0; + break; + + case 228: + case 226: + case 223: + case 221: + case 218: + case 216: + case 211: + case 209: + case 204: + case 202: + case 197: + case 195: + case 166: + case 163: + case 159: + case 156: + case 152: + case 149: + case 102: + case 100: + case 89: + case 86: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1)); + recog_dup_loc[0] = &XEXP (XEXP (pat, 1), 0); + recog_dup_num[0] = 0; + break; + + case 98: + case 84: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + break; + + case 339: + case 337: + case 335: + case 333: + case 291: + case 290: + case 227: + case 225: + case 224: + case 222: + case 220: + case 219: + case 217: + case 215: + case 214: + case 213: + case 212: + case 210: + case 208: + case 207: + case 206: + case 205: + case 203: + case 201: + case 200: + case 199: + case 198: + case 196: + case 194: + case 193: + case 192: + case 191: + case 165: + case 162: + case 161: + case 158: + case 155: + case 154: + case 151: + case 148: + case 147: + case 142: + case 139: + case 138: + case 137: + case 135: + case 134: + case 130: + case 127: + case 126: + case 125: + case 123: + case 122: + case 112: + case 109: + case 108: + case 107: + case 105: + case 104: + case 101: + case 99: + case 97: + case 96: + case 95: + case 93: + case 92: + case 88: + case 85: + case 83: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 82: + case 81: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + break; + + case 72: + case 71: + case 70: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XVECEXP (pat, 0, 2), 0)); + break; + + case 342: + case 341: + case 340: + case 331: + case 330: + case 329: + case 328: + case 327: + case 326: + case 325: + case 324: + case 323: + case 322: + case 321: + case 189: + case 187: + case 186: + case 185: + case 184: + case 182: + case 181: + case 179: + case 178: + case 177: + case 175: + case 174: + case 171: + case 169: + case 168: + case 80: + case 79: + case 78: + case 77: + case 76: + case 75: + case 74: + case 73: + case 69: + case 68: + case 67: + case 66: + case 65: + case 64: + case 62: + case 61: + case 59: + case 58: + case 57: + case 55: + case 54: + case 52: + case 51: + case 50: + case 49: + case 48: + case 47: + case 43: + case 42: + case 41: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + break; + + case 33: + case 31: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (pat, 1)); + break; + + case 257: + case 256: + case 255: + case 254: + case 253: + case 252: + case 251: + case 250: + case 249: + case 248: + case 27: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + break; + + case 25: + case 24: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 2)); + break; + + case 23: + case 22: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XEXP (pat, 1), 2), 1), 0)); + break; + + case 21: + case 20: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 2), 1)); + break; + + case 18: + case 15: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 320: + case 19: + case 16: + case 13: + case 12: + case 11: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 9: + case 6: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 318: + case 297: + case 10: + case 7: + case 4: + case 3: + case 2: + ro[0] = *(ro_loc[0] = &XEXP (pat, 1)); + break; + + case 298: + case 288: + case 287: + case 40: + case 39: + case 38: + case 37: + case 35: + case 34: + case 32: + case 30: + case 29: + case 26: + case 1: + case 0: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (pat, 1)); + break; + + default: + abort (); + } +} diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-flags.h b/gnu/usr.bin/gcc2/arch/m68k/insn-flags.h new file mode 100644 index 000000000000..13cb48ec0612 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-flags.h @@ -0,0 +1,537 @@ +/* Generated automatically by the program `genflags' +from the machine description file `md'. */ + +#define HAVE_tstsi 1 +#define HAVE_tsthi 1 +#define HAVE_tstqi 1 +#define HAVE_tstsf (TARGET_68881 || TARGET_FPA) +#define HAVE_tstsf_fpa (TARGET_FPA) +#define HAVE_tstdf (TARGET_68881 || TARGET_FPA) +#define HAVE_tstdf_fpa (TARGET_FPA) +#define HAVE_cmpsi 1 +#define HAVE_cmphi 1 +#define HAVE_cmpqi 1 +#define HAVE_cmpdf (TARGET_68881 || TARGET_FPA) +#define HAVE_cmpdf_fpa (TARGET_FPA) +#define HAVE_cmpsf (TARGET_68881 || TARGET_FPA) +#define HAVE_cmpsf_fpa (TARGET_FPA) +#define HAVE_movsi 1 +#define HAVE_movhi 1 +#define HAVE_movstricthi 1 +#define HAVE_movqi 1 +#define HAVE_movstrictqi 1 +#define HAVE_movsf 1 +#define HAVE_movdf 1 +#define HAVE_movxf 1 +#define HAVE_movdi 1 +#define HAVE_pushasi 1 +#define HAVE_truncsiqi2 1 +#define HAVE_trunchiqi2 1 +#define HAVE_truncsihi2 1 +#define HAVE_zero_extendhisi2 1 +#define HAVE_zero_extendqihi2 1 +#define HAVE_zero_extendqisi2 1 +#define HAVE_extendhisi2 1 +#define HAVE_extendqihi2 1 +#define HAVE_extendqisi2 (TARGET_68020) +#define HAVE_extendsfdf2 (TARGET_68881 || TARGET_FPA) +#define HAVE_truncdfsf2 (TARGET_68881 || TARGET_FPA) +#define HAVE_floatsisf2 (TARGET_68881 || TARGET_FPA) +#define HAVE_floatsidf2 (TARGET_68881 || TARGET_FPA) +#define HAVE_floathisf2 (TARGET_68881) +#define HAVE_floathidf2 (TARGET_68881) +#define HAVE_floatqisf2 (TARGET_68881) +#define HAVE_floatqidf2 (TARGET_68881) +#define HAVE_fix_truncdfsi2 (TARGET_68040) +#define HAVE_fix_truncdfhi2 (TARGET_68040) +#define HAVE_fix_truncdfqi2 (TARGET_68040) +#define HAVE_ftruncdf2 (TARGET_68881 && !TARGET_68040) +#define HAVE_ftruncsf2 (TARGET_68881 && !TARGET_68040) +#define HAVE_fixsfqi2 (TARGET_68881) +#define HAVE_fixsfhi2 (TARGET_68881) +#define HAVE_fixsfsi2 (TARGET_68881) +#define HAVE_fixdfqi2 (TARGET_68881) +#define HAVE_fixdfhi2 (TARGET_68881) +#define HAVE_fixdfsi2 (TARGET_68881) +#define HAVE_addsi3 1 +#define HAVE_addhi3 1 +#define HAVE_addqi3 1 +#define HAVE_adddf3 (TARGET_68881 || TARGET_FPA) +#define HAVE_addsf3 (TARGET_68881 || TARGET_FPA) +#define HAVE_subsi3 1 +#define HAVE_subhi3 1 +#define HAVE_subqi3 1 +#define HAVE_subdf3 (TARGET_68881 || TARGET_FPA) +#define HAVE_subsf3 (TARGET_68881 || TARGET_FPA) +#define HAVE_mulhi3 1 +#define HAVE_mulhisi3 1 +#define HAVE_mulsi3 (TARGET_68020) +#define HAVE_umulhisi3 1 +#define HAVE_umulsidi3 (TARGET_68020) +#define HAVE_mulsidi3 (TARGET_68020) +#define HAVE_muldf3 (TARGET_68881 || TARGET_FPA) +#define HAVE_mulsf3 (TARGET_68881 || TARGET_FPA) +#define HAVE_divhi3 1 +#define HAVE_divhisi3 1 +#define HAVE_udivhi3 1 +#define HAVE_udivhisi3 1 +#define HAVE_divdf3 (TARGET_68881 || TARGET_FPA) +#define HAVE_divsf3 (TARGET_68881 || TARGET_FPA) +#define HAVE_modhi3 1 +#define HAVE_modhisi3 1 +#define HAVE_umodhi3 1 +#define HAVE_umodhisi3 1 +#define HAVE_divmodsi4 (TARGET_68020) +#define HAVE_udivmodsi4 (TARGET_68020) +#define HAVE_andsi3 1 +#define HAVE_andhi3 1 +#define HAVE_andqi3 1 +#define HAVE_iorsi3 1 +#define HAVE_iorhi3 1 +#define HAVE_iorqi3 1 +#define HAVE_xorsi3 1 +#define HAVE_xorhi3 1 +#define HAVE_xorqi3 1 +#define HAVE_negsi2 1 +#define HAVE_neghi2 1 +#define HAVE_negqi2 1 +#define HAVE_negsf2 (TARGET_68881 || TARGET_FPA) +#define HAVE_negdf2 (TARGET_68881 || TARGET_FPA) +#define HAVE_sqrtdf2 (TARGET_68881) +#define HAVE_abssf2 (TARGET_68881 || TARGET_FPA) +#define HAVE_absdf2 (TARGET_68881 || TARGET_FPA) +#define HAVE_one_cmplsi2 1 +#define HAVE_one_cmplhi2 1 +#define HAVE_one_cmplqi2 1 +#define HAVE_ashlsi3 1 +#define HAVE_ashlhi3 1 +#define HAVE_ashlqi3 1 +#define HAVE_ashrsi3 1 +#define HAVE_ashrhi3 1 +#define HAVE_ashrqi3 1 +#define HAVE_lshlsi3 1 +#define HAVE_lshlhi3 1 +#define HAVE_lshlqi3 1 +#define HAVE_lshrsi3 1 +#define HAVE_lshrhi3 1 +#define HAVE_lshrqi3 1 +#define HAVE_rotlsi3 1 +#define HAVE_rotlhi3 1 +#define HAVE_rotlqi3 1 +#define HAVE_rotrsi3 1 +#define HAVE_rotrhi3 1 +#define HAVE_rotrqi3 1 +#define HAVE_extv (TARGET_68020 && TARGET_BITFIELD) +#define HAVE_extzv (TARGET_68020 && TARGET_BITFIELD) +#define HAVE_insv (TARGET_68020 && TARGET_BITFIELD) +#define HAVE_seq 1 +#define HAVE_sne 1 +#define HAVE_sgt 1 +#define HAVE_sgtu 1 +#define HAVE_slt 1 +#define HAVE_sltu 1 +#define HAVE_sge 1 +#define HAVE_sgeu 1 +#define HAVE_sle 1 +#define HAVE_sleu 1 +#define HAVE_beq 1 +#define HAVE_bne 1 +#define HAVE_bgt 1 +#define HAVE_bgtu 1 +#define HAVE_blt 1 +#define HAVE_bltu 1 +#define HAVE_bge 1 +#define HAVE_bgeu 1 +#define HAVE_ble 1 +#define HAVE_bleu 1 +#define HAVE_jump 1 +#define HAVE_tablejump 1 +#define HAVE_decrement_and_branch_until_zero (find_reg_note (insn, REG_NONNEG, 0)) +#define HAVE_call 1 +#define HAVE_call_value 1 +#define HAVE_untyped_call (NEEDS_UNTYPED_CALL) +#define HAVE_blockage 1 +#define HAVE_nop 1 +#define HAVE_probe (NEED_PROBE) +#define HAVE_return (USE_RETURN_INSN) +#define HAVE_indirect_jump 1 +#define HAVE_tstxf (TARGET_68881) +#define HAVE_cmpxf (TARGET_68881) +#define HAVE_extendsfxf2 (TARGET_68881) +#define HAVE_extenddfxf2 (TARGET_68881) +#define HAVE_truncxfdf2 (TARGET_68881) +#define HAVE_truncxfsf2 (TARGET_68881) +#define HAVE_floatsixf2 (TARGET_68881) +#define HAVE_floathixf2 (TARGET_68881) +#define HAVE_floatqixf2 (TARGET_68881) +#define HAVE_ftruncxf2 (TARGET_68881) +#define HAVE_fixxfqi2 (TARGET_68881) +#define HAVE_fixxfhi2 (TARGET_68881) +#define HAVE_fixxfsi2 (TARGET_68881) +#define HAVE_addxf3 (TARGET_68881) +#define HAVE_subxf3 (TARGET_68881) +#define HAVE_mulxf3 (TARGET_68881) +#define HAVE_divxf3 (TARGET_68881) +#define HAVE_negxf2 (TARGET_68881) +#define HAVE_absxf2 (TARGET_68881) +#define HAVE_sqrtxf2 (TARGET_68881) + +#ifndef NO_MD_PROTOTYPES +extern rtx gen_tstsi PROTO((rtx)); +extern rtx gen_tsthi PROTO((rtx)); +extern rtx gen_tstqi PROTO((rtx)); +extern rtx gen_tstsf PROTO((rtx)); +extern rtx gen_tstsf_fpa PROTO((rtx)); +extern rtx gen_tstdf PROTO((rtx)); +extern rtx gen_tstdf_fpa PROTO((rtx)); +extern rtx gen_cmpsi PROTO((rtx, rtx)); +extern rtx gen_cmphi PROTO((rtx, rtx)); +extern rtx gen_cmpqi PROTO((rtx, rtx)); +extern rtx gen_cmpdf PROTO((rtx, rtx)); +extern rtx gen_cmpdf_fpa PROTO((rtx, rtx)); +extern rtx gen_cmpsf PROTO((rtx, rtx)); +extern rtx gen_cmpsf_fpa PROTO((rtx, rtx)); +extern rtx gen_movsi PROTO((rtx, rtx)); +extern rtx gen_movhi PROTO((rtx, rtx)); +extern rtx gen_movstricthi PROTO((rtx, rtx)); +extern rtx gen_movqi PROTO((rtx, rtx)); +extern rtx gen_movstrictqi PROTO((rtx, rtx)); +extern rtx gen_movsf PROTO((rtx, rtx)); +extern rtx gen_movdf PROTO((rtx, rtx)); +extern rtx gen_movxf PROTO((rtx, rtx)); +extern rtx gen_movdi PROTO((rtx, rtx)); +extern rtx gen_pushasi PROTO((rtx, rtx)); +extern rtx gen_truncsiqi2 PROTO((rtx, rtx)); +extern rtx gen_trunchiqi2 PROTO((rtx, rtx)); +extern rtx gen_truncsihi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendhisi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendqihi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendqisi2 PROTO((rtx, rtx)); +extern rtx gen_extendhisi2 PROTO((rtx, rtx)); +extern rtx gen_extendqihi2 PROTO((rtx, rtx)); +extern rtx gen_extendqisi2 PROTO((rtx, rtx)); +extern rtx gen_extendsfdf2 PROTO((rtx, rtx)); +extern rtx gen_truncdfsf2 PROTO((rtx, rtx)); +extern rtx gen_floatsisf2 PROTO((rtx, rtx)); +extern rtx gen_floatsidf2 PROTO((rtx, rtx)); +extern rtx gen_floathisf2 PROTO((rtx, rtx)); +extern rtx gen_floathidf2 PROTO((rtx, rtx)); +extern rtx gen_floatqisf2 PROTO((rtx, rtx)); +extern rtx gen_floatqidf2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncdfsi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncdfhi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncdfqi2 PROTO((rtx, rtx)); +extern rtx gen_ftruncdf2 PROTO((rtx, rtx)); +extern rtx gen_ftruncsf2 PROTO((rtx, rtx)); +extern rtx gen_fixsfqi2 PROTO((rtx, rtx)); +extern rtx gen_fixsfhi2 PROTO((rtx, rtx)); +extern rtx gen_fixsfsi2 PROTO((rtx, rtx)); +extern rtx gen_fixdfqi2 PROTO((rtx, rtx)); +extern rtx gen_fixdfhi2 PROTO((rtx, rtx)); +extern rtx gen_fixdfsi2 PROTO((rtx, rtx)); +extern rtx gen_addsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_adddf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subdf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulhisi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_umulhisi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_umulsidi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulsidi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_muldf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divhisi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_udivhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_udivhisi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divdf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_modhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_modhisi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_umodhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_umodhisi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divmodsi4 PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_udivmodsi4 PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_andsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_andhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_andqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_negsi2 PROTO((rtx, rtx)); +extern rtx gen_neghi2 PROTO((rtx, rtx)); +extern rtx gen_negqi2 PROTO((rtx, rtx)); +extern rtx gen_negsf2 PROTO((rtx, rtx)); +extern rtx gen_negdf2 PROTO((rtx, rtx)); +extern rtx gen_sqrtdf2 PROTO((rtx, rtx)); +extern rtx gen_abssf2 PROTO((rtx, rtx)); +extern rtx gen_absdf2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplsi2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplhi2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplqi2 PROTO((rtx, rtx)); +extern rtx gen_ashlsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashlhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashlqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshlsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshlhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshlqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_extv PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_extzv PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_insv PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_seq PROTO((rtx)); +extern rtx gen_sne PROTO((rtx)); +extern rtx gen_sgt PROTO((rtx)); +extern rtx gen_sgtu PROTO((rtx)); +extern rtx gen_slt PROTO((rtx)); +extern rtx gen_sltu PROTO((rtx)); +extern rtx gen_sge PROTO((rtx)); +extern rtx gen_sgeu PROTO((rtx)); +extern rtx gen_sle PROTO((rtx)); +extern rtx gen_sleu PROTO((rtx)); +extern rtx gen_beq PROTO((rtx)); +extern rtx gen_bne PROTO((rtx)); +extern rtx gen_bgt PROTO((rtx)); +extern rtx gen_bgtu PROTO((rtx)); +extern rtx gen_blt PROTO((rtx)); +extern rtx gen_bltu PROTO((rtx)); +extern rtx gen_bge PROTO((rtx)); +extern rtx gen_bgeu PROTO((rtx)); +extern rtx gen_ble PROTO((rtx)); +extern rtx gen_bleu PROTO((rtx)); +extern rtx gen_jump PROTO((rtx)); +extern rtx gen_tablejump PROTO((rtx, rtx)); +extern rtx gen_decrement_and_branch_until_zero PROTO((rtx, rtx)); +extern rtx gen_untyped_call PROTO((rtx, rtx, rtx)); +extern rtx gen_blockage PROTO((void)); +extern rtx gen_nop PROTO((void)); +extern rtx gen_probe PROTO((void)); +extern rtx gen_return PROTO((void)); +extern rtx gen_indirect_jump PROTO((rtx)); +extern rtx gen_tstxf PROTO((rtx)); +extern rtx gen_cmpxf PROTO((rtx, rtx)); +extern rtx gen_extendsfxf2 PROTO((rtx, rtx)); +extern rtx gen_extenddfxf2 PROTO((rtx, rtx)); +extern rtx gen_truncxfdf2 PROTO((rtx, rtx)); +extern rtx gen_truncxfsf2 PROTO((rtx, rtx)); +extern rtx gen_floatsixf2 PROTO((rtx, rtx)); +extern rtx gen_floathixf2 PROTO((rtx, rtx)); +extern rtx gen_floatqixf2 PROTO((rtx, rtx)); +extern rtx gen_ftruncxf2 PROTO((rtx, rtx)); +extern rtx gen_fixxfqi2 PROTO((rtx, rtx)); +extern rtx gen_fixxfhi2 PROTO((rtx, rtx)); +extern rtx gen_fixxfsi2 PROTO((rtx, rtx)); +extern rtx gen_addxf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subxf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulxf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divxf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_negxf2 PROTO((rtx, rtx)); +extern rtx gen_absxf2 PROTO((rtx, rtx)); +extern rtx gen_sqrtxf2 PROTO((rtx, rtx)); + +#ifdef MD_CALL_PROTOTYPES +extern rtx gen_call PROTO((rtx, rtx)); +extern rtx gen_call_value PROTO((rtx, rtx, rtx)); + +#else /* !MD_CALL_PROTOTYPES */ +extern rtx gen_call (); +extern rtx gen_call_value (); +#endif /* !MD_CALL_PROTOTYPES */ + +#else /* NO_MD_PROTOTYPES */ +extern rtx gen_tstsi (); +extern rtx gen_tsthi (); +extern rtx gen_tstqi (); +extern rtx gen_tstsf (); +extern rtx gen_tstsf_fpa (); +extern rtx gen_tstdf (); +extern rtx gen_tstdf_fpa (); +extern rtx gen_cmpsi (); +extern rtx gen_cmphi (); +extern rtx gen_cmpqi (); +extern rtx gen_cmpdf (); +extern rtx gen_cmpdf_fpa (); +extern rtx gen_cmpsf (); +extern rtx gen_cmpsf_fpa (); +extern rtx gen_movsi (); +extern rtx gen_movhi (); +extern rtx gen_movstricthi (); +extern rtx gen_movqi (); +extern rtx gen_movstrictqi (); +extern rtx gen_movsf (); +extern rtx gen_movdf (); +extern rtx gen_movxf (); +extern rtx gen_movdi (); +extern rtx gen_pushasi (); +extern rtx gen_truncsiqi2 (); +extern rtx gen_trunchiqi2 (); +extern rtx gen_truncsihi2 (); +extern rtx gen_zero_extendhisi2 (); +extern rtx gen_zero_extendqihi2 (); +extern rtx gen_zero_extendqisi2 (); +extern rtx gen_extendhisi2 (); +extern rtx gen_extendqihi2 (); +extern rtx gen_extendqisi2 (); +extern rtx gen_extendsfdf2 (); +extern rtx gen_truncdfsf2 (); +extern rtx gen_floatsisf2 (); +extern rtx gen_floatsidf2 (); +extern rtx gen_floathisf2 (); +extern rtx gen_floathidf2 (); +extern rtx gen_floatqisf2 (); +extern rtx gen_floatqidf2 (); +extern rtx gen_fix_truncdfsi2 (); +extern rtx gen_fix_truncdfhi2 (); +extern rtx gen_fix_truncdfqi2 (); +extern rtx gen_ftruncdf2 (); +extern rtx gen_ftruncsf2 (); +extern rtx gen_fixsfqi2 (); +extern rtx gen_fixsfhi2 (); +extern rtx gen_fixsfsi2 (); +extern rtx gen_fixdfqi2 (); +extern rtx gen_fixdfhi2 (); +extern rtx gen_fixdfsi2 (); +extern rtx gen_addsi3 (); +extern rtx gen_addhi3 (); +extern rtx gen_addqi3 (); +extern rtx gen_adddf3 (); +extern rtx gen_addsf3 (); +extern rtx gen_subsi3 (); +extern rtx gen_subhi3 (); +extern rtx gen_subqi3 (); +extern rtx gen_subdf3 (); +extern rtx gen_subsf3 (); +extern rtx gen_mulhi3 (); +extern rtx gen_mulhisi3 (); +extern rtx gen_mulsi3 (); +extern rtx gen_umulhisi3 (); +extern rtx gen_umulsidi3 (); +extern rtx gen_mulsidi3 (); +extern rtx gen_muldf3 (); +extern rtx gen_mulsf3 (); +extern rtx gen_divhi3 (); +extern rtx gen_divhisi3 (); +extern rtx gen_udivhi3 (); +extern rtx gen_udivhisi3 (); +extern rtx gen_divdf3 (); +extern rtx gen_divsf3 (); +extern rtx gen_modhi3 (); +extern rtx gen_modhisi3 (); +extern rtx gen_umodhi3 (); +extern rtx gen_umodhisi3 (); +extern rtx gen_divmodsi4 (); +extern rtx gen_udivmodsi4 (); +extern rtx gen_andsi3 (); +extern rtx gen_andhi3 (); +extern rtx gen_andqi3 (); +extern rtx gen_iorsi3 (); +extern rtx gen_iorhi3 (); +extern rtx gen_iorqi3 (); +extern rtx gen_xorsi3 (); +extern rtx gen_xorhi3 (); +extern rtx gen_xorqi3 (); +extern rtx gen_negsi2 (); +extern rtx gen_neghi2 (); +extern rtx gen_negqi2 (); +extern rtx gen_negsf2 (); +extern rtx gen_negdf2 (); +extern rtx gen_sqrtdf2 (); +extern rtx gen_abssf2 (); +extern rtx gen_absdf2 (); +extern rtx gen_one_cmplsi2 (); +extern rtx gen_one_cmplhi2 (); +extern rtx gen_one_cmplqi2 (); +extern rtx gen_ashlsi3 (); +extern rtx gen_ashlhi3 (); +extern rtx gen_ashlqi3 (); +extern rtx gen_ashrsi3 (); +extern rtx gen_ashrhi3 (); +extern rtx gen_ashrqi3 (); +extern rtx gen_lshlsi3 (); +extern rtx gen_lshlhi3 (); +extern rtx gen_lshlqi3 (); +extern rtx gen_lshrsi3 (); +extern rtx gen_lshrhi3 (); +extern rtx gen_lshrqi3 (); +extern rtx gen_rotlsi3 (); +extern rtx gen_rotlhi3 (); +extern rtx gen_rotlqi3 (); +extern rtx gen_rotrsi3 (); +extern rtx gen_rotrhi3 (); +extern rtx gen_rotrqi3 (); +extern rtx gen_extv (); +extern rtx gen_extzv (); +extern rtx gen_insv (); +extern rtx gen_seq (); +extern rtx gen_sne (); +extern rtx gen_sgt (); +extern rtx gen_sgtu (); +extern rtx gen_slt (); +extern rtx gen_sltu (); +extern rtx gen_sge (); +extern rtx gen_sgeu (); +extern rtx gen_sle (); +extern rtx gen_sleu (); +extern rtx gen_beq (); +extern rtx gen_bne (); +extern rtx gen_bgt (); +extern rtx gen_bgtu (); +extern rtx gen_blt (); +extern rtx gen_bltu (); +extern rtx gen_bge (); +extern rtx gen_bgeu (); +extern rtx gen_ble (); +extern rtx gen_bleu (); +extern rtx gen_jump (); +extern rtx gen_tablejump (); +extern rtx gen_decrement_and_branch_until_zero (); +extern rtx gen_untyped_call (); +extern rtx gen_blockage (); +extern rtx gen_nop (); +extern rtx gen_probe (); +extern rtx gen_return (); +extern rtx gen_indirect_jump (); +extern rtx gen_tstxf (); +extern rtx gen_cmpxf (); +extern rtx gen_extendsfxf2 (); +extern rtx gen_extenddfxf2 (); +extern rtx gen_truncxfdf2 (); +extern rtx gen_truncxfsf2 (); +extern rtx gen_floatsixf2 (); +extern rtx gen_floathixf2 (); +extern rtx gen_floatqixf2 (); +extern rtx gen_ftruncxf2 (); +extern rtx gen_fixxfqi2 (); +extern rtx gen_fixxfhi2 (); +extern rtx gen_fixxfsi2 (); +extern rtx gen_addxf3 (); +extern rtx gen_subxf3 (); +extern rtx gen_mulxf3 (); +extern rtx gen_divxf3 (); +extern rtx gen_negxf2 (); +extern rtx gen_absxf2 (); +extern rtx gen_sqrtxf2 (); +extern rtx gen_call (); +extern rtx gen_call_value (); +#endif /* NO_MD_PROTOTYPES */ diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-opinit.c b/gnu/usr.bin/gcc2/arch/m68k/insn-opinit.c new file mode 100644 index 000000000000..83f29384a2aa --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-opinit.c @@ -0,0 +1,221 @@ +/* Generated automatically by the program `genopinit' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "flags.h" +#include "insn-flags.h" +#include "insn-codes.h" +#include "insn-config.h" +#include "recog.h" +#include "expr.h" +#include "reload.h" + +void +init_all_optabs () +{ + tst_optab->handlers[(int) SImode].insn_code = CODE_FOR_tstsi; + tst_optab->handlers[(int) HImode].insn_code = CODE_FOR_tsthi; + tst_optab->handlers[(int) QImode].insn_code = CODE_FOR_tstqi; + if (HAVE_tstsf) + tst_optab->handlers[(int) SFmode].insn_code = CODE_FOR_tstsf; + if (HAVE_tstdf) + tst_optab->handlers[(int) DFmode].insn_code = CODE_FOR_tstdf; + cmp_optab->handlers[(int) SImode].insn_code = CODE_FOR_cmpsi; + cmp_optab->handlers[(int) HImode].insn_code = CODE_FOR_cmphi; + cmp_optab->handlers[(int) QImode].insn_code = CODE_FOR_cmpqi; + if (HAVE_cmpdf) + cmp_optab->handlers[(int) DFmode].insn_code = CODE_FOR_cmpdf; + if (HAVE_cmpsf) + cmp_optab->handlers[(int) SFmode].insn_code = CODE_FOR_cmpsf; + mov_optab->handlers[(int) SImode].insn_code = CODE_FOR_movsi; + mov_optab->handlers[(int) HImode].insn_code = CODE_FOR_movhi; + movstrict_optab->handlers[(int) HImode].insn_code = CODE_FOR_movstricthi; + mov_optab->handlers[(int) QImode].insn_code = CODE_FOR_movqi; + movstrict_optab->handlers[(int) QImode].insn_code = CODE_FOR_movstrictqi; + mov_optab->handlers[(int) SFmode].insn_code = CODE_FOR_movsf; + mov_optab->handlers[(int) DFmode].insn_code = CODE_FOR_movdf; + mov_optab->handlers[(int) XFmode].insn_code = CODE_FOR_movxf; + mov_optab->handlers[(int) DImode].insn_code = CODE_FOR_movdi; + extendtab[(int) SImode][(int) HImode][1] = CODE_FOR_zero_extendhisi2; + extendtab[(int) HImode][(int) QImode][1] = CODE_FOR_zero_extendqihi2; + extendtab[(int) SImode][(int) QImode][1] = CODE_FOR_zero_extendqisi2; + extendtab[(int) SImode][(int) HImode][0] = CODE_FOR_extendhisi2; + extendtab[(int) HImode][(int) QImode][0] = CODE_FOR_extendqihi2; + if (HAVE_extendqisi2) + extendtab[(int) SImode][(int) QImode][0] = CODE_FOR_extendqisi2; + if (HAVE_extendsfdf2) + extendtab[(int) DFmode][(int) SFmode][0] = CODE_FOR_extendsfdf2; + if (HAVE_floatsisf2) + floattab[(int) SFmode][(int) SImode][0] = CODE_FOR_floatsisf2; + if (HAVE_floatsidf2) + floattab[(int) DFmode][(int) SImode][0] = CODE_FOR_floatsidf2; + if (HAVE_floathisf2) + floattab[(int) SFmode][(int) HImode][0] = CODE_FOR_floathisf2; + if (HAVE_floathidf2) + floattab[(int) DFmode][(int) HImode][0] = CODE_FOR_floathidf2; + if (HAVE_floatqisf2) + floattab[(int) SFmode][(int) QImode][0] = CODE_FOR_floatqisf2; + if (HAVE_floatqidf2) + floattab[(int) DFmode][(int) QImode][0] = CODE_FOR_floatqidf2; + if (HAVE_fix_truncdfsi2) + fixtrunctab[(int) DFmode][(int) SImode][0] = CODE_FOR_fix_truncdfsi2; + if (HAVE_fix_truncdfhi2) + fixtrunctab[(int) DFmode][(int) HImode][0] = CODE_FOR_fix_truncdfhi2; + if (HAVE_fix_truncdfqi2) + fixtrunctab[(int) DFmode][(int) QImode][0] = CODE_FOR_fix_truncdfqi2; + if (HAVE_ftruncdf2) + ftrunc_optab->handlers[(int) DFmode].insn_code = CODE_FOR_ftruncdf2; + if (HAVE_ftruncsf2) + ftrunc_optab->handlers[(int) SFmode].insn_code = CODE_FOR_ftruncsf2; + if (HAVE_fixsfqi2) + fixtab[(int) SFmode][(int) QImode][0] = CODE_FOR_fixsfqi2; + if (HAVE_fixsfhi2) + fixtab[(int) SFmode][(int) HImode][0] = CODE_FOR_fixsfhi2; + if (HAVE_fixsfsi2) + fixtab[(int) SFmode][(int) SImode][0] = CODE_FOR_fixsfsi2; + if (HAVE_fixdfqi2) + fixtab[(int) DFmode][(int) QImode][0] = CODE_FOR_fixdfqi2; + if (HAVE_fixdfhi2) + fixtab[(int) DFmode][(int) HImode][0] = CODE_FOR_fixdfhi2; + if (HAVE_fixdfsi2) + fixtab[(int) DFmode][(int) SImode][0] = CODE_FOR_fixdfsi2; + add_optab->handlers[(int) SImode].insn_code = CODE_FOR_addsi3; + add_optab->handlers[(int) HImode].insn_code = CODE_FOR_addhi3; + add_optab->handlers[(int) QImode].insn_code = CODE_FOR_addqi3; + if (HAVE_adddf3) + add_optab->handlers[(int) DFmode].insn_code = CODE_FOR_adddf3; + if (HAVE_addsf3) + add_optab->handlers[(int) SFmode].insn_code = CODE_FOR_addsf3; + sub_optab->handlers[(int) SImode].insn_code = CODE_FOR_subsi3; + sub_optab->handlers[(int) HImode].insn_code = CODE_FOR_subhi3; + sub_optab->handlers[(int) QImode].insn_code = CODE_FOR_subqi3; + if (HAVE_subdf3) + sub_optab->handlers[(int) DFmode].insn_code = CODE_FOR_subdf3; + if (HAVE_subsf3) + sub_optab->handlers[(int) SFmode].insn_code = CODE_FOR_subsf3; + smul_optab->handlers[(int) HImode].insn_code = CODE_FOR_mulhi3; + smul_widen_optab->handlers[(int) SImode].insn_code = CODE_FOR_mulhisi3; + if (HAVE_mulsi3) + smul_optab->handlers[(int) SImode].insn_code = CODE_FOR_mulsi3; + umul_widen_optab->handlers[(int) SImode].insn_code = CODE_FOR_umulhisi3; + if (HAVE_umulsidi3) + umul_widen_optab->handlers[(int) DImode].insn_code = CODE_FOR_umulsidi3; + if (HAVE_mulsidi3) + smul_widen_optab->handlers[(int) DImode].insn_code = CODE_FOR_mulsidi3; + if (HAVE_muldf3) + smul_optab->handlers[(int) DFmode].insn_code = CODE_FOR_muldf3; + if (HAVE_mulsf3) + smul_optab->handlers[(int) SFmode].insn_code = CODE_FOR_mulsf3; + sdiv_optab->handlers[(int) HImode].insn_code = CODE_FOR_divhi3; + udiv_optab->handlers[(int) HImode].insn_code = CODE_FOR_udivhi3; + if (HAVE_divdf3) + flodiv_optab->handlers[(int) DFmode].insn_code = CODE_FOR_divdf3; + if (HAVE_divsf3) + flodiv_optab->handlers[(int) SFmode].insn_code = CODE_FOR_divsf3; + smod_optab->handlers[(int) HImode].insn_code = CODE_FOR_modhi3; + umod_optab->handlers[(int) HImode].insn_code = CODE_FOR_umodhi3; + if (HAVE_divmodsi4) + sdivmod_optab->handlers[(int) SImode].insn_code = CODE_FOR_divmodsi4; + if (HAVE_udivmodsi4) + udivmod_optab->handlers[(int) SImode].insn_code = CODE_FOR_udivmodsi4; + and_optab->handlers[(int) SImode].insn_code = CODE_FOR_andsi3; + and_optab->handlers[(int) HImode].insn_code = CODE_FOR_andhi3; + and_optab->handlers[(int) QImode].insn_code = CODE_FOR_andqi3; + ior_optab->handlers[(int) SImode].insn_code = CODE_FOR_iorsi3; + ior_optab->handlers[(int) HImode].insn_code = CODE_FOR_iorhi3; + ior_optab->handlers[(int) QImode].insn_code = CODE_FOR_iorqi3; + xor_optab->handlers[(int) SImode].insn_code = CODE_FOR_xorsi3; + xor_optab->handlers[(int) HImode].insn_code = CODE_FOR_xorhi3; + xor_optab->handlers[(int) QImode].insn_code = CODE_FOR_xorqi3; + neg_optab->handlers[(int) SImode].insn_code = CODE_FOR_negsi2; + neg_optab->handlers[(int) HImode].insn_code = CODE_FOR_neghi2; + neg_optab->handlers[(int) QImode].insn_code = CODE_FOR_negqi2; + if (HAVE_negsf2) + neg_optab->handlers[(int) SFmode].insn_code = CODE_FOR_negsf2; + if (HAVE_negdf2) + neg_optab->handlers[(int) DFmode].insn_code = CODE_FOR_negdf2; + if (HAVE_sqrtdf2) + sqrt_optab->handlers[(int) DFmode].insn_code = CODE_FOR_sqrtdf2; + if (HAVE_abssf2) + abs_optab->handlers[(int) SFmode].insn_code = CODE_FOR_abssf2; + if (HAVE_absdf2) + abs_optab->handlers[(int) DFmode].insn_code = CODE_FOR_absdf2; + one_cmpl_optab->handlers[(int) SImode].insn_code = CODE_FOR_one_cmplsi2; + one_cmpl_optab->handlers[(int) HImode].insn_code = CODE_FOR_one_cmplhi2; + one_cmpl_optab->handlers[(int) QImode].insn_code = CODE_FOR_one_cmplqi2; + ashl_optab->handlers[(int) SImode].insn_code = CODE_FOR_ashlsi3; + ashl_optab->handlers[(int) HImode].insn_code = CODE_FOR_ashlhi3; + ashl_optab->handlers[(int) QImode].insn_code = CODE_FOR_ashlqi3; + ashr_optab->handlers[(int) SImode].insn_code = CODE_FOR_ashrsi3; + ashr_optab->handlers[(int) HImode].insn_code = CODE_FOR_ashrhi3; + ashr_optab->handlers[(int) QImode].insn_code = CODE_FOR_ashrqi3; + lshl_optab->handlers[(int) SImode].insn_code = CODE_FOR_lshlsi3; + lshl_optab->handlers[(int) HImode].insn_code = CODE_FOR_lshlhi3; + lshl_optab->handlers[(int) QImode].insn_code = CODE_FOR_lshlqi3; + lshr_optab->handlers[(int) SImode].insn_code = CODE_FOR_lshrsi3; + lshr_optab->handlers[(int) HImode].insn_code = CODE_FOR_lshrhi3; + lshr_optab->handlers[(int) QImode].insn_code = CODE_FOR_lshrqi3; + rotl_optab->handlers[(int) SImode].insn_code = CODE_FOR_rotlsi3; + rotl_optab->handlers[(int) HImode].insn_code = CODE_FOR_rotlhi3; + rotl_optab->handlers[(int) QImode].insn_code = CODE_FOR_rotlqi3; + rotr_optab->handlers[(int) SImode].insn_code = CODE_FOR_rotrsi3; + rotr_optab->handlers[(int) HImode].insn_code = CODE_FOR_rotrhi3; + rotr_optab->handlers[(int) QImode].insn_code = CODE_FOR_rotrqi3; + setcc_gen_code[(int) EQ] = CODE_FOR_seq; + setcc_gen_code[(int) NE] = CODE_FOR_sne; + setcc_gen_code[(int) GT] = CODE_FOR_sgt; + setcc_gen_code[(int) GTU] = CODE_FOR_sgtu; + setcc_gen_code[(int) LT] = CODE_FOR_slt; + setcc_gen_code[(int) LTU] = CODE_FOR_sltu; + setcc_gen_code[(int) GE] = CODE_FOR_sge; + setcc_gen_code[(int) GEU] = CODE_FOR_sgeu; + setcc_gen_code[(int) LE] = CODE_FOR_sle; + setcc_gen_code[(int) LEU] = CODE_FOR_sleu; + bcc_gen_fctn[(int) EQ] = gen_beq; + bcc_gen_fctn[(int) NE] = gen_bne; + bcc_gen_fctn[(int) GT] = gen_bgt; + bcc_gen_fctn[(int) GTU] = gen_bgtu; + bcc_gen_fctn[(int) LT] = gen_blt; + bcc_gen_fctn[(int) LTU] = gen_bltu; + bcc_gen_fctn[(int) GE] = gen_bge; + bcc_gen_fctn[(int) GEU] = gen_bgeu; + bcc_gen_fctn[(int) LE] = gen_ble; + bcc_gen_fctn[(int) LEU] = gen_bleu; + if (HAVE_tstxf) + tst_optab->handlers[(int) XFmode].insn_code = CODE_FOR_tstxf; + if (HAVE_cmpxf) + cmp_optab->handlers[(int) XFmode].insn_code = CODE_FOR_cmpxf; + if (HAVE_extendsfxf2) + extendtab[(int) XFmode][(int) SFmode][0] = CODE_FOR_extendsfxf2; + if (HAVE_extenddfxf2) + extendtab[(int) XFmode][(int) DFmode][0] = CODE_FOR_extenddfxf2; + if (HAVE_floatsixf2) + floattab[(int) XFmode][(int) SImode][0] = CODE_FOR_floatsixf2; + if (HAVE_floathixf2) + floattab[(int) XFmode][(int) HImode][0] = CODE_FOR_floathixf2; + if (HAVE_floatqixf2) + floattab[(int) XFmode][(int) QImode][0] = CODE_FOR_floatqixf2; + if (HAVE_ftruncxf2) + ftrunc_optab->handlers[(int) XFmode].insn_code = CODE_FOR_ftruncxf2; + if (HAVE_fixxfqi2) + fixtab[(int) XFmode][(int) QImode][0] = CODE_FOR_fixxfqi2; + if (HAVE_fixxfhi2) + fixtab[(int) XFmode][(int) HImode][0] = CODE_FOR_fixxfhi2; + if (HAVE_fixxfsi2) + fixtab[(int) XFmode][(int) SImode][0] = CODE_FOR_fixxfsi2; + if (HAVE_addxf3) + add_optab->handlers[(int) XFmode].insn_code = CODE_FOR_addxf3; + if (HAVE_subxf3) + sub_optab->handlers[(int) XFmode].insn_code = CODE_FOR_subxf3; + if (HAVE_mulxf3) + smul_optab->handlers[(int) XFmode].insn_code = CODE_FOR_mulxf3; + if (HAVE_divxf3) + flodiv_optab->handlers[(int) XFmode].insn_code = CODE_FOR_divxf3; + if (HAVE_negxf2) + neg_optab->handlers[(int) XFmode].insn_code = CODE_FOR_negxf2; + if (HAVE_absxf2) + abs_optab->handlers[(int) XFmode].insn_code = CODE_FOR_absxf2; + if (HAVE_sqrtxf2) + sqrt_optab->handlers[(int) XFmode].insn_code = CODE_FOR_sqrtxf2; +} diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-output.c b/gnu/usr.bin/gcc2/arch/m68k/insn-output.c new file mode 100644 index 000000000000..84070236fff6 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-output.c @@ -0,0 +1,7826 @@ +/* Generated automatically by the program `genoutput' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" + +#include "conditions.h" +#include "insn-flags.h" +#include "insn-attr.h" + +#include "insn-codes.h" + +#include "recog.h" + +#include +#include "output.h" + +static char * +output_0 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[1])) + return "fmove%.d %f1,%0"; + if (FPA_REG_P (operands[1])) + return "fpmove%.d %1, %x0"; + return output_move_double (operands); +} +} + +static char * +output_1 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + return output_move_double (operands); +} +} + +static char * +output_2 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef ISI_OV + /* ISI's assembler fails to handle tstl a0. */ + if (! ADDRESS_REG_P (operands[0])) +#else + if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) +#endif + return "tst%.l %0"; + /* If you think that the 68020 does not support tstl a0, + reread page B-167 of the 68020 manual more carefully. */ + /* On an address reg, cmpw may replace cmpl. */ +#ifdef SGS_CMP_ORDER + return "cmp%.w %0,%#0"; +#else + return "cmp%.w %#0,%0"; +#endif +} +} + +static char * +output_7 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags = CC_IN_68881; + if (FP_REG_P (operands[0])) + return "ftst%.x %0"; + return "ftst%.s %0"; +} +} + +static char * +output_10 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags = CC_IN_68881; + if (FP_REG_P (operands[0])) + return "ftst%.x %0"; + return "ftst%.d %0"; +} +} + +static char * +output_11 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + return "cmpm%.l %1,%0"; + if (REG_P (operands[1]) + || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) + { cc_status.flags |= CC_REVERSED; +#ifdef SGS_CMP_ORDER + return "cmp%.l %d1,%d0"; +#else + return "cmp%.l %d0,%d1"; +#endif + } +#ifdef SGS_CMP_ORDER + return "cmp%.l %d0,%d1"; +#else + return "cmp%.l %d1,%d0"; +#endif +} +} + +static char * +output_12 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + return "cmpm%.w %1,%0"; + if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1])) + || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) + { cc_status.flags |= CC_REVERSED; +#ifdef SGS_CMP_ORDER + return "cmp%.w %d1,%d0"; +#else + return "cmp%.w %d0,%d1"; +#endif + } +#ifdef SGS_CMP_ORDER + return "cmp%.w %d0,%d1"; +#else + return "cmp%.w %d1,%d0"; +#endif +} +} + +static char * +output_13 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + return "cmpm%.b %1,%0"; + if (REG_P (operands[1]) + || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) + { cc_status.flags |= CC_REVERSED; +#ifdef SGS_CMP_ORDER + return "cmp%.b %d1,%d0"; +#else + return "cmp%.b %d0,%d1"; +#endif + } +#ifdef SGS_CMP_ORDER + return "cmp%.b %d0,%d1"; +#else + return "cmp%.b %d1,%d0"; +#endif +} +} + +static char * +output_16 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags = CC_IN_68881; +#ifdef SGS_CMP_ORDER + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return "fcmp%.x %0,%1"; + else + return "fcmp%.d %0,%f1"; + } + cc_status.flags |= CC_REVERSED; + return "fcmp%.d %1,%f0"; +#else + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return "fcmp%.x %1,%0"; + else + return "fcmp%.d %f1,%0"; + } + cc_status.flags |= CC_REVERSED; + return "fcmp%.d %f0,%1"; +#endif +} +} + +static char * +output_19 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags = CC_IN_68881; +#ifdef SGS_CMP_ORDER + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return "fcmp%.x %0,%1"; + else + return "fcmp%.s %0,%f1"; + } + cc_status.flags |= CC_REVERSED; + return "fcmp%.s %1,%f0"; +#else + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return "fcmp%.x %1,%0"; + else + return "fcmp%.s %f1,%0"; + } + cc_status.flags |= CC_REVERSED; + return "fcmp%.s %f0,%1"; +#endif +} +} + +static char * +output_20 (operands, insn) + rtx *operands; + rtx insn; +{ + { return output_btst (operands, operands[1], operands[0], insn, 7); } +} + +static char * +output_21 (operands, insn) + rtx *operands; + rtx insn; +{ + { return output_btst (operands, operands[1], operands[0], insn, 31); } +} + +static char * +output_22 (operands, insn) + rtx *operands; + rtx insn; +{ + { return output_btst (operands, operands[1], operands[0], insn, 7); } +} + +static char * +output_23 (operands, insn) + rtx *operands; + rtx insn; +{ + { return output_btst (operands, operands[1], operands[0], insn, 31); } +} + +static char * +output_24 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1])); + return output_btst (operands, operands[1], operands[0], insn, 7); +} +} + +static char * +output_25 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == MEM) + { + operands[0] = adj_offsettable_operand (operands[0], + INTVAL (operands[1]) / 8); + operands[1] = gen_rtx (CONST_INT, VOIDmode, + 7 - INTVAL (operands[1]) % 8); + return output_btst (operands, operands[1], operands[0], insn, 7); + } + operands[1] = gen_rtx (CONST_INT, VOIDmode, + 31 - INTVAL (operands[1])); + return output_btst (operands, operands[1], operands[0], insn, 31); +} +} + +static char * +output_26 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (operands[1] == const0_rtx) + return "clr%.l %0"; + return "pea %a1"; +} +} + +static char * +output_27 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (ADDRESS_REG_P (operands[0])) + return "sub%.l %0,%0"; + /* moveq is faster on the 68000. */ + if (DATA_REG_P (operands[0]) && !TARGET_68020) +#if defined(MOTOROLA) && !defined(CRDS) + return "moveq%.l %#0,%0"; +#else + return "moveq %#0,%0"; +#endif + return "clr%.l %0"; +} +} + +static char * +output_29 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (which_alternative == 3) + return "fpmove%.l %x1,fpa0\n\tfpmove%.l fpa0,%x0"; + if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0])) + return "fpmove%.l %x1,%x0"; + if (GET_CODE (operands[1]) == CONST_INT) + { + if (operands[1] == const0_rtx + && (DATA_REG_P (operands[0]) + || GET_CODE (operands[0]) == MEM) + /* clr insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + && (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM + && MEM_VOLATILE_P (operands[0])))) + return "clr%.l %0"; + else if (DATA_REG_P (operands[0]) + && INTVAL (operands[1]) < 128 + && INTVAL (operands[1]) >= -128) + { +#if defined(MOTOROLA) && !defined(CRDS) + return "moveq%.l %1,%0"; +#else + return "moveq %1,%0"; +#endif + } +#ifndef NO_ADDSUB_Q + else if (DATA_REG_P (operands[0]) + /* Do this with a moveq #N-8, dreg; addq #8,dreg */ + && INTVAL (operands[1]) < 136 + && INTVAL (operands[1]) >= 128) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); +#if defined(MOTOROLA) && !defined(CRDS) + return "moveq%.l %1,%0\n\taddq%.w %#8,%0"; +#else + return "moveq %1,%0\n\taddq%.w %#8,%0"; +#endif + } + else if (DATA_REG_P (operands[0]) + /* Do this with a moveq #N+8, dreg; subq #8,dreg */ + && INTVAL (operands[1]) < -128 + && INTVAL (operands[1]) >= -136) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 8); +#if defined(MOTOROLA) && !defined(CRDS) + return "moveq%.l %1,%0;subq%.w %#8,%0"; +#else + return "moveq %1,%0;subq%.w %#8,%0"; +#endif + } +#endif + else if (DATA_REG_P (operands[0]) + /* If N is in the right range and is even, then use + moveq #N/2, dreg; addl dreg,dreg */ + && INTVAL (operands[1]) > 127 + && INTVAL (operands[1]) <= 254 + && INTVAL (operands[1]) % 2 == 0) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) / 2); +#if defined(MOTOROLA) && !defined(CRDS) + return "moveq%.l %1,%0\n\tadd%.w %0,%0"; +#else + return "moveq %1,%0\n\tadd%.w %0,%0"; +#endif + } + else if (ADDRESS_REG_P (operands[0]) + && INTVAL (operands[1]) < 0x8000 + && INTVAL (operands[1]) >= -0x8000) + return "move%.w %1,%0"; + else if (push_operand (operands[0], SImode) + && INTVAL (operands[1]) < 0x8000 + && INTVAL (operands[1]) >= -0x8000) + return "pea %a1"; + } + else if ((GET_CODE (operands[1]) == SYMBOL_REF + || GET_CODE (operands[1]) == CONST) + && push_operand (operands[0], SImode)) + return "pea %a1"; + else if ((GET_CODE (operands[1]) == SYMBOL_REF + || GET_CODE (operands[1]) == CONST) + && ADDRESS_REG_P (operands[0])) + return "lea %a1,%0"; + return "move%.l %1,%0"; +} +} + +static char * +output_30 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + if (operands[1] == const0_rtx + && (DATA_REG_P (operands[0]) + || GET_CODE (operands[0]) == MEM) + /* clr insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + && (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM + && MEM_VOLATILE_P (operands[0])))) + return "clr%.w %0"; + else if (DATA_REG_P (operands[0]) + && INTVAL (operands[1]) < 128 + && INTVAL (operands[1]) >= -128) + { +#if defined(MOTOROLA) && !defined(CRDS) + return "moveq%.l %1,%0"; +#else + return "moveq %1,%0"; +#endif + } + else if (INTVAL (operands[1]) < 0x8000 + && INTVAL (operands[1]) >= -0x8000) + return "move%.w %1,%0"; + } + else if (CONSTANT_P (operands[1])) + return "move%.l %1,%0"; +#ifndef SGS_NO_LI + /* Recognize the insn before a tablejump, one that refers + to a table of offsets. Such an insn will need to refer + to a label on the insn. So output one. Use the label-number + of the table of offsets to generate this label. */ + if (GET_CODE (operands[1]) == MEM + && GET_CODE (XEXP (operands[1], 0)) == PLUS + && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF + || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF) + && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS + && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS) + { + rtx labelref; + if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF) + labelref = XEXP (XEXP (operands[1], 0), 0); + else + labelref = XEXP (XEXP (operands[1], 0), 1); +#if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES) +#ifdef SGS + asm_fprintf (asm_out_file, "\tset %LLI%d,.+2\n", + CODE_LABEL_NUMBER (XEXP (labelref, 0))); +#else /* not SGS */ + asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n", + CODE_LABEL_NUMBER (XEXP (labelref, 0))); +#endif /* not SGS */ +#else /* SGS_SWITCH_TABLES or not MOTOROLA */ + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LI", + CODE_LABEL_NUMBER (XEXP (labelref, 0))); +#ifdef SGS_SWITCH_TABLES + /* Set flag saying we need to define the symbol + LD%n (with value L%n-LI%n) at the end of the switch table. */ + switch_table_difference_label_flag = 1; +#endif /* SGS_SWITCH_TABLES */ +#endif /* SGS_SWITCH_TABLES or not MOTOROLA */ + } +#endif /* SGS_NO_LI */ + return "move%.w %1,%0"; +} +} + +static char * +output_31 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + if (operands[1] == const0_rtx + && (DATA_REG_P (operands[0]) + || GET_CODE (operands[0]) == MEM) + /* clr insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + && (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM + && MEM_VOLATILE_P (operands[0])))) + return "clr%.w %0"; + } + return "move%.w %1,%0"; +} +} + +static char * +output_32 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xoperands[4]; + + /* This is probably useless, since it loses for pushing a struct + of several bytes a byte at a time. */ + if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC + && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx) + { + xoperands[1] = operands[1]; + xoperands[2] + = gen_rtx (MEM, QImode, + gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx)); + /* Just pushing a byte puts it in the high byte of the halfword. */ + /* We must put it in the low-order, high-numbered byte. */ + output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands); + return ""; + } + + /* Moving a byte into an address register is not possible. */ + /* Use d0 as an intermediate, but don't clobber its contents. */ + if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM) + { + /* ??? For 2.5, don't allow this choice and use secondary reloads + instead. + + See if the address register is used in the address. If it + is, we have to generate a more complex sequence than those below. */ + if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, + operands[1], NULL_RTX)) + { + /* See if the stack pointer is used in the address. If it isn't, + we can push d0 or d1 (the insn can't use both of them) on + the stack, perform our move into d0/d1, copy the byte from d0/1, + and pop d0/1. */ + if (! reg_mentioned_p (stack_pointer_rtx, operands[1])) + { + if (refers_to_regno_p (0, 1, operands[1], NULL_RTX)) + return "move%.l %/d0,%-\n\tmove%.b %1,%/d0\n\tmove%.l %/d0,%0\n\tmove%.l %+,%/d0"; + else + return "move%.l %/d1,%-\n\tmove%.b %1,%/d1\n\tmove%.l %/d1,%0\n\tmove%.l %+,%/d1"; + } + else + { + /* Otherwise, we know that d0 cannot be used in the address + (since sp and one address register is). Assume that sp is + being used as a base register and replace the address + register that is our operand[0] with d0. */ + rtx reg_map[FIRST_PSEUDO_REGISTER]; + int i; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + reg_map[i] = 0; + + reg_map[REGNO (operands[0])] = gen_rtx (REG, Pmode, 0); + operands[1] = copy_rtx (operands[1]); + replace_regs (operands[1], reg_map, FIRST_PSEUDO_REGISTER, 0); + return "exg %/d0,%0\n\tmove%.b %1,%/d0\n\texg %/d0,%0"; + } + } + + /* If the address of operand 1 uses d0, choose d1 as intermediate. */ + if (refers_to_regno_p (0, 1, operands[1], NULL_RTX)) + return "exg %/d1,%0\n\tmove%.b %1,%/d1\n\texg %/d1,%0"; + /* Otherwise d0 is usable. + (An effective address on the 68k can't use two d-regs.) */ + else + return "exg %/d0,%0\n\tmove%.b %1,%/d0\n\texg %/d0,%0"; + } + + /* Likewise for moving from an address reg. */ + if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM) + { + /* ??? For 2.5, don't allow this choice and use secondary reloads + instead. + + See if the address register is used in the address. If it + is, we have to generate a more complex sequence than those below. */ + if (refers_to_regno_p (REGNO (operands[1]), REGNO (operands[1]) + 1, + operands[0], NULL_RTX)) + { + /* See if the stack pointer is used in the address. If it isn't, + we can push d0 or d1 (the insn can't use both of them) on + the stack, copy the byte to d0/1, perform our move from d0/d1, + and pop d0/1. */ + if (! reg_mentioned_p (stack_pointer_rtx, operands[0])) + { + if (refers_to_regno_p (0, 1, operands[0], NULL_RTX)) + return "move%.l %/d0,%-\n\tmove%.l %1,%/d0\n\tmove%.b %/d0,%0\n\tmove%.l %+,%/d0"; + else + return "move%.l %/d1,%-\n\tmove%.l %1,%/d1\n\tmove%.b %/d1,%0\n\tmove%.l %+,%/d1"; + } + else + { + /* Otherwise, we know that d0 cannot be used in the address + (since sp and one address register is). Assume that sp is + being used as a base register and replace the address + register that is our operand[1] with d0. */ + rtx reg_map[FIRST_PSEUDO_REGISTER]; + int i; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + reg_map[i] = 0; + + reg_map[REGNO (operands[1])] = gen_rtx (REG, Pmode, 0); + operands[0] = copy_rtx (operands[0]); + replace_regs (operands[0], reg_map, FIRST_PSEUDO_REGISTER, 0); + return "exg %/d0,%1\n\tmove%.b %/d0,%0\n\texg %/d0,%1"; + } + } + + if (refers_to_regno_p (0, 1, operands[0], NULL_RTX)) + return "exg %/d1,%1\n\tmove%.b %/d1,%0\n\texg %/d1,%1"; + else + return "exg %/d0,%1\n\tmove%.b %/d0,%0\n\texg %/d0,%1"; + } + + /* clr and st insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + if (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if (operands[1] == const0_rtx) + return "clr%.b %0"; + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) == -1) + { + CC_STATUS_INIT; + return "st %0"; + } + } + if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) + return "move%.l %1,%0"; + if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) + return "move%.w %1,%0"; + return "move%.b %1,%0"; +} +} + +static char * +output_33 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (operands[1] == const0_rtx + /* clr insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + && (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) + return "clr%.b %0"; + return "move%.b %1,%0"; +} +} + +static char * +output_34 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (which_alternative >= 4) + return "fpmove%.s %1,fpa0\n\tfpmove%.s fpa0,%0"; + if (FPA_REG_P (operands[0])) + { + if (FPA_REG_P (operands[1])) + return "fpmove%.s %x1,%x0"; + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_single (operands); + else if (FP_REG_P (operands[1])) + return "fmove%.s %1,sp@-\n\tfpmove%.d sp@+, %0"; + return "fpmove%.s %x1,%x0"; + } + if (FPA_REG_P (operands[1])) + { + if (FP_REG_P (operands[0])) + return "fpmove%.s %x1,sp@-\n\tfmove%.s sp@+,%0"; + else + return "fpmove%.s %x1,%x0"; + } + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return "f%$move%.x %1,%0"; + else if (ADDRESS_REG_P (operands[1])) + return "move%.l %1,%-\n\tf%$move%.s %+,%0"; + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_single (operands); + return "f%$move%.s %f1,%0"; + } + if (FP_REG_P (operands[1])) + { + if (ADDRESS_REG_P (operands[0])) + return "fmove%.s %1,%-\n\tmove%.l %+,%0"; + return "fmove%.s %f1,%0"; + } + return "move%.l %1,%0"; +} +} + +static char * +output_35 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (which_alternative == 6) + return "fpmove%.d %x1,fpa0\n\tfpmove%.d fpa0,%x0"; + if (FPA_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_double (operands); + if (FP_REG_P (operands[1])) + return "fmove%.d %1,sp@-\n\tfpmove%.d sp@+,%x0"; + return "fpmove%.d %x1,%x0"; + } + else if (FPA_REG_P (operands[1])) + { + if (FP_REG_P(operands[0])) + return "fpmove%.d %x1,sp@-\n\tfmoved sp@+,%0"; + else + return "fpmove%.d %x1,%x0"; + } + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return "f%&move%.x %1,%0"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn ("move%.l %1,%-", xoperands); + output_asm_insn ("move%.l %1,%-", operands); + return "f%&move%.d %+,%0"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_double (operands); + return "f%&move%.d %f1,%0"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + { + output_asm_insn ("fmove%.d %f1,%-\n\tmove%.l %+,%0", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return "move%.l %+,%0"; + } + else + return "fmove%.d %f1,%0"; + } + return output_move_double (operands); +} + +} + +static char * +output_37 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return "fmove%.x %1,%0"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); + output_asm_insn ("move%.l %1,%-", xoperands); + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn ("move%.l %1,%-", xoperands); + output_asm_insn ("move%.l %1,%-", operands); + return "fmove%.x %+,%0"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return "fmove%.x %1,%0"; + return "fmove%.x %f1,%0"; + } + if (REG_P (operands[0])) + { + output_asm_insn ("fmove%.x %f1,%-\n\tmove%.l %+,%0", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + output_asm_insn ("move%.l %+,%0", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return "move%.l %+,%0"; + } + return "fmove%.x %f1,%0"; +} + +} + +static char * +output_38 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return "fmove%.x %1,%0"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); + output_asm_insn ("move%.l %1,%-", xoperands); + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn ("move%.l %1,%-", xoperands); + output_asm_insn ("move%.l %1,%-", operands); + return "fmove%.x %+,%0"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return "fmove%.x %1,%0"; + return "fmove%.x %f1,%0"; + } + if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + { + output_asm_insn ("fmove%.x %f1,%-\n\tmove%.l %+,%0", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + output_asm_insn ("move%.l %+,%0", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return "move%.l %+,%0"; + } + else + return "fmove%.x %f1,%0"; + } + return output_move_double (operands); +} + +} + +static char * +output_39 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (which_alternative == 8) + return "fpmove%.d %x1,fpa0\n\tfpmove%.d fpa0,%x0"; + if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1])) + return "fpmove%.d %x1,%x0"; + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return "fmove%.x %1,%0"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn ("move%.l %1,%-", xoperands); + output_asm_insn ("move%.l %1,%-", operands); + return "fmove%.d %+,%0"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_double (operands); + return "fmove%.d %f1,%0"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + { + output_asm_insn ("fmove%.d %f1,%-\n\tmove%.l %+,%0", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return "move%.l %+,%0"; + } + else + return "fmove%.d %f1,%0"; + } + return output_move_double (operands); +} + +} + +static char * +output_41 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == REG) + { + /* Must clear condition codes, since the move.l bases them on + the entire 32 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return "move%.l %1,%0"; + } + if (GET_CODE (operands[1]) == MEM) + operands[1] = adj_offsettable_operand (operands[1], 3); + return "move%.b %1,%0"; +} +} + +static char * +output_42 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == REG + && (GET_CODE (operands[1]) == MEM + || GET_CODE (operands[1]) == CONST_INT)) + { + /* Must clear condition codes, since the move.w bases them on + the entire 16 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return "move%.w %1,%0"; + } + if (GET_CODE (operands[0]) == REG) + { + /* Must clear condition codes, since the move.l bases them on + the entire 32 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return "move%.l %1,%0"; + } + if (GET_CODE (operands[1]) == MEM) + operands[1] = adj_offsettable_operand (operands[1], 1); + return "move%.b %1,%0"; +} +} + +static char * +output_43 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) == REG) + { + /* Must clear condition codes, since the move.l bases them on + the entire 32 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return "move%.l %1,%0"; + } + if (GET_CODE (operands[1]) == MEM) + operands[1] = adj_offsettable_operand (operands[1], 2); + return "move%.w %1,%0"; +} +} + +static char * +output_47 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (DATA_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG + && REGNO (operands[0]) == REGNO (operands[1])) + return "and%.l %#0xFFFF,%0"; + if (reg_mentioned_p (operands[0], operands[1])) + return "move%.w %1,%0\n\tand%.l %#0xFFFF,%0"; + return "clr%.l %0\n\tmove%.w %1,%0"; + } + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + return "move%.w %1,%0\n\tclr%.w %0"; + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == POST_INC) + return "clr%.w %0\n\tmove%.w %1,%0"; + else + { + output_asm_insn ("clr%.w %0", operands); + operands[0] = adj_offsettable_operand (operands[0], 2); + return "move%.w %1,%0"; + } +} +} + +static char * +output_48 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (DATA_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG + && REGNO (operands[0]) == REGNO (operands[1])) + return "and%.w %#0xFF,%0"; + if (reg_mentioned_p (operands[0], operands[1])) + return "move%.b %1,%0\n\tand%.w %#0xFF,%0"; + return "clr%.w %0\n\tmove%.b %1,%0"; + } + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + { + if (REGNO (XEXP (XEXP (operands[0], 0), 0)) + == STACK_POINTER_REGNUM) + { + output_asm_insn ("clr%.w %-", operands); + operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), + plus_constant (stack_pointer_rtx, 1)); + return "move%.b %1,%0"; + } + else + return "move%.b %1,%0\n\tclr%.b %0"; + } + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == POST_INC) + return "clr%.b %0\n\tmove%.b %1,%0"; + else + { + output_asm_insn ("clr%.b %0", operands); + operands[0] = adj_offsettable_operand (operands[0], 1); + return "move%.b %1,%0"; + } +} +} + +static char * +output_49 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (DATA_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG + && REGNO (operands[0]) == REGNO (operands[1])) + return "and%.l %#0xFF,%0"; + if (reg_mentioned_p (operands[0], operands[1])) + return "move%.b %1,%0\n\tand%.l %#0xFF,%0"; + return "clr%.l %0\n\tmove%.b %1,%0"; + } + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + { + operands[0] = XEXP (XEXP (operands[0], 0), 0); +#ifdef MOTOROLA +#ifdef SGS + return "clr%.l -(%0)\n\tmove%.b %1,3(%0)"; +#else + return "clr%.l -(%0)\n\tmove%.b %1,(3,%0)"; +#endif +#else + return "clrl %0@-\n\tmoveb %1,%0@(3)"; +#endif + } + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == POST_INC) + { + operands[0] = XEXP (XEXP (operands[0], 0), 0); +#ifdef MOTOROLA +#ifdef SGS + return "clr%.l (%0)+\n\tmove%.b %1,-1(%0)"; +#else + return "clr%.l (%0)+\n\tmove%.b %1,(-1,%0)"; +#endif +#else + return "clrl %0@+\n\tmoveb %1,%0@(-1)"; +#endif + } + else + { + output_asm_insn ("clr%.l %0", operands); + operands[0] = adj_offsettable_operand (operands[0], 3); + return "move%.b %1,%0"; + } +} +} + +static char * +output_50 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (ADDRESS_REG_P (operands[0])) + return "move%.w %1,%0"; + return "ext%.l %0"; +} +} + +static char * +output_55 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) + { + if (REGNO (operands[0]) == REGNO (operands[1])) + { + /* Extending float to double in an fp-reg is a no-op. + NOTICE_UPDATE_CC has already assumed that the + cc will be set. So cancel what it did. */ + cc_status = cc_prev_status; + return ""; + } + return "f%&move%.x %1,%0"; + } + if (FP_REG_P (operands[0])) + return "f%&move%.s %f1,%0"; + if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1])) + { + output_asm_insn ("fmove%.d %f1,%-\n\tmove%.l %+,%0", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return "move%.l %+,%0"; + } + return "fmove%.d %f1,%0"; +} +} + +static char * +output_58 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[1])) + return "f%$move%.x %1,%0"; + return "f%$move%.d %f1,%0"; +} +} + +static char * +output_70 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "fmovem%.l %!,%2\n\tmoveq %#16,%3\n\tor%.l %2,%3\n\tand%.w %#-33,%3\n\tfmovem%.l %3,%!\n\tfmove%.l %1,%0\n\tfmovem%.l %2,%!"; +} +} + +static char * +output_71 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "fmovem%.l %!,%2\n\tmoveq %#16,%3\n\tor%.l %2,%3\n\tand%.w %#-33,%3\n\tfmovem%.l %3,%!\n\tfmove%.w %1,%0\n\tfmovem%.l %2,%!"; +} +} + +static char * +output_72 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "fmovem%.l %!,%2\n\tmoveq %#16,%3\n\tor%.l %2,%3\n\tand%.w %#-33,%3\n\tfmovem%.l %3,%!\n\tfmove%.b %1,%0\n\tfmovem%.l %2,%!"; +} +} + +static char * +output_73 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[1])) + return "fintrz%.x %f1,%0"; + return "fintrz%.d %f1,%0"; +} +} + +static char * +output_74 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[1])) + return "fintrz%.x %f1,%0"; + return "fintrz%.s %f1,%0"; +} +} + +static char * +output_83 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (! operands_match_p (operands[0], operands[1])) + { + if (!ADDRESS_REG_P (operands[1])) + { + rtx tmp = operands[1]; + + operands[1] = operands[2]; + operands[2] = tmp; + } + + /* These insns can result from reloads to access + stack slots over 64k from the frame pointer. */ + if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000) + return "move%.l %2,%0\n\tadd%.l %1,%0"; +#ifdef SGS + if (GET_CODE (operands[2]) == REG) + return "lea 0(%1,%2.l),%0"; + else + return "lea %c2(%1),%0"; +#else /* not SGS */ +#ifdef MOTOROLA + if (GET_CODE (operands[2]) == REG) + return "lea (%1,%2.l),%0"; + else + return "lea (%c2,%1),%0"; +#else /* not MOTOROLA (MIT syntax) */ + if (GET_CODE (operands[2]) == REG) + return "lea %1@(0,%2:l),%0"; + else + return "lea %1@(%c2),%0"; +#endif /* not MOTOROLA */ +#endif /* not SGS */ + } + if (GET_CODE (operands[2]) == CONST_INT) + { +#ifndef NO_ADDSUB_Q + if (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) <= 8) + return (ADDRESS_REG_P (operands[0]) + ? "addq%.w %2,%0" + : "addq%.l %2,%0"); + if (INTVAL (operands[2]) < 0 + && INTVAL (operands[2]) >= -8) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[2])); + return (ADDRESS_REG_P (operands[0]) + ? "subq%.w %2,%0" + : "subq%.l %2,%0"); + } + /* On everything except the 68000 it is faster to use two + addqw instructions to add a small integer (8 < N <= 16) + to an address register. Likewise for subqw.*/ + if (INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); + return "addq%.w %#8,%0\n\taddq%.w %2,%0"; + } + if (INTVAL (operands[2]) < -8 + && INTVAL (operands[2]) >= -16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[2]) - 8); + return "subq%.w %#8,%0\n\tsubq%.w %2,%0"; + } +#endif + if (ADDRESS_REG_P (operands[0]) + && INTVAL (operands[2]) >= -0x8000 + && INTVAL (operands[2]) < 0x8000) + return "add%.w %2,%0"; + } + return "add%.l %2,%0"; +} +} + +static char * +output_85 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[2]) == CONST_INT) + { + /* If the constant would be a negative number when interpreted as + HImode, make it negative. This is usually, but not always, done + elsewhere in the compiler. First check for constants out of range, + which could confuse us. */ + + if (INTVAL (operands[2]) >= 32768) + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) - 65536); + + if (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) <= 8) + return "addq%.w %2,%0"; + if (INTVAL (operands[2]) < 0 + && INTVAL (operands[2]) >= -8) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[2])); + return "subq%.w %2,%0"; + } + /* On everything except the 68000 it is faster to use two + addqw instructions to add a small integer (8 < N <= 16) + to an address register. Likewise for subqw. */ + if (INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); + return "addq%.w %#8,%0\n\taddq%.w %2,%0"; + } + if (INTVAL (operands[2]) < -8 + && INTVAL (operands[2]) >= -16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[2]) - 8); + return "subq%.w %#8,%0\n\tsubq%.w %2,%0"; + } + } +#endif + return "add%.w %2,%0"; +} +} + +static char * +output_86 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[1]) == CONST_INT) + { + /* If the constant would be a negative number when interpreted as + HImode, make it negative. This is usually, but not always, done + elsewhere in the compiler. First check for constants out of range, + which could confuse us. */ + + if (INTVAL (operands[1]) >= 32768) + operands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[1]) - 65536); + + if (INTVAL (operands[1]) > 0 + && INTVAL (operands[1]) <= 8) + return "addq%.w %1,%0"; + if (INTVAL (operands[1]) < 0 + && INTVAL (operands[1]) >= -8) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[1])); + return "subq%.w %1,%0"; + } + /* On everything except the 68000 it is faster to use two + addqw instructions to add a small integer (8 < N <= 16) + to an address register. Likewise for subqw. */ + if (INTVAL (operands[1]) > 8 + && INTVAL (operands[1]) <= 16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); + return "addq%.w %#8,%0\n\taddq%.w %1,%0"; + } + if (INTVAL (operands[1]) < -8 + && INTVAL (operands[1]) >= -16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[1]) - 8); + return "subq%.w %#8,%0\n\tsubq%.w %1,%0"; + } + } +#endif + return "add%.w %1,%0"; +} +} + +static char * +output_87 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[1]) == CONST_INT) + { + /* If the constant would be a negative number when interpreted as + HImode, make it negative. This is usually, but not always, done + elsewhere in the compiler. First check for constants out of range, + which could confuse us. */ + + if (INTVAL (operands[1]) >= 32768) + operands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[1]) - 65536); + + if (INTVAL (operands[1]) > 0 + && INTVAL (operands[1]) <= 8) + return "addq%.w %1,%0"; + if (INTVAL (operands[1]) < 0 + && INTVAL (operands[1]) >= -8) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[1])); + return "subq%.w %1,%0"; + } + /* On everything except the 68000 it is faster to use two + addqw instructions to add a small integer (8 < N <= 16) + to an address register. Likewise for subqw. */ + if (INTVAL (operands[1]) > 8 + && INTVAL (operands[1]) <= 16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); + return "addq%.w %#8,%0\n\taddq%.w %1,%0"; + } + if (INTVAL (operands[1]) < -8 + && INTVAL (operands[1]) >= -16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[1]) - 8); + return "subq%.w %#8,%0\n\tsubq%.w %1,%0"; + } + } +#endif + return "add%.w %1,%0"; +} +} + +static char * +output_88 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) >= 128) + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) - 256); + + if (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) <= 8) + return "addq%.b %2,%0"; + if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); + return "subq%.b %2,%0"; + } + } +#endif + return "add%.b %2,%0"; +} +} + +static char * +output_89 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[1]) == CONST_INT) + { + if (INTVAL (operands[1]) >= 128) + operands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[1]) - 256); + + if (INTVAL (operands[1]) > 0 + && INTVAL (operands[1]) <= 8) + return "addq%.b %1,%0"; + if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); + return "subq%.b %1,%0"; + } + } +#endif + return "add%.b %1,%0"; +} +} + +static char * +output_90 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[1]) == CONST_INT) + { + if (INTVAL (operands[1]) >= 128) + operands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[1]) - 256); + + if (INTVAL (operands[1]) > 0 + && INTVAL (operands[1]) <= 8) + return "addq%.b %1,%0"; + if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); + return "subq%.b %1,%0"; + } + } +#endif + return "add%.b %1,%0"; +} +} + +static char * +output_92 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (rtx_equal_p (operands[0], operands[1])) + return "fpadd%.d %y2,%0"; + if (rtx_equal_p (operands[0], operands[2])) + return "fpadd%.d %y1,%0"; + if (which_alternative == 0) + return "fpadd3%.d %w2,%w1,%0"; + return "fpadd3%.d %x2,%x1,%0"; +} +} + +static char * +output_93 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return "f%&add%.x %2,%0"; + return "f%&add%.d %f2,%0"; +} +} + +static char * +output_95 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (rtx_equal_p (operands[0], operands[1])) + return "fpadd%.s %w2,%0"; + if (rtx_equal_p (operands[0], operands[2])) + return "fpadd%.s %w1,%0"; + if (which_alternative == 0) + return "fpadd3%.s %w2,%w1,%0"; + return "fpadd3%.s %2,%1,%0"; +} +} + +static char * +output_96 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return "f%$add%.x %2,%0"; + return "f%$add%.s %f2,%0"; +} +} + +static char * +output_97 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (! operands_match_p (operands[0], operands[1])) + { + if (operands_match_p (operands[0], operands[2])) + { +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[1]) == CONST_INT) + { + if (INTVAL (operands[1]) > 0 + && INTVAL (operands[1]) <= 8) + return "subq%.l %1,%0\n\tneg%.l %0"; + } +#endif + return "sub%.l %1,%0\n\tneg%.l %0"; + } + /* This case is matched by J, but negating -0x8000 + in an lea would give an invalid displacement. + So do this specially. */ + if (INTVAL (operands[2]) == -0x8000) + return "move%.l %1,%0\n\tsub%.l %2,%0"; +#ifdef SGS + return "lea %n2(%1),%0"; +#else +#ifdef MOTOROLA + return "lea (%n2,%1),%0"; +#else /* not MOTOROLA (MIT syntax) */ + return "lea %1@(%n2),%0"; +#endif /* not MOTOROLA */ +#endif /* not SGS */ + } + if (GET_CODE (operands[2]) == CONST_INT) + { +#ifndef NO_ADDSUB_Q + if (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) <= 8) + return "subq%.l %2,%0"; + /* Using two subqw for 8 < N <= 16 being subtracted from an + address register is faster on all but 68000 */ + if (INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); + return "subq%.w %#8,%0\n\tsubq%.w %2,%0"; + } +#endif + if (ADDRESS_REG_P (operands[0]) + && INTVAL (operands[2]) >= -0x8000 + && INTVAL (operands[2]) < 0x8000) + return "sub%.w %2,%0"; + } + return "sub%.l %2,%0"; +} +} + +static char * +output_104 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (rtx_equal_p (operands[0], operands[2])) + return "fprsub%.d %y1,%0"; + if (rtx_equal_p (operands[0], operands[1])) + return "fpsub%.d %y2,%0"; + if (which_alternative == 0) + return "fpsub3%.d %w2,%w1,%0"; + return "fpsub3%.d %x2,%x1,%0"; +} +} + +static char * +output_105 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return "f%&sub%.x %2,%0"; + return "f%&sub%.d %f2,%0"; +} +} + +static char * +output_107 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (rtx_equal_p (operands[0], operands[2])) + return "fprsub%.s %w1,%0"; + if (rtx_equal_p (operands[0], operands[1])) + return "fpsub%.s %w2,%0"; + if (which_alternative == 0) + return "fpsub3%.s %w2,%w1,%0"; + return "fpsub3%.s %2,%1,%0"; +} +} + +static char * +output_108 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return "f%$sub%.x %2,%0"; + return "f%$sub%.s %f2,%0"; +} +} + +static char * +output_109 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#if defined(MOTOROLA) && !defined(CRDS) + return "muls%.w %2,%0"; +#else + return "muls %2,%0"; +#endif +} +} + +static char * +output_110 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#if defined(MOTOROLA) && !defined(CRDS) + return "muls%.w %2,%0"; +#else + return "muls %2,%0"; +#endif +} +} + +static char * +output_111 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#if defined(MOTOROLA) && !defined(CRDS) + return "muls%.w %2,%0"; +#else + return "muls %2,%0"; +#endif +} +} + +static char * +output_113 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#if defined(MOTOROLA) && !defined(CRDS) + return "mulu%.w %2,%0"; +#else + return "mulu %2,%0"; +#endif +} +} + +static char * +output_114 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#if defined(MOTOROLA) && !defined(CRDS) + return "mulu%.w %2,%0"; +#else + return "mulu %2,%0"; +#endif +} +} + +static char * +output_122 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (rtx_equal_p (operands[1], operands[2])) + return "fpsqr%.d %y1,%0"; + if (rtx_equal_p (operands[0], operands[1])) + return "fpmul%.d %y2,%0"; + if (rtx_equal_p (operands[0], operands[2])) + return "fpmul%.d %y1,%0"; + if (which_alternative == 0) + return "fpmul3%.d %w2,%w1,%0"; + return "fpmul3%.d %x2,%x1,%0"; +} +} + +static char * +output_123 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_DOUBLE + && floating_exact_log2 (operands[2]) && !TARGET_68040) + { + int i = floating_exact_log2 (operands[2]); + operands[2] = gen_rtx (CONST_INT, VOIDmode, i); + return "fscale%.l %2,%0"; + } + if (REG_P (operands[2])) + return "f%&mul%.x %2,%0"; + return "f%&mul%.d %f2,%0"; +} +} + +static char * +output_125 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (rtx_equal_p (operands[1], operands[2])) + return "fpsqr%.s %w1,%0"; + if (rtx_equal_p (operands[0], operands[1])) + return "fpmul%.s %w2,%0"; + if (rtx_equal_p (operands[0], operands[2])) + return "fpmul%.s %w1,%0"; + if (which_alternative == 0) + return "fpmul3%.s %w2,%w1,%0"; + return "fpmul3%.s %2,%1,%0"; +} +} + +static char * +output_126 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef FSGLMUL_USE_S + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return (TARGET_68040_ONLY + ? "fsmul%.s %2,%0" + : "fsglmul%.s %2,%0"); +#else + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return (TARGET_68040_ONLY + ? "fsmul%.x %2,%0" + : "fsglmul%.x %2,%0"); +#endif + return (TARGET_68040_ONLY + ? "fsmul%.s %f2,%0" + : "fsglmul%.s %f2,%0"); +} +} + +static char * +output_127 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef MOTOROLA + return "ext%.l %0\n\tdivs%.w %2,%0"; +#else + return "extl %0\n\tdivs %2,%0"; +#endif +} +} + +static char * +output_128 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef MOTOROLA + return "divs%.w %2,%0"; +#else + return "divs %2,%0"; +#endif +} +} + +static char * +output_129 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef MOTOROLA + return "divs%.w %2,%0"; +#else + return "divs %2,%0"; +#endif +} +} + +static char * +output_130 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef MOTOROLA + return "and%.l %#0xFFFF,%0\n\tdivu%.w %2,%0"; +#else + return "andl %#0xFFFF,%0\n\tdivu %2,%0"; +#endif +} +} + +static char * +output_131 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef MOTOROLA + return "divu%.w %2,%0"; +#else + return "divu %2,%0"; +#endif +} +} + +static char * +output_132 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef MOTOROLA + return "divu%.w %2,%0"; +#else + return "divu %2,%0"; +#endif +} +} + +static char * +output_134 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (rtx_equal_p (operands[0], operands[2])) + return "fprdiv%.d %y1,%0"; + if (rtx_equal_p (operands[0], operands[1])) + return "fpdiv%.d %y2,%0"; + if (which_alternative == 0) + return "fpdiv3%.d %w2,%w1,%0"; + return "fpdiv3%.d %x2,%x1,%x0"; +} +} + +static char * +output_135 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return "f%&div%.x %2,%0"; + return "f%&div%.d %f2,%0"; +} +} + +static char * +output_137 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (rtx_equal_p (operands[0], operands[1])) + return "fpdiv%.s %w2,%0"; + if (rtx_equal_p (operands[0], operands[2])) + return "fprdiv%.s %w1,%0"; + if (which_alternative == 0) + return "fpdiv3%.s %w2,%w1,%0"; + return "fpdiv3%.s %2,%1,%0"; +} +} + +static char * +output_138 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef FSGLDIV_USE_S + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return (TARGET_68040_ONLY + ? "fsdiv%.s %2,%0" + : "fsgldiv%.s %2,%0"); +#else + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return (TARGET_68040_ONLY + ? "fsdiv%.x %2,%0" + : "fsgldiv%.x %2,%0"); +#endif + return (TARGET_68040_ONLY + ? "fsdiv%.s %f2,%0" + : "fsgldiv%.s %f2,%0"); +} +} + +static char * +output_139 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return "ext%.l %0\n\tdivs%.w %2,%0\n\tswap %0"; +#else + return "extl %0\n\tdivs %2,%0\n\tswap %0"; +#endif +} +} + +static char * +output_140 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return "divs%.w %2,%0\n\tswap %0"; +#else + return "divs %2,%0\n\tswap %0"; +#endif +} +} + +static char * +output_141 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return "divs%.w %2,%0\n\tswap %0"; +#else + return "divs %2,%0\n\tswap %0"; +#endif +} +} + +static char * +output_142 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return "and%.l %#0xFFFF,%0\n\tdivu%.w %2,%0\n\tswap %0"; +#else + return "andl %#0xFFFF,%0\n\tdivu %2,%0\n\tswap %0"; +#endif +} +} + +static char * +output_143 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return "divu%.w %2,%0\n\tswap %0"; +#else + return "divu %2,%0\n\tswap %0"; +#endif +} +} + +static char * +output_144 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return "divu%.w %2,%0\n\tswap %0"; +#else + return "divu %2,%0\n\tswap %0"; +#endif +} +} + +static char * +output_145 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (find_reg_note (insn, REG_UNUSED, operands[3])) + return "divs%.l %2,%0"; + else + return "divsl%.l %2,%3:%0"; +} +} + +static char * +output_146 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (find_reg_note (insn, REG_UNUSED, operands[3])) + return "divu%.l %2,%0"; + else + return "divul%.l %2,%3:%0"; +} +} + +static char * +output_147 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + int logval; + if (GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) | 0xffff) == 0xffffffff + && (DATA_REG_P (operands[0]) + || offsettable_memref_p (operands[0]))) + { + if (GET_CODE (operands[0]) != REG) + operands[0] = adj_offsettable_operand (operands[0], 2); + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) & 0xffff); + /* Do not delete a following tstl %0 insn; that would be incorrect. */ + CC_STATUS_INIT; + if (operands[2] == const0_rtx) + return "clr%.w %0"; + return "and%.w %2,%0"; + } + if (GET_CODE (operands[2]) == CONST_INT + && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 + && (DATA_REG_P (operands[0]) + || offsettable_memref_p (operands[0]))) + { + if (DATA_REG_P (operands[0])) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); + } + else + { + operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); + } + /* This does not set condition codes in a standard way. */ + CC_STATUS_INIT; + return "bclr %1,%0"; + } + return "and%.l %2,%0"; +} +} + +static char * +output_154 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + register int logval; + if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) >> 16 == 0 + && (DATA_REG_P (operands[0]) + || offsettable_memref_p (operands[0]))) + { + if (GET_CODE (operands[0]) != REG) + operands[0] = adj_offsettable_operand (operands[0], 2); + /* Do not delete a following tstl %0 insn; that would be incorrect. */ + CC_STATUS_INIT; + return "or%.w %2,%0"; + } + if (GET_CODE (operands[2]) == CONST_INT + && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 + && (DATA_REG_P (operands[0]) + || offsettable_memref_p (operands[0]))) + { + if (DATA_REG_P (operands[0])) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); + } + else + { + operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); + operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); + } + CC_STATUS_INIT; + return "bset %1,%0"; + } + return "or%.l %2,%0"; +} +} + +static char * +output_161 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) >> 16 == 0 + && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))) + { + if (! DATA_REG_P (operands[0])) + operands[0] = adj_offsettable_operand (operands[0], 2); + /* Do not delete a following tstl %0 insn; that would be incorrect. */ + CC_STATUS_INIT; + return "eor%.w %2,%0"; + } + return "eor%.l %2,%0"; +} +} + +static char * +output_175 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (DATA_REG_P (operands[0])) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, 31); + return "bchg %1,%0"; + } + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return "f%$neg%.x %1,%0"; + return "f%$neg%.s %f1,%0"; +} +} + +static char * +output_178 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (DATA_REG_P (operands[0])) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, 31); + return "bchg %1,%0"; + } + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return "f%&neg%.x %1,%0"; + return "f%&neg%.d %f1,%0"; +} +} + +static char * +output_179 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[1])) + return "fsqrt%.x %1,%0"; + else + return "fsqrt%.d %1,%0"; +} +} + +static char * +output_182 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return "f%$abs%.x %1,%0"; + return "f%$abs%.s %f1,%0"; +} +} + +static char * +output_185 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return "f%&abs%.x %1,%0"; + return "f%&abs%.d %f1,%0"; +} +} + +static char * +output_191 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "swap %0\n\tclr%.w %0"; +} +} + +static char * +output_192 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); + return "asl%.w %2,%0\n\tswap %0\n\tclr%.w %0"; +} +} + +static char * +output_193 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (operands[2] == const1_rtx) + return "add%.l %0,%0"; + return "asl%.l %2,%0"; +} +} + +static char * +output_199 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); + return "swap %0\n\tasr%.w %2,%0\n\text%.l %0"; +} +} + +static char * +output_200 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + return "asr%.l %2,%0"; +} +} + +static char * +output_205 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "swap %0\n\tclr%.w %0"; +} +} + +static char * +output_206 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); + return "lsl%.w %2,%0\n\tswap %0\n\tclr%.w %0"; +} +} + +static char * +output_207 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (operands[2] == const1_rtx) + return "add%.l %0,%0"; + return "lsl%.l %2,%0"; +} +} + +static char * +output_212 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "clr%.w %0\n\tswap %0"; +} +} + +static char * +output_213 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + /* I think lsr%.w sets the CC properly. */ + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); + return "clr%.w %0\n\tswap %0\n\tlsr%.w %2,%0"; +} +} + +static char * +output_214 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + return "lsr%.l %2,%0"; +} +} + +static char * +output_229 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[0] + = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); + + return "move%.l %3,%0"; +} +} + +static char * +output_230 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0])) + { + if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32) + return "bfins %3,%0{%b2:%b1}"; + } + else + operands[0] + = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); + + if (GET_CODE (operands[3]) == MEM) + operands[3] = adj_offsettable_operand (operands[3], + (32 - INTVAL (operands[1])) / 8); + if (INTVAL (operands[1]) == 8) + return "move%.b %3,%0"; + return "move%.w %3,%0"; +} +} + +static char * +output_231 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[1] + = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); + + return "move%.l %1,%0"; +} +} + +static char * +output_232 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags |= CC_NOT_NEGATIVE; + if (REG_P (operands[1])) + { + if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) + return "bfextu %1{%b3:%b2},%0"; + } + else + operands[1] + = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); + + output_asm_insn ("clr%.l %0", operands); + if (GET_CODE (operands[0]) == MEM) + operands[0] = adj_offsettable_operand (operands[0], + (32 - INTVAL (operands[1])) / 8); + if (INTVAL (operands[2]) == 8) + return "move%.b %1,%0"; + return "move%.w %1,%0"; +} +} + +static char * +output_233 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[1] + = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); + + return "move%.l %1,%0"; +} +} + +static char * +output_234 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[1])) + { + if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) + return "bfexts %1{%b3:%b2},%0"; + } + else + operands[1] + = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); + + if (INTVAL (operands[2]) == 8) + return "move%.b %1,%0\n\textb%.l %0"; + return "move%.w %1,%0\n\text%.l %0"; +} +} + +static char * +output_236 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags |= CC_NOT_NEGATIVE; + return "bfextu %1{%b3:%b2},%0"; +} +} + +static char * +output_237 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "bfchg %0{%b2:%b1}"; +} +} + +static char * +output_238 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "bfclr %0{%b2:%b1}"; +} +} + +static char * +output_239 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "bfset %0{%b2:%b1}"; +} +} + +static char * +output_242 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags |= CC_NOT_NEGATIVE; + return "bfextu %1{%b3:%b2},%0"; +} +} + +static char * +output_243 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "bfclr %0{%b2:%b1}"; +} +} + +static char * +output_244 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + return "bfset %0{%b2:%b1}"; +} +} + +static char * +output_245 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#if 0 + /* These special cases are now recognized by a specific pattern. */ + if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16) + return "move%.w %3,%0"; + if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8) + return "move%.b %3,%0"; +#endif + return "bfins %3,%0{%b2:%b1}"; +} +} + +static char * +output_246 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (operands[1] == const1_rtx + && GET_CODE (operands[2]) == CONST_INT) + { + int width = GET_CODE (operands[0]) == REG ? 31 : 7; + return output_btst (operands, + gen_rtx (CONST_INT, VOIDmode, + width - INTVAL (operands[2])), + operands[0], + insn, 1000); + /* Pass 1000 as SIGNPOS argument so that btst will + not think we are testing the sign bit for an `and' + and assume that nonzero implies a negative result. */ + } + if (INTVAL (operands[1]) != 32) + cc_status.flags = CC_NOT_NEGATIVE; + return "bftst %0{%b2:%b1}"; +} +} + +static char * +output_247 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (operands[1] == const1_rtx + && GET_CODE (operands[2]) == CONST_INT) + { + int width = GET_CODE (operands[0]) == REG ? 31 : 7; + return output_btst (operands, + gen_rtx (CONST_INT, VOIDmode, + width - INTVAL (operands[2])), + operands[0], + insn, 1000); + /* Pass 1000 as SIGNPOS argument so that btst will + not think we are testing the sign bit for an `and' + and assume that nonzero implies a negative result. */ + } + if (INTVAL (operands[1]) != 32) + cc_status.flags = CC_NOT_NEGATIVE; + return "bftst %0{%b2:%b1}"; +} +} + +static char * +output_248 (operands, insn) + rtx *operands; + rtx insn; +{ + + cc_status = cc_prev_status; + OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0"); + +} + +static char * +output_249 (operands, insn) + rtx *operands; + rtx insn; +{ + + cc_status = cc_prev_status; + OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0"); + +} + +static char * +output_250 (operands, insn) + rtx *operands; + rtx insn; +{ + + cc_status = cc_prev_status; + OUTPUT_JUMP ("sgt %0", "fsgt %0", 0); + +} + +static char * +output_251 (operands, insn) + rtx *operands; + rtx insn; +{ + cc_status = cc_prev_status; + return "shi %0"; +} + +static char * +output_252 (operands, insn) + rtx *operands; + rtx insn; +{ + cc_status = cc_prev_status; + OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0"); +} + +static char * +output_253 (operands, insn) + rtx *operands; + rtx insn; +{ + cc_status = cc_prev_status; + return "scs %0"; +} + +static char * +output_254 (operands, insn) + rtx *operands; + rtx insn; +{ + cc_status = cc_prev_status; + OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0"); +} + +static char * +output_255 (operands, insn) + rtx *operands; + rtx insn; +{ + cc_status = cc_prev_status; + return "scc %0"; +} + +static char * +output_256 (operands, insn) + rtx *operands; + rtx insn; +{ + + cc_status = cc_prev_status; + OUTPUT_JUMP ("sle %0", "fsle %0", 0); + +} + +static char * +output_257 (operands, insn) + rtx *operands; + rtx insn; +{ + cc_status = cc_prev_status; + return "sls %0"; +} + +static char * +output_258 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef MOTOROLA + OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0"); +#else + OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0"); +#endif +} +} + +static char * +output_259 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef MOTOROLA + OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0"); +#else + OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0"); +#endif +} +} + +static char * +output_260 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + OUTPUT_JUMP ("jbgt %l0", "fbgt %l0", 0); +#else + OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0); +#endif + +} + +static char * +output_261 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jbhi %l0"; +#else + return "jhi %l0"; +#endif + +} + +static char * +output_262 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + OUTPUT_JUMP ("jblt %l0", "fblt %l0", "jbmi %l0"); +#else + OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0"); +#endif + +} + +static char * +output_263 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jbcs %l0"; +#else + return "jcs %l0"; +#endif + +} + +static char * +output_264 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + OUTPUT_JUMP ("jbge %l0", "fbge %l0", "jbpl %l0"); +#else + OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0"); +#endif + +} + +static char * +output_265 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jbcc %l0"; +#else + return "jcc %l0"; +#endif + +} + +static char * +output_266 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + OUTPUT_JUMP ("jble %l0", "fble %l0", 0); +#else + OUTPUT_JUMP ("jle %l0", "fjle %l0", 0); +#endif + +} + +static char * +output_267 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jbls %l0"; +#else + return "jls %l0"; +#endif + +} + +static char * +output_268 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef MOTOROLA + OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0"); +#else + OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0"); +#endif +} +} + +static char * +output_269 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifdef MOTOROLA + OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0"); +#else + OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0"); +#endif +} +} + +static char * +output_270 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + OUTPUT_JUMP ("jble %l0", "fbngt %l0", 0); +#else + OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0); +#endif + +} + +static char * +output_271 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jbls %l0"; +#else + return "jls %l0"; +#endif + +} + +static char * +output_272 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + OUTPUT_JUMP ("jbge %l0", "fbnlt %l0", "jbpl %l0"); +#else + OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0"); +#endif + +} + +static char * +output_273 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jbcc %l0"; +#else + return "jcc %l0"; +#endif + +} + +static char * +output_274 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + OUTPUT_JUMP ("jblt %l0", "fbnge %l0", "jbmi %l0"); +#else + OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0"); +#endif + +} + +static char * +output_275 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jbcs %l0"; +#else + return "jcs %l0"; +#endif + +} + +static char * +output_276 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + OUTPUT_JUMP ("jbgt %l0", "fbnle %l0", 0); +#else + OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0); +#endif + +} + +static char * +output_277 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jbhi %l0"; +#else + return "jhi %l0"; +#endif + +} + +static char * +output_278 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jbra %l0"; +#else + return "jra %l0"; +#endif + +} + +static char * +output_280 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jmp (%0)"; +#else + return "jmp %0@"; +#endif + +} + +static char * +output_281 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef ASM_RETURN_CASE_JUMP + ASM_RETURN_CASE_JUMP; +#else +#ifdef SGS +#ifdef ASM_OUTPUT_CASE_LABEL + return "jmp 6(%%pc,%0.w)"; +#else +#ifdef CRDS + return "jmp 2(pc,%0.w)"; +#else + return "jmp 2(%%pc,%0.w)"; +#endif /* end !CRDS */ +#endif +#else /* not SGS */ +#ifdef MOTOROLA + return "jmp (2,pc,%0.w)"; +#else + return "jmp pc@(2,%0:w)"; +#endif +#endif +#endif + +} + +static char * +output_282 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + if (DATA_REG_P (operands[0])) + return "dbra %0,%l1"; + if (GET_CODE (operands[0]) == MEM) + { +#ifdef MOTOROLA +#ifdef NO_ADDSUB_Q + return "sub%.w %#1,%0\n\tjbcc %l1"; +#else + return "subq%.w %#1,%0\n\tjbcc %l1"; +#endif +#else /* not MOTOROLA */ + return "subqw %#1,%0\n\tjcc %l1"; +#endif + } +#ifdef MOTOROLA +#ifdef SGS_CMP_ORDER +#ifdef NO_ADDSUB_Q + return "sub%.w %#1,%0\n\tcmp%.w %0,%#-1\n\tjbne %l1"; +#else + return "subq%.w %#1,%0\n\tcmp%.w %0,%#-1\n\tjbne %l1"; +#endif +#else /* not SGS_CMP_ORDER */ + return "subq%.w %#1,%0\n\tcmp%.w %#-1,%0\n\tjbne %l1"; +#endif +#else /* not MOTOROLA */ + return "subqw %#1,%0\n\tcmpw %#-1,%0\n\tjne %l1"; +#endif +} +} + +static char * +output_283 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; +#ifdef MOTOROLA +#ifdef NO_ADDSUB_Q + if (DATA_REG_P (operands[0])) + return "dbra %0,%l1\n\tclr%.w %0\n\tsub%.l %#1,%0\n\tjbcc %l1"; + if (GET_CODE (operands[0]) == MEM) + return "sub%.l %#1,%0\n\tjbcc %l1"; +#else + if (DATA_REG_P (operands[0])) + return "dbra %0,%l1\n\tclr%.w %0\n\tsubq%.l %#1,%0\n\tjbcc %l1"; + if (GET_CODE (operands[0]) == MEM) + return "subq%.l %#1,%0\n\tjbcc %l1"; +#endif /* NO_ADDSUB_Q */ +#ifdef SGS_CMP_ORDER +#ifdef NO_ADDSUB_Q + return "sub.l %#1,%0\n\tcmp.l %0,%#-1\n\tjbne %l1"; +#else + return "subq.l %#1,%0\n\tcmp.l %0,%#-1\n\tjbne %l1"; +#endif +#else /* not SGS_CMP_ORDER */ + return "subq.l %#1,%0\n\tcmp.l %#-1,%0\n\tjbne %l1"; +#endif /* not SGS_CMP_ORDER */ +#else /* not MOTOROLA */ + if (DATA_REG_P (operands[0])) + return "dbra %0,%l1\n\tclr%.w %0\n\tsubql %#1,%0\n\tjcc %l1"; + if (GET_CODE (operands[0]) == MEM) + return "subql %#1,%0\n\tjcc %l1"; + return "subql %#1,%0\n\tcmpl %#-1,%0\n\tjne %l1"; +#endif /* not MOTOROLA */ +} +} + +static char * +output_284 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; +#ifdef MOTOROLA +#ifdef NO_ADDSUB_Q + if (DATA_REG_P (operands[0])) + return "dbra %0,%l1"; + if (GET_CODE (operands[0]) == MEM) + return "sub%.w %#1,%0\n\tjbcc %l1"; +#else + if (DATA_REG_P (operands[0])) + return "dbra %0,%l1"; + if (GET_CODE (operands[0]) == MEM) + return "subq%.w %#1,%0\n\tjbcc %l1"; +#endif +#ifdef SGS_CMP_ORDER +#ifdef NO_ADDSUB_Q + return "sub.w %#1,%0\n\tcmp.w %0,%#-1\n\tjbne %l1"; +#else + return "subq.w %#1,%0\n\tcmp.w %0,%#-1\n\tjbne %l1"; +#endif +#else /* not SGS_CMP_ORDER */ + return "subq.w %#1,%0\n\tcmp.w %#-1,%0\n\tjbne %l1"; +#endif /* not SGS_CMP_ORDER */ +#else /* not MOTOROLA */ + if (DATA_REG_P (operands[0])) + return "dbra %0,%l1"; + if (GET_CODE (operands[0]) == MEM) + return "subqw %#1,%0\n\tjcc %l1"; + return "subqw %#1,%0\n\tcmpw %#-1,%0\n\tjne %l1"; +#endif /* not MOTOROLA */ +} +} + +static char * +output_285 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; +#ifdef MOTOROLA +#ifdef NO_ADDSUB_Q + if (DATA_REG_P (operands[0])) + return "dbra %0,%l1\n\tclr%.w %0\n\tsub%.l %#1,%0\n\tjbcc %l1"; + if (GET_CODE (operands[0]) == MEM) + return "sub%.l %#1,%0\n\tjbcc %l1"; +#else + if (DATA_REG_P (operands[0])) + return "dbra %0,%l1\n\tclr%.w %0\n\tsubq%.l %#1,%0\n\tjbcc %l1"; + if (GET_CODE (operands[0]) == MEM) + return "subq%.l %#1,%0\n\tjbcc %l1"; +#endif +#ifdef SGS_CMP_ORDER +#ifdef NO_ADDSUB_Q + return "sub.l %#1,%0\n\tcmp.l %0,%#-1\n\tjbne %l1"; +#else + return "subq.l %#1,%0\n\tcmp.l %0,%#-1\n\tjbne %l1"; +#endif +#else /* not SGS_CMP_ORDER */ + return "subq.l %#1,%0\n\tcmp.l %#-1,%0\n\tjbne %l1"; +#endif /* not SGS_CMP_ORDER */ +#else /* not MOTOROLA */ + if (DATA_REG_P (operands[0])) + return "dbra %0,%l1\n\tclr%.w %0\n\tsubql %#1,%0\n\tjcc %l1"; + if (GET_CODE (operands[0]) == MEM) + return "subql %#1,%0\n\tjcc %l1"; + return "subql %#1,%0\n\tcmpl %#-1,%0\n\tjne %l1"; +#endif /* not MOTOROLA */ +} +} + +static char * +output_287 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jsr %0"; +#else + return "jbsr %0"; +#endif + +} + +static char * +output_288 (operands, insn) + rtx *operands; + rtx insn; +{ + + if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) +#ifdef MOTOROLA + return "bsr %0@PLTPC"; +#else + return "jbsr %0,a1"; +#endif + return "jsr %0"; + +} + +static char * +output_290 (operands, insn) + rtx *operands; + rtx insn; +{ + +#ifdef MOTOROLA + return "jsr %1"; +#else + return "jbsr %1"; +#endif + +} + +static char * +output_291 (operands, insn) + rtx *operands; + rtx insn; +{ + + if (GET_CODE (operands[1]) == MEM + && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) +#ifdef MOTOROLA + return "bsr %1@PLTPC"; +#else + return "jbsr %1,a1"; +#endif + return "jsr %1"; + +} + +static char * +output_295 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx, + gen_rtx (CONST_INT, VOIDmode, NEED_PROBE)); + return "tstl %a0"; +} +} + +static char * +output_296 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (current_function_pops_args == 0) + return "rts"; + operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args); + return "rtd %0"; +} +} + +static char * +output_299 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn ("move%.l %1,%@", xoperands); + output_asm_insn ("move%.l %1,%-", operands); + return "fmove%.d %+,%0"; +} + +} + +static char * +output_300 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (INTVAL (operands[0]) > 4) + { + rtx xoperands[2]; + xoperands[0] = stack_pointer_rtx; + xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4); +#ifndef NO_ADDSUB_Q + if (INTVAL (xoperands[1]) <= 8) + output_asm_insn ("addq%.w %1,%0", xoperands); + else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020) + { + xoperands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (xoperands[1]) - 8); + output_asm_insn ("addq%.w %#8,%0\n\taddq%.w %1,%0", xoperands); + } + else +#endif + if (INTVAL (xoperands[1]) <= 0x7FFF) + output_asm_insn ("add%.w %1,%0", xoperands); + else + output_asm_insn ("add%.l %1,%0", xoperands); + } + if (FP_REG_P (operands[2])) + return "fmove%.s %2,%@"; + return "move%.l %2,%@"; +} +} + +static char * +output_301 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (INTVAL (operands[0]) > 4) + { + rtx xoperands[2]; + xoperands[0] = stack_pointer_rtx; + xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4); +#ifndef NO_ADDSUB_Q + if (INTVAL (xoperands[1]) <= 8) + output_asm_insn ("addq%.w %1,%0", xoperands); + else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020) + { + xoperands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (xoperands[1]) - 8); + output_asm_insn ("addq%.w %#8,%0\n\taddq%.w %1,%0", xoperands); + } + else +#endif + if (INTVAL (xoperands[1]) <= 0x7FFF) + output_asm_insn ("add%.w %1,%0", xoperands); + else + output_asm_insn ("add%.l %1,%0", xoperands); + } + if (operands[2] == const0_rtx) + return "clr%.l %@"; + return "move%.l %2,%@"; +} +} + +static char * +output_302 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + rtx xoperands[4]; + + if (GET_CODE (operands[1]) == REG) + return "move%.l %1,%-"; + + xoperands[1] = operands[1]; + xoperands[2] + = gen_rtx (MEM, QImode, + gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, + gen_rtx (CONST_INT, VOIDmode, 3))); + xoperands[3] = stack_pointer_rtx; + output_asm_insn ("subq%.w %#4,%3\n\tmove%.b %1,%2", xoperands); + return ""; +} +} + +static char * +output_303 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + if (operands[1] == const0_rtx + && (DATA_REG_P (operands[0]) + || GET_CODE (operands[0]) == MEM) + /* clr insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + && (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM + && MEM_VOLATILE_P (operands[0])))) + return "clr%.w %0"; + } + return "move%.w %1,%0"; +} +} + +static char * +output_304 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + output_dbcc_and_branch (operands); + return ""; +} +} + +static char * +output_305 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + CC_STATUS_INIT; + output_dbcc_and_branch (operands); + return ""; +} +} + +static char * +output_306 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_306[] = { + "fpma%.d %1,%w2,%w3,%0", + "fpma%.d %x1,%x2,%x3,%0", + "fpma%.d %x1,%x2,%x3,%0", + }; + return strings_306[which_alternative]; +} + +static char * +output_307 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_307[] = { + "fpma%.s %1,%w2,%w3,%0", + "fpma%.s %1,%2,%3,%0", + "fpma%.s %1,%2,%3,%0", + }; + return strings_307[which_alternative]; +} + +static char * +output_308 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_308[] = { + "fpms%.d %3,%w2,%w1,%0", + "fpms%.d %x3,%2,%x1,%0", + "fpms%.d %x3,%2,%x1,%0", + }; + return strings_308[which_alternative]; +} + +static char * +output_309 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_309[] = { + "fpms%.s %3,%w2,%w1,%0", + "fpms%.s %3,%2,%1,%0", + "fpms%.s %3,%2,%1,%0", + }; + return strings_309[which_alternative]; +} + +static char * +output_310 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_310[] = { + "fpmr%.d %2,%w1,%w3,%0", + "fpmr%.d %x2,%1,%x3,%0", + "fpmr%.d %x2,%1,%x3,%0", + }; + return strings_310[which_alternative]; +} + +static char * +output_311 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_311[] = { + "fpmr%.s %2,%w1,%w3,%0", + "fpmr%.s %x2,%1,%x3,%0", + "fpmr%.s %x2,%1,%x3,%0", + }; + return strings_311[which_alternative]; +} + +static char * +output_312 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_312[] = { + "fpam%.d %2,%w1,%w3,%0", + "fpam%.d %x2,%1,%x3,%0", + "fpam%.d %x2,%1,%x3,%0", + }; + return strings_312[which_alternative]; +} + +static char * +output_313 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_313[] = { + "fpam%.s %2,%w1,%w3,%0", + "fpam%.s %x2,%1,%x3,%0", + "fpam%.s %x2,%1,%x3,%0", + }; + return strings_313[which_alternative]; +} + +static char * +output_314 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_314[] = { + "fpsm%.d %2,%w1,%w3,%0", + "fpsm%.d %x2,%1,%x3,%0", + "fpsm%.d %x2,%1,%x3,%0", + }; + return strings_314[which_alternative]; +} + +static char * +output_315 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_315[] = { + "fpsm%.d %3,%w2,%w1,%0", + "fpsm%.d %x3,%2,%x1,%0", + "fpsm%.d %x3,%2,%x1,%0", + }; + return strings_315[which_alternative]; +} + +static char * +output_316 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_316[] = { + "fpsm%.s %2,%w1,%w3,%0", + "fpsm%.s %x2,%1,%x3,%0", + "fpsm%.s %x2,%1,%x3,%0", + }; + return strings_316[which_alternative]; +} + +static char * +output_317 (operands, insn) + rtx *operands; + rtx insn; +{ + static /*const*/ char *const strings_317[] = { + "fpsm%.s %3,%w2,%w1,%0", + "fpsm%.s %x3,%2,%x1,%0", + "fpsm%.s %x3,%2,%x1,%0", + }; + return strings_317[which_alternative]; +} + +static char * +output_318 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags = CC_IN_68881; + return "ftst%.x %0"; +} +} + +static char * +output_320 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + cc_status.flags = CC_IN_68881; +#ifdef SGS_CMP_ORDER + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return "fcmp%.x %0,%1"; + else + return "fcmp%.x %0,%f1"; + } + cc_status.flags |= CC_REVERSED; + return "fcmp%.x %1,%f0"; +#else + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return "fcmp%.x %1,%0"; + else + return "fcmp%.x %f1,%0"; + } + cc_status.flags |= CC_REVERSED; + return "fcmp%.x %f0,%1"; +#endif +} +} + +static char * +output_321 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) + { + if (REGNO (operands[0]) == REGNO (operands[1])) + { + /* Extending float to double in an fp-reg is a no-op. + NOTICE_UPDATE_CC has already assumed that the + cc will be set. So cancel what it did. */ + cc_status = cc_prev_status; + return ""; + } + return "f%$move%.x %1,%0"; + } + if (FP_REG_P (operands[0])) + return "f%$move%.s %f1,%0"; + return "fmove%.x %f1,%0"; +} +} + +static char * +output_322 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) + { + if (REGNO (operands[0]) == REGNO (operands[1])) + { + /* Extending float to double in an fp-reg is a no-op. + NOTICE_UPDATE_CC has already assumed that the + cc will be set. So cancel what it did. */ + cc_status = cc_prev_status; + return ""; + } + return "fmove%.x %1,%0"; + } + if (FP_REG_P (operands[0])) + return "f%&move%.d %f1,%0"; + return "fmove%.x %f1,%0"; +} +} + +static char * +output_323 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0])) + { + output_asm_insn ("fmove%.d %f1,%-\n\tmove%.l %+,%0", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return "move%.l %+,%0"; + } + return "fmove%.d %f1,%0"; +} +} + +static char * +output_328 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[1])) + return "fintrz%.x %f1,%0"; + return "fintrz%.x %f1,%0"; +} +} + +static char * +output_333 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return "fadd%.x %2,%0"; + return "fadd%.x %f2,%0"; +} +} + +static char * +output_335 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return "fsub%.x %2,%0"; + return "fsub%.x %f2,%0"; +} +} + +static char * +output_337 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return "fmul%.x %2,%0"; + return "fmul%.x %f2,%0"; +} +} + +static char * +output_339 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[2])) + return "fdiv%.x %2,%0"; + return "fdiv%.x %f2,%0"; +} +} + +static char * +output_340 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return "fneg%.x %1,%0"; + return "fneg%.x %f1,%0"; +} +} + +static char * +output_341 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return "fabs%.x %1,%0"; + return "fabs%.x %f1,%0"; +} +} + +static char * +output_342 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + return "fsqrt%.x %1,%0"; +} +} + +char * const insn_template[] = + { + 0, + 0, + 0, + "tst%.w %0", + "tst%.b %0", + 0, + "fptst%.s %x0\n\tfpmove fpastatus,%1\n\tmovw %1,cc", + 0, + 0, + "fptst%.d %x0\n\tfpmove fpastatus,%1\n\tmovw %1,cc", + 0, + 0, + 0, + 0, + 0, + "fpcmp%.d %y1,%0\n\tfpmove fpastatus,%2\n\tmovw %2,cc", + 0, + 0, + "fpcmp%.s %w1,%x0\n\tfpmove fpastatus,%2\n\tmovw %2,cc", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "pea %a1", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "ext%.w %0", + "extb%.l %0", + 0, + "fpstod %w1,%0", + 0, + 0, + "fpdtos %y1,%0", + 0, + "fmove%.s %f1,%0", + 0, + "fpltos %1,%0", + "f%$move%.l %1,%0", + 0, + "fpltod %1,%0", + "f%&move%.l %1,%0", + "f%$move%.w %1,%0", + "fmove%.w %1,%0", + "fmove%.b %1,%0", + "f%&move%.b %1,%0", + 0, + 0, + 0, + 0, + 0, + "fmove%.b %1,%0", + "fmove%.w %1,%0", + "fmove%.l %1,%0", + "fmove%.b %1,%0", + "fmove%.w %1,%0", + "fmove%.l %1,%0", + "fpstol %w1,%0", + "fpdtol %y1,%0", + 0, + "add%.w %2,%0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "sub%.w %2,%0", + "sub%.w %2,%0", + "sub%.w %1,%0", + "sub%.b %2,%0", + "sub%.b %1,%0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "muls%.l %2,%0", + 0, + 0, + 0, + "mulu%.l %2,%3:%0", + "mulu%.l %2,%3:%0", + 0, + "muls%.l %2,%3:%0", + "muls%.l %2,%3:%0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "and%.w %2,%0", + "and%.w %1,%0", + "and%.w %1,%0", + "and%.b %2,%0", + "and%.b %1,%0", + "and%.b %1,%0", + 0, + "or%.w %2,%0", + "or%.w %1,%0", + "or%.w %1,%0", + "or%.b %2,%0", + "or%.b %1,%0", + "or%.b %1,%0", + 0, + "eor%.w %2,%0", + "eor%.w %1,%0", + "eor%.w %1,%0", + "eor%.b %2,%0", + "eor%.b %1,%0", + "eor%.b %1,%0", + "neg%.l %0", + "neg%.w %0", + "neg%.w %0", + "neg%.b %0", + "neg%.b %0", + 0, + "fpneg%.s %w1,%0", + 0, + 0, + "fpneg%.d %y1, %0", + 0, + 0, + 0, + "fpabs%.s %y1,%0", + 0, + 0, + "fpabs%.d %y1,%0", + 0, + "not%.l %0", + "not%.w %0", + "not%.w %0", + "not%.b %0", + "not%.b %0", + 0, + 0, + 0, + "asl%.w %2,%0", + "asl%.w %1,%0", + "asl%.b %2,%0", + "asl%.b %1,%0", + "swap %0\n\text%.l %0", + 0, + 0, + "asr%.w %2,%0", + "asr%.w %1,%0", + "asr%.b %2,%0", + "asr%.b %1,%0", + 0, + 0, + 0, + "lsl%.w %2,%0", + "lsl%.w %1,%0", + "lsl%.b %2,%0", + "lsl%.b %1,%0", + 0, + 0, + 0, + "lsr%.w %2,%0", + "lsr%.w %1,%0", + "lsr%.b %2,%0", + "lsr%.b %1,%0", + "rol%.l %2,%0", + "rol%.w %2,%0", + "rol%.w %1,%0", + "rol%.b %2,%0", + "rol%.b %1,%0", + "ror%.l %2,%0", + "ror%.w %2,%0", + "ror%.w %1,%0", + "ror%.b %2,%0", + "ror%.b %1,%0", + 0, + 0, + 0, + 0, + 0, + 0, + "bfexts %1{%b3:%b2},%0", + 0, + 0, + 0, + 0, + "bfins %3,%0{%b2:%b1}", + "bfexts %1{%b3:%b2},%0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "", + "nop", + 0, + 0, + "jmp %a0", + "lea %a1,%0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "fmove%.s %f1,%0", + "fmove%.l %1,%0", + "fmove%.w %1,%0", + "fmove%.b %1,%0", + 0, + "fmove%.b %1,%0", + "fmove%.w %1,%0", + "fmove%.l %1,%0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + }; + +char *(*const insn_outfun[])() = + { + output_0, + output_1, + output_2, + 0, + 0, + 0, + 0, + output_7, + 0, + 0, + output_10, + output_11, + output_12, + output_13, + 0, + 0, + output_16, + 0, + 0, + output_19, + output_20, + output_21, + output_22, + output_23, + output_24, + output_25, + output_26, + output_27, + 0, + output_29, + output_30, + output_31, + output_32, + output_33, + output_34, + output_35, + 0, + output_37, + output_38, + output_39, + 0, + output_41, + output_42, + output_43, + 0, + 0, + 0, + output_47, + output_48, + output_49, + output_50, + 0, + 0, + 0, + 0, + output_55, + 0, + 0, + output_58, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_70, + output_71, + output_72, + output_73, + output_74, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_83, + 0, + output_85, + output_86, + output_87, + output_88, + output_89, + output_90, + 0, + output_92, + output_93, + 0, + output_95, + output_96, + output_97, + 0, + 0, + 0, + 0, + 0, + 0, + output_104, + output_105, + 0, + output_107, + output_108, + output_109, + output_110, + output_111, + 0, + output_113, + output_114, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_122, + output_123, + 0, + output_125, + output_126, + output_127, + output_128, + output_129, + output_130, + output_131, + output_132, + 0, + output_134, + output_135, + 0, + output_137, + output_138, + output_139, + output_140, + output_141, + output_142, + output_143, + output_144, + output_145, + output_146, + output_147, + 0, + 0, + 0, + 0, + 0, + 0, + output_154, + 0, + 0, + 0, + 0, + 0, + 0, + output_161, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_175, + 0, + 0, + output_178, + output_179, + 0, + 0, + output_182, + 0, + 0, + output_185, + 0, + 0, + 0, + 0, + 0, + output_191, + output_192, + output_193, + 0, + 0, + 0, + 0, + 0, + output_199, + output_200, + 0, + 0, + 0, + 0, + output_205, + output_206, + output_207, + 0, + 0, + 0, + 0, + output_212, + output_213, + output_214, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_229, + output_230, + output_231, + output_232, + output_233, + output_234, + 0, + output_236, + output_237, + output_238, + output_239, + 0, + 0, + output_242, + output_243, + output_244, + output_245, + output_246, + output_247, + output_248, + output_249, + output_250, + output_251, + output_252, + output_253, + output_254, + output_255, + output_256, + output_257, + output_258, + output_259, + output_260, + output_261, + output_262, + output_263, + output_264, + output_265, + output_266, + output_267, + output_268, + output_269, + output_270, + output_271, + output_272, + output_273, + output_274, + output_275, + output_276, + output_277, + output_278, + 0, + output_280, + output_281, + output_282, + output_283, + output_284, + output_285, + 0, + output_287, + output_288, + 0, + output_290, + output_291, + 0, + 0, + 0, + output_295, + output_296, + 0, + 0, + output_299, + output_300, + output_301, + output_302, + output_303, + output_304, + output_305, + output_306, + output_307, + output_308, + output_309, + output_310, + output_311, + output_312, + output_313, + output_314, + output_315, + output_316, + output_317, + output_318, + 0, + output_320, + output_321, + output_322, + output_323, + 0, + 0, + 0, + 0, + output_328, + 0, + 0, + 0, + 0, + output_333, + 0, + output_335, + 0, + output_337, + 0, + output_339, + output_340, + output_341, + output_342, + }; + +rtx (*const insn_gen_function[]) () = + { + 0, + 0, + gen_tstsi, + gen_tsthi, + gen_tstqi, + gen_tstsf, + gen_tstsf_fpa, + 0, + gen_tstdf, + gen_tstdf_fpa, + 0, + gen_cmpsi, + gen_cmphi, + gen_cmpqi, + gen_cmpdf, + gen_cmpdf_fpa, + 0, + gen_cmpsf, + gen_cmpsf_fpa, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_movsi, + 0, + gen_movhi, + gen_movstricthi, + gen_movqi, + gen_movstrictqi, + gen_movsf, + gen_movdf, + gen_movxf, + 0, + 0, + gen_movdi, + gen_pushasi, + gen_truncsiqi2, + gen_trunchiqi2, + gen_truncsihi2, + gen_zero_extendhisi2, + gen_zero_extendqihi2, + gen_zero_extendqisi2, + 0, + 0, + 0, + gen_extendhisi2, + gen_extendqihi2, + gen_extendqisi2, + gen_extendsfdf2, + 0, + 0, + gen_truncdfsf2, + 0, + 0, + 0, + gen_floatsisf2, + 0, + 0, + gen_floatsidf2, + 0, + 0, + gen_floathisf2, + gen_floathidf2, + gen_floatqisf2, + gen_floatqidf2, + gen_fix_truncdfsi2, + gen_fix_truncdfhi2, + gen_fix_truncdfqi2, + gen_ftruncdf2, + gen_ftruncsf2, + gen_fixsfqi2, + gen_fixsfhi2, + gen_fixsfsi2, + gen_fixdfqi2, + gen_fixdfhi2, + gen_fixdfsi2, + 0, + 0, + gen_addsi3, + 0, + gen_addhi3, + 0, + 0, + gen_addqi3, + 0, + 0, + gen_adddf3, + 0, + 0, + gen_addsf3, + 0, + 0, + gen_subsi3, + 0, + gen_subhi3, + 0, + gen_subqi3, + 0, + gen_subdf3, + 0, + 0, + gen_subsf3, + 0, + 0, + gen_mulhi3, + gen_mulhisi3, + 0, + gen_mulsi3, + gen_umulhisi3, + 0, + gen_umulsidi3, + 0, + 0, + gen_mulsidi3, + 0, + 0, + gen_muldf3, + 0, + 0, + gen_mulsf3, + 0, + 0, + gen_divhi3, + gen_divhisi3, + 0, + gen_udivhi3, + gen_udivhisi3, + 0, + gen_divdf3, + 0, + 0, + gen_divsf3, + 0, + 0, + gen_modhi3, + gen_modhisi3, + 0, + gen_umodhi3, + gen_umodhisi3, + 0, + gen_divmodsi4, + gen_udivmodsi4, + gen_andsi3, + gen_andhi3, + 0, + 0, + gen_andqi3, + 0, + 0, + gen_iorsi3, + gen_iorhi3, + 0, + 0, + gen_iorqi3, + 0, + 0, + gen_xorsi3, + gen_xorhi3, + 0, + 0, + gen_xorqi3, + 0, + 0, + gen_negsi2, + gen_neghi2, + 0, + gen_negqi2, + 0, + gen_negsf2, + 0, + 0, + gen_negdf2, + 0, + 0, + gen_sqrtdf2, + gen_abssf2, + 0, + 0, + gen_absdf2, + 0, + 0, + gen_one_cmplsi2, + gen_one_cmplhi2, + 0, + gen_one_cmplqi2, + 0, + 0, + 0, + gen_ashlsi3, + gen_ashlhi3, + 0, + gen_ashlqi3, + 0, + 0, + 0, + gen_ashrsi3, + gen_ashrhi3, + 0, + gen_ashrqi3, + 0, + 0, + 0, + gen_lshlsi3, + gen_lshlhi3, + 0, + gen_lshlqi3, + 0, + 0, + 0, + gen_lshrsi3, + gen_lshrhi3, + 0, + gen_lshrqi3, + 0, + gen_rotlsi3, + gen_rotlhi3, + 0, + gen_rotlqi3, + 0, + gen_rotrsi3, + gen_rotrhi3, + 0, + gen_rotrqi3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_extv, + gen_extzv, + 0, + 0, + 0, + gen_insv, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_seq, + gen_sne, + gen_sgt, + gen_sgtu, + gen_slt, + gen_sltu, + gen_sge, + gen_sgeu, + gen_sle, + gen_sleu, + gen_beq, + gen_bne, + gen_bgt, + gen_bgtu, + gen_blt, + gen_bltu, + gen_bge, + gen_bgeu, + gen_ble, + gen_bleu, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_jump, + gen_tablejump, + 0, + 0, + 0, + 0, + 0, + gen_decrement_and_branch_until_zero, + gen_call, + 0, + 0, + gen_call_value, + 0, + 0, + gen_untyped_call, + gen_blockage, + gen_nop, + gen_probe, + gen_return, + gen_indirect_jump, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_tstxf, + gen_cmpxf, + 0, + gen_extendsfxf2, + gen_extenddfxf2, + gen_truncxfdf2, + gen_truncxfsf2, + gen_floatsixf2, + gen_floathixf2, + gen_floatqixf2, + gen_ftruncxf2, + gen_fixxfqi2, + gen_fixxfhi2, + gen_fixxfsi2, + gen_addxf3, + 0, + gen_subxf3, + 0, + gen_mulxf3, + 0, + gen_divxf3, + 0, + gen_negxf2, + gen_absxf2, + gen_sqrtxf2, + }; + +char *insn_name[] = + { + "tstsi-1", + "tstsi-0", + "tstsi", + "tsthi", + "tstqi", + "tstsf", + "tstsf_fpa", + "tstsf_fpa+1", + "tstdf", + "tstdf_fpa", + "tstdf_fpa+1", + "cmpsi", + "cmphi", + "cmpqi", + "cmpdf", + "cmpdf_fpa", + "cmpdf_fpa+1", + "cmpsf", + "cmpsf_fpa", + "cmpsf_fpa+1", + "cmpsf_fpa+2", + "cmpsf_fpa+3", + "cmpsf_fpa+4", + "cmpsf_fpa+5", + "movsi-4", + "movsi-3", + "movsi-2", + "movsi-1", + "movsi", + "movsi+1", + "movhi", + "movstricthi", + "movqi", + "movstrictqi", + "movsf", + "movdf", + "movxf", + "movxf+1", + "movdi-1", + "movdi", + "pushasi", + "truncsiqi2", + "trunchiqi2", + "truncsihi2", + "zero_extendhisi2", + "zero_extendqihi2", + "zero_extendqisi2", + "zero_extendqisi2+1", + "zero_extendqisi2+2", + "extendhisi2-1", + "extendhisi2", + "extendqihi2", + "extendqisi2", + "extendsfdf2", + "extendsfdf2+1", + "truncdfsf2-1", + "truncdfsf2", + "truncdfsf2+1", + "truncdfsf2+2", + "floatsisf2-1", + "floatsisf2", + "floatsisf2+1", + "floatsidf2-1", + "floatsidf2", + "floatsidf2+1", + "floathisf2-1", + "floathisf2", + "floathidf2", + "floatqisf2", + "floatqidf2", + "fix_truncdfsi2", + "fix_truncdfhi2", + "fix_truncdfqi2", + "ftruncdf2", + "ftruncsf2", + "fixsfqi2", + "fixsfhi2", + "fixsfsi2", + "fixdfqi2", + "fixdfhi2", + "fixdfsi2", + "fixdfsi2+1", + "addsi3-1", + "addsi3", + "addsi3+1", + "addhi3", + "addhi3+1", + "addqi3-1", + "addqi3", + "addqi3+1", + "adddf3-1", + "adddf3", + "adddf3+1", + "addsf3-1", + "addsf3", + "addsf3+1", + "subsi3-1", + "subsi3", + "subsi3+1", + "subhi3", + "subhi3+1", + "subqi3", + "subqi3+1", + "subdf3", + "subdf3+1", + "subsf3-1", + "subsf3", + "subsf3+1", + "mulhi3-1", + "mulhi3", + "mulhisi3", + "mulhisi3+1", + "mulsi3", + "umulhisi3", + "umulhisi3+1", + "umulsidi3", + "umulsidi3+1", + "mulsidi3-1", + "mulsidi3", + "mulsidi3+1", + "muldf3-1", + "muldf3", + "muldf3+1", + "mulsf3-1", + "mulsf3", + "mulsf3+1", + "divhi3-1", + "divhi3", + "divhisi3", + "divhisi3+1", + "udivhi3", + "udivhisi3", + "udivhisi3+1", + "divdf3", + "divdf3+1", + "divsf3-1", + "divsf3", + "divsf3+1", + "modhi3-1", + "modhi3", + "modhisi3", + "modhisi3+1", + "umodhi3", + "umodhisi3", + "umodhisi3+1", + "divmodsi4", + "udivmodsi4", + "andsi3", + "andhi3", + "andhi3+1", + "andqi3-1", + "andqi3", + "andqi3+1", + "iorsi3-1", + "iorsi3", + "iorhi3", + "iorhi3+1", + "iorqi3-1", + "iorqi3", + "iorqi3+1", + "xorsi3-1", + "xorsi3", + "xorhi3", + "xorhi3+1", + "xorqi3-1", + "xorqi3", + "xorqi3+1", + "negsi2-1", + "negsi2", + "neghi2", + "neghi2+1", + "negqi2", + "negqi2+1", + "negsf2", + "negsf2+1", + "negdf2-1", + "negdf2", + "negdf2+1", + "sqrtdf2-1", + "sqrtdf2", + "abssf2", + "abssf2+1", + "absdf2-1", + "absdf2", + "absdf2+1", + "one_cmplsi2-1", + "one_cmplsi2", + "one_cmplhi2", + "one_cmplhi2+1", + "one_cmplqi2", + "one_cmplqi2+1", + "one_cmplqi2+2", + "ashlsi3-1", + "ashlsi3", + "ashlhi3", + "ashlhi3+1", + "ashlqi3", + "ashlqi3+1", + "ashlqi3+2", + "ashrsi3-1", + "ashrsi3", + "ashrhi3", + "ashrhi3+1", + "ashrqi3", + "ashrqi3+1", + "ashrqi3+2", + "lshlsi3-1", + "lshlsi3", + "lshlhi3", + "lshlhi3+1", + "lshlqi3", + "lshlqi3+1", + "lshlqi3+2", + "lshrsi3-1", + "lshrsi3", + "lshrhi3", + "lshrhi3+1", + "lshrqi3", + "lshrqi3+1", + "rotlsi3", + "rotlhi3", + "rotlhi3+1", + "rotlqi3", + "rotlqi3+1", + "rotrsi3", + "rotrhi3", + "rotrhi3+1", + "rotrqi3", + "rotrqi3+1", + "rotrqi3+2", + "rotrqi3+3", + "rotrqi3+4", + "extv-3", + "extv-2", + "extv-1", + "extv", + "extzv", + "extzv+1", + "extzv+2", + "insv-1", + "insv", + "insv+1", + "insv+2", + "insv+3", + "insv+4", + "seq-3", + "seq-2", + "seq-1", + "seq", + "sne", + "sgt", + "sgtu", + "slt", + "sltu", + "sge", + "sgeu", + "sle", + "sleu", + "beq", + "bne", + "bgt", + "bgtu", + "blt", + "bltu", + "bge", + "bgeu", + "ble", + "bleu", + "bleu+1", + "bleu+2", + "bleu+3", + "bleu+4", + "bleu+5", + "jump-5", + "jump-4", + "jump-3", + "jump-2", + "jump-1", + "jump", + "tablejump", + "tablejump+1", + "tablejump+2", + "tablejump+3", + "decrement_and_branch_until_zero-2", + "decrement_and_branch_until_zero-1", + "decrement_and_branch_until_zero", + "call", + "call+1", + "call_value-1", + "call_value", + "call_value+1", + "untyped_call-1", + "untyped_call", + "blockage", + "nop", + "probe", + "return", + "indirect_jump", + "indirect_jump+1", + "indirect_jump+2", + "indirect_jump+3", + "indirect_jump+4", + "indirect_jump+5", + "indirect_jump+6", + "indirect_jump+7", + "indirect_jump+8", + "indirect_jump+9", + "indirect_jump+10", + "tstxf-10", + "tstxf-9", + "tstxf-8", + "tstxf-7", + "tstxf-6", + "tstxf-5", + "tstxf-4", + "tstxf-3", + "tstxf-2", + "tstxf-1", + "tstxf", + "cmpxf", + "cmpxf+1", + "extendsfxf2", + "extenddfxf2", + "truncxfdf2", + "truncxfsf2", + "floatsixf2", + "floathixf2", + "floatqixf2", + "ftruncxf2", + "fixxfqi2", + "fixxfhi2", + "fixxfsi2", + "addxf3", + "addxf3+1", + "subxf3", + "subxf3+1", + "mulxf3", + "mulxf3+1", + "divxf3", + "divxf3+1", + "negxf2", + "absxf2", + "sqrtxf2", + }; +char **insn_name_ptr = insn_name; + +const int insn_n_operands[] = + { + 2, + 2, + 1, + 1, + 1, + 1, + 2, + 1, + 1, + 2, + 1, + 2, + 2, + 2, + 2, + 3, + 2, + 2, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 1, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 4, + 4, + 4, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 3, + 3, + 3, + 2, + 2, + 3, + 2, + 2, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 3, + 2, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 4, + 4, + 3, + 4, + 4, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 4, + 4, + 3, + 3, + 2, + 2, + 3, + 2, + 2, + 3, + 3, + 2, + 2, + 3, + 2, + 2, + 3, + 3, + 2, + 2, + 3, + 2, + 2, + 2, + 2, + 1, + 2, + 1, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 1, + 2, + 1, + 3, + 3, + 3, + 3, + 2, + 3, + 2, + 3, + 3, + 3, + 3, + 2, + 3, + 2, + 3, + 3, + 3, + 3, + 2, + 3, + 2, + 3, + 3, + 3, + 3, + 2, + 3, + 2, + 3, + 3, + 2, + 3, + 2, + 3, + 3, + 2, + 3, + 2, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 3, + 3, + 4, + 4, + 4, + 3, + 3, + 4, + 3, + 3, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 2, + 2, + 3, + 3, + 3, + 3, + 0, + 0, + 0, + 0, + 1, + 2, + 2, + 3, + 3, + 2, + 2, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 4, + 1, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + }; + +const int insn_n_dups[] = + { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 2, + 2, + 3, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 2, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 2, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + }; + +char *const insn_operand_constraint[][MAX_RECOG_OPERANDS] = + { + { "=m", "ro<>fyE", }, + { "=m", "ro<>Fy", }, + { "rm", }, + { "dm", }, + { "dm", }, + { "", }, + { "xmdF", "=d", }, + { "fdm", }, + { "", }, + { "xrmF", "=d", }, + { "fm", }, + { "rKs,mr,>", "mr,Ksr,>", }, + { "rnm,d,n,m", "d,rnm,m,n", }, + { "dn,md,>", "dm,nd,>", }, + { "", "", }, + { "x,y", "xH,rmF", "=d,d", }, + { "f,mG", "fmG,f", }, + { "", "", }, + { "x,y", "xH,rmF", "=d,d", }, + { "f,mdG", "fmdG,f", }, + { "do", "di", }, + { "d", "di", }, + { "do", "d", }, + { "d", "d", }, + { "md", "i", }, + { "do", "i", }, + { "=m", "J", }, + { "=g", }, + { "", "", }, + { "=g,da,y,!*x*r*m", "daymKs,i,g,*x*r*m", }, + { "=g", "g", }, + { "+dm", "rmn", }, + { "=d,*a,m,m,?*a", "dmi*a,d*a,dmi,?*a,m", }, + { "+dm", "dmn", }, + { "=rmf,x,y,rm,!x,!rm", "rmfF,xH,rmF,y,rm,x", }, + { "=rm,&rf,&rof<>,y,rm,x,!x,!rm", "rf,m,rofE<>,rmE,y,xH,rm,x", }, + { "", "", }, + { "=f,m,f,!r,!f", "m,f,f,f,r", }, + { "=rm,&rf,&rof<>", "rf,m,rof<>", }, + { "=rm,&r,&ro<>,y,rm,!*x,!rm", "rF,m,roi<>F,rmiF,y,rmF,*x", }, + { "=m", "p", }, + { "=dm,d", "doJ,i", }, + { "=dm,d", "doJ,i", }, + { "=dm,d", "roJ,i", }, + { "", "", }, + { "", "", }, + { "", "", }, + { "=do<>,d<", "r,m", }, + { "=do<>,d", "d,m", }, + { "=do<>,d", "d,m", }, + { "=*d,a", "0,rm", }, + { "=d", "0", }, + { "=d", "0", }, + { "", "", }, + { "=x,y", "xH,rmF", }, + { "=*fdm,f", "f,dmF", }, + { "", "", }, + { "=x,y", "xH,rmF", }, + { "=f", "fmG", }, + { "=dm", "f", }, + { "", "", }, + { "=y,x", "rmi,x", }, + { "=f", "dmi", }, + { "", "", }, + { "=y,x", "rmi,x", }, + { "=f", "dmi", }, + { "=f", "dmn", }, + { "=f", "dmn", }, + { "=f", "dmn", }, + { "=f", "dmn", }, + { "=dm", "f", "=d", "=d", }, + { "=dm", "f", "=d", "=d", }, + { "=dm", "f", "=d", "=d", }, + { "=f", "fFm", }, + { "=f", "dfFm", }, + { "=dm", "f", }, + { "=dm", "f", }, + { "=dm", "f", }, + { "=dm", "f", }, + { "=dm", "f", }, + { "=dm", "f", }, + { "=x,y", "xH,rmF", }, + { "=x,y", "xH,rmF", }, + { "=m,?a,?a,r", "%0,a,rJK,0", "dIKLs,rJK,a,mrIKLs", }, + { "=a", "0", "rm", }, + { "=m,r", "%0,0", "dn,rmn", }, + { "+m,d", "dn,rmn", }, + { "+m,d", "dn,rmn", }, + { "=m,d", "%0,0", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "", "", "", }, + { "=x,y", "%xH,y", "xH,dmF", }, + { "=f", "%0", "fmG", }, + { "", "", "", }, + { "=x,y", "%xH,y", "xH,rmF", }, + { "=f", "%0", "fdmF", }, + { "=m,r,!a,?d", "0,0,a,mrIKs", "dIKs,mrIKs,J,0", }, + { "=a", "0", "rm", }, + { "=m,r", "0,0", "dn,rmn", }, + { "+m,d", "dn,rmn", }, + { "=m,d", "0,0", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "", "", "", }, + { "=x,y,y", "xH,y,dmF", "xH,dmF,0", }, + { "=f", "0", "fmG", }, + { "", "", "", }, + { "=x,y,y", "xH,y,rmF", "xH,rmF,0", }, + { "=f", "0", "fdmF", }, + { "=d", "%0", "dmn", }, + { "=d", "%0", "dm", }, + { "=d", "%0", "n", }, + { "=d", "%0", "dmsK", }, + { "=d", "%0", "dm", }, + { "=d", "%0", "n", }, + { "", "", "", }, + { "=d", "%0", "dm", "=d", }, + { "=d", "%0", "n", "=d", }, + { "", "", "", }, + { "=d", "%0", "dm", "=d", }, + { "=d", "%0", "n", "=d", }, + { "", "", "", }, + { "=x,y", "%xH,y", "xH,rmF", }, + { "=f", "%0", "fmG", }, + { "", "", "", }, + { "=x,y", "%xH,y", "xH,rmF", }, + { "=f", "%0", "fdmF", }, + { "=d", "0", "dmn", }, + { "=d", "0", "dm", }, + { "=d", "0", "n", }, + { "=d", "0", "dmn", }, + { "=d", "0", "dm", }, + { "=d", "0", "n", }, + { "", "", "", }, + { "=x,y,y", "xH,y,rmF", "xH,rmF,0", }, + { "=f", "0", "fmG", }, + { "", "", "", }, + { "=x,y,y", "xH,y,rmF", "xH,rmF,0", }, + { "=f", "0", "fdmF", }, + { "=d", "0", "dmn", }, + { "=d", "0", "dm", }, + { "=d", "0", "n", }, + { "=d", "0", "dmn", }, + { "=d", "0", "dm", }, + { "=d", "0", "n", }, + { "=d", "0", "dmsK", "=d", }, + { "=d", "0", "dmsK", "=d", }, + { "=m,d", "%0,0", "dKs,dmKs", }, + { "=m,d", "%0,0", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "=m,d", "%0,0", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "=m,d", "%0,0", "dKs,dmKs", }, + { "=m,d", "%0,0", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "=m,d", "%0,0", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "+m,d", "dn,dmn", }, + { "=do,m", "%0,0", "di,dKs", }, + { "=dm", "%0", "dn", }, + { "+dm", "dn", }, + { "+dm", "dn", }, + { "=dm", "%0", "dn", }, + { "+dm", "dn", }, + { "+dm", "dn", }, + { "=dm", "0", }, + { "=dm", "0", }, + { "+dm", }, + { "=dm", "0", }, + { "+dm", }, + { "", "", }, + { "=x,y", "xH,rmF", }, + { "=f,d", "fdmF,0", }, + { "", "", }, + { "=x,y", "xH,rmF", }, + { "=f,d", "fmF,0", }, + { "=f", "fm", }, + { "", "", }, + { "=x,y", "xH,rmF", }, + { "=f", "fdmF", }, + { "", "", }, + { "=x,y", "xH,rmF", }, + { "=f", "fmF", }, + { "=dm", "0", }, + { "=dm", "0", }, + { "+dm", }, + { "=dm", "0", }, + { "+dm", }, + { "=d", "0", "i", }, + { "=d", "0", "i", }, + { "=d", "0", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "i", }, + { "=d", "0", "i", }, + { "=d", "0", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "i", }, + { "=d", "0", "i", }, + { "=d", "0", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "i", }, + { "=d", "0", "i", }, + { "=d", "0", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "=d", "0", "dI", }, + { "+d", "dI", }, + { "+o", "i", "i", "rmi", }, + { "+do", "i", "i", "d", }, + { "=rm", "o", "i", "i", }, + { "=&d", "do", "i", "i", }, + { "=rm", "o", "i", "i", }, + { "=d", "do", "i", "i", }, + { "=d,d", "o,d", "di,di", "di,di", }, + { "=d,d", "o,d", "di,di", "di,di", }, + { "+o,d", "di,di", "di,di", "i,i", }, + { "+o,d", "di,di", "di,di", }, + { "+o,d", "di,di", "di,di", }, + { "+o,d", "di,di", "di,di", "d,d", }, + { "=d", "d", "di", "di", }, + { "=d", "d", "di", "di", }, + { "+d", "di", "di", }, + { "+d", "di", "di", }, + { "+d", "di", "di", "d", }, + { "o", "di", "di", }, + { "d", "di", "di", }, + { "=d", }, + { "=d", }, + { "=d", }, + { "=d", }, + { "=d", }, + { "=d", }, + { "=d", }, + { "=d", }, + { "=d", }, + { "=d", }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { "", }, + { "a", }, + { "r", }, + { "+g", }, + { "+g", }, + { "+g", }, + { "+g", }, + { "", "", }, + { "o", "g", }, + { "o", "g", }, + { "", "", "", }, + { "=rf", "o", "g", }, + { "=rf", "o", "g", }, + { "", "", "", }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { "p", }, + { "=a", "p", }, + { "=f", "ad", }, + { "n", "=m", "rmfF", }, + { "n", "=m", "g", }, + { "", "dami", }, + { "=d", "rmn", }, + { "+d", "", "", "", }, + { "+d", "", "", "", }, + { "=x,y,y", "%x,dmF,y", "xH,y,y", "xH,y,dmF", }, + { "=x,y,y", "%x,ydmF,y", "xH,y,ydmF", "xH,ydmF,ydmF", }, + { "=x,y,y", "xH,rmF,y", "%xH,y,y", "x,y,rmF", }, + { "=x,y,y", "xH,rmF,yrmF", "%xH,rmF,y", "x,y,yrmF", }, + { "=x,y,y", "%xH,y,y", "x,y,rmF", "xH,rmF,y", }, + { "=x,y,y", "%xH,rmF,y", "x,y,yrmF", "xH,rmF,yrmF", }, + { "=x,y,y", "%xH,y,y", "x,y,rmF", "xH,rmF,y", }, + { "=x,y,y", "%xH,rmF,y", "x,y,yrmF", "xH,rmF,yrmF", }, + { "=x,y,y", "xH,y,y", "x,y,rmF", "xH,rmF,y", }, + { "=x,y,y", "xH,rmF,y", "xH,y,y", "x,y,rmF", }, + { "=x,y,y", "xH,rmF,y", "x,y,yrmF", "xH,rmF,yrmF", }, + { "=x,y,y", "xH,rmF,yrmF", "xH,rmF,y", "x,y,yrmF", }, + { "fm", }, + { "f,mG", "fmG,f", }, + { "f,mG", "fmG,f", }, + { "=fm,f", "f,m", }, + { "=fm,f", "f,m", }, + { "=m,!r", "f,f", }, + { "=dm", "f", }, + { "=f", "dmi", }, + { "=f", "dmn", }, + { "=f", "dmn", }, + { "=f", "fFm", }, + { "=dm", "f", }, + { "=dm", "f", }, + { "=dm", "f", }, + { "", "", "", }, + { "=f", "%0", "fmG", }, + { "", "", "", }, + { "=f", "0", "fmG", }, + { "", "", "", }, + { "=f", "%0", "fmG", }, + { "", "", "", }, + { "=f", "0", "fmG", }, + { "=f", "fmF", }, + { "=f", "fmF", }, + { "=f", "fm", }, + }; + +const enum machine_mode insn_operand_mode[][MAX_RECOG_OPERANDS] = + { + { DFmode, DFmode, }, + { DImode, DImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + { SFmode, }, + { SFmode, SImode, }, + { SFmode, }, + { DFmode, }, + { DFmode, SImode, }, + { DFmode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { DFmode, DFmode, }, + { DFmode, DFmode, SImode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { SFmode, SFmode, SImode, }, + { SFmode, SFmode, }, + { QImode, SImode, }, + { SImode, SImode, }, + { QImode, SImode, }, + { SImode, SImode, }, + { QImode, SImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { SImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { XFmode, XFmode, }, + { XFmode, XFmode, }, + { XFmode, XFmode, }, + { DImode, DImode, }, + { SImode, SImode, }, + { QImode, SImode, }, + { QImode, HImode, }, + { HImode, SImode, }, + { SImode, HImode, }, + { HImode, QImode, }, + { SImode, QImode, }, + { SImode, HImode, }, + { HImode, QImode, }, + { SImode, QImode, }, + { SImode, HImode, }, + { HImode, QImode, }, + { SImode, QImode, }, + { DFmode, SFmode, }, + { DFmode, SFmode, }, + { DFmode, SFmode, }, + { SFmode, DFmode, }, + { SFmode, DFmode, }, + { SFmode, DFmode, }, + { SFmode, DFmode, }, + { SFmode, SImode, }, + { SFmode, SImode, }, + { SFmode, SImode, }, + { DFmode, SImode, }, + { DFmode, SImode, }, + { DFmode, SImode, }, + { SFmode, HImode, }, + { DFmode, HImode, }, + { SFmode, QImode, }, + { DFmode, QImode, }, + { SImode, DFmode, SImode, SImode, }, + { HImode, DFmode, SImode, SImode, }, + { QImode, DFmode, SImode, SImode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { QImode, SFmode, }, + { HImode, SFmode, }, + { SImode, SFmode, }, + { QImode, DFmode, }, + { HImode, DFmode, }, + { SImode, DFmode, }, + { SImode, SFmode, }, + { SImode, DFmode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, HImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { DFmode, DFmode, DFmode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { SFmode, SFmode, SFmode, }, + { SFmode, SFmode, SFmode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, HImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { DFmode, DFmode, DFmode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { SFmode, SFmode, SFmode, }, + { SFmode, SFmode, SFmode, }, + { HImode, HImode, HImode, }, + { SImode, HImode, HImode, }, + { SImode, HImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, HImode, HImode, }, + { SImode, HImode, SImode, }, + { DImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { DImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { DFmode, DFmode, DFmode, }, + { DFmode, DFmode, DFmode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { SFmode, SFmode, SFmode, }, + { SFmode, SFmode, SFmode, }, + { HImode, HImode, HImode, }, + { HImode, SImode, HImode, }, + { HImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, SImode, HImode, }, + { HImode, SImode, SImode, }, + { DFmode, DFmode, DFmode, }, + { DFmode, DFmode, DFmode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { SFmode, SFmode, SFmode, }, + { SFmode, SFmode, SFmode, }, + { HImode, HImode, HImode, }, + { HImode, SImode, HImode, }, + { HImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, SImode, HImode, }, + { HImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { HImode, }, + { QImode, QImode, }, + { QImode, }, + { SFmode, SFmode, }, + { SFmode, SFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { DFmode, DFmode, }, + { DFmode, DFmode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { SFmode, SFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { DFmode, DFmode, }, + { DFmode, DFmode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { HImode, }, + { QImode, QImode, }, + { QImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, }, + { QImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, QImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, QImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, QImode, SImode, SImode, }, + { SImode, QImode, SImode, SImode, }, + { QImode, SImode, SImode, VOIDmode, }, + { QImode, SImode, SImode, }, + { QImode, SImode, SImode, }, + { QImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { QImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { QImode, }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode, }, + { SImode, }, + { HImode, }, + { HImode, }, + { SImode, }, + { HImode, }, + { SImode, }, + { QImode, SImode, }, + { QImode, SImode, }, + { QImode, SImode, }, + { VOIDmode, QImode, SImode, }, + { VOIDmode, QImode, SImode, }, + { VOIDmode, QImode, SImode, }, + { VOIDmode, VOIDmode, VOIDmode, }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { SImode, }, + { SImode, QImode, }, + { VOIDmode, VOIDmode, }, + { VOIDmode, VOIDmode, VOIDmode, }, + { VOIDmode, VOIDmode, VOIDmode, }, + { VOIDmode, VOIDmode, }, + { VOIDmode, VOIDmode, }, + { VOIDmode, VOIDmode, VOIDmode, VOIDmode, }, + { VOIDmode, VOIDmode, VOIDmode, VOIDmode, }, + { DFmode, DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, SFmode, }, + { DFmode, DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, SFmode, }, + { DFmode, DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, SFmode, }, + { DFmode, DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, SFmode, }, + { DFmode, DFmode, DFmode, DFmode, }, + { DFmode, DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, SFmode, }, + { SFmode, SFmode, SFmode, SFmode, }, + { XFmode, }, + { XFmode, XFmode, }, + { XFmode, XFmode, }, + { XFmode, SFmode, }, + { XFmode, DFmode, }, + { DFmode, XFmode, }, + { SFmode, XFmode, }, + { XFmode, SImode, }, + { XFmode, HImode, }, + { XFmode, QImode, }, + { XFmode, XFmode, }, + { QImode, XFmode, }, + { HImode, XFmode, }, + { SImode, XFmode, }, + { XFmode, XFmode, XFmode, }, + { XFmode, XFmode, XFmode, }, + { XFmode, XFmode, XFmode, }, + { XFmode, XFmode, XFmode, }, + { XFmode, XFmode, XFmode, }, + { XFmode, XFmode, XFmode, }, + { XFmode, XFmode, XFmode, }, + { XFmode, XFmode, XFmode, }, + { XFmode, XFmode, }, + { XFmode, XFmode, }, + { XFmode, DFmode, }, + }; + +const char insn_operand_strict_low[][MAX_RECOG_OPERANDS] = + { + { 0, 0, }, + { 0, 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, 0, }, + { 0, }, + { 0, }, + { 0, 0, }, + { 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 1, 0, }, + { 0, 0, }, + { 1, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 1, 0, }, + { 0, 0, }, + { 0, 0, }, + { 1, }, + { 0, 0, }, + { 1, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 1, }, + { 0, 0, }, + { 1, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, }, + { 1, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + }; + +extern int push_operand (); +extern int general_operand (); +extern int nonimmediate_operand (); +extern int scratch_operand (); +extern int address_operand (); +extern int register_operand (); +extern int const_int_operand (); +extern int not_sp_operand (); +extern int immediate_operand (); +extern int memory_operand (); + +int (*const insn_operand_predicate[][MAX_RECOG_OPERANDS])() = + { + { push_operand, general_operand, }, + { push_operand, general_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { general_operand, }, + { general_operand, scratch_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, scratch_operand, }, + { general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, scratch_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, scratch_operand, }, + { general_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { push_operand, general_operand, }, + { general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, nonimmediate_operand, }, + { nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, }, + { push_operand, address_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, general_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, register_operand, scratch_operand, scratch_operand, }, + { general_operand, register_operand, scratch_operand, scratch_operand, }, + { general_operand, register_operand, scratch_operand, scratch_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, const_int_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, const_int_operand, }, + { register_operand, register_operand, nonimmediate_operand, }, + { register_operand, register_operand, nonimmediate_operand, register_operand, }, + { register_operand, register_operand, const_int_operand, register_operand, }, + { register_operand, register_operand, nonimmediate_operand, }, + { register_operand, register_operand, nonimmediate_operand, register_operand, }, + { register_operand, register_operand, const_int_operand, register_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, nonimmediate_operand, }, + { general_operand, general_operand, const_int_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, nonimmediate_operand, }, + { general_operand, general_operand, const_int_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, nonimmediate_operand, }, + { general_operand, general_operand, const_int_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, nonimmediate_operand, }, + { general_operand, general_operand, const_int_operand, }, + { general_operand, general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, general_operand, }, + { not_sp_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, }, + { general_operand, general_operand, }, + { general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, }, + { general_operand, general_operand, }, + { general_operand, }, + { register_operand, register_operand, immediate_operand, }, + { register_operand, register_operand, immediate_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, immediate_operand, }, + { register_operand, register_operand, immediate_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, immediate_operand, }, + { register_operand, register_operand, immediate_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, immediate_operand, }, + { register_operand, register_operand, immediate_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { register_operand, register_operand, general_operand, }, + { register_operand, general_operand, }, + { nonimmediate_operand, immediate_operand, immediate_operand, general_operand, }, + { nonimmediate_operand, immediate_operand, immediate_operand, general_operand, }, + { general_operand, nonimmediate_operand, immediate_operand, immediate_operand, }, + { general_operand, nonimmediate_operand, immediate_operand, immediate_operand, }, + { general_operand, nonimmediate_operand, immediate_operand, immediate_operand, }, + { general_operand, nonimmediate_operand, immediate_operand, immediate_operand, }, + { general_operand, nonimmediate_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, general_operand, general_operand, }, + { nonimmediate_operand, general_operand, general_operand, immediate_operand, }, + { nonimmediate_operand, general_operand, general_operand, }, + { nonimmediate_operand, general_operand, general_operand, }, + { nonimmediate_operand, general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, general_operand, general_operand, }, + { nonimmediate_operand, general_operand, general_operand, }, + { nonimmediate_operand, general_operand, general_operand, }, + { nonimmediate_operand, general_operand, general_operand, general_operand, }, + { memory_operand, general_operand, general_operand, }, + { nonimmediate_operand, general_operand, general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0, }, + { register_operand, }, + { register_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { memory_operand, general_operand, }, + { memory_operand, general_operand, }, + { memory_operand, general_operand, }, + { 0, memory_operand, general_operand, }, + { 0, memory_operand, general_operand, }, + { 0, memory_operand, general_operand, }, + { 0, 0, 0, }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { address_operand, }, + { general_operand, address_operand, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { register_operand, general_operand, general_operand, general_operand, }, + { nonimmediate_operand, }, + { general_operand, general_operand, }, + { nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + }; + +const int insn_n_alternatives[] = + { + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 3, + 4, + 3, + 0, + 2, + 2, + 0, + 2, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 4, + 1, + 1, + 5, + 1, + 6, + 8, + 0, + 5, + 3, + 7, + 1, + 2, + 2, + 2, + 0, + 0, + 0, + 2, + 2, + 2, + 2, + 1, + 1, + 0, + 2, + 2, + 0, + 2, + 1, + 1, + 0, + 2, + 1, + 0, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 2, + 4, + 1, + 2, + 2, + 2, + 2, + 2, + 2, + 0, + 2, + 1, + 0, + 2, + 1, + 4, + 1, + 2, + 2, + 2, + 2, + 0, + 3, + 1, + 0, + 3, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 2, + 1, + 0, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 3, + 1, + 0, + 3, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 2, + 2, + 0, + 2, + 2, + 1, + 0, + 2, + 1, + 0, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 2, + 2, + 2, + 2, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 1, + 2, + 2, + 2, + 2, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 1, + }; diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-peep.c b/gnu/usr.bin/gcc2/arch/m68k/insn-peep.c new file mode 100644 index 000000000000..ac2cb51fdd8e --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-peep.c @@ -0,0 +1,410 @@ +/* Generated automatically by the program `genpeep' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "output.h" +#include "real.h" + +extern rtx peep_operand[]; + +#define operands peep_operand + +rtx +peephole (ins1) + rtx ins1; +{ + rtx insn, x, pat; + int i; + + if (NEXT_INSN (ins1) + && GET_CODE (NEXT_INSN (ins1)) == BARRIER) + return 0; + + insn = ins1; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L299; + x = XEXP (pat, 0); + if (GET_CODE (x) != REG) goto L299; + if (GET_MODE (x) != SImode) goto L299; + if (XINT (x, 0) != 15) goto L299; + x = XEXP (pat, 1); + if (GET_CODE (x) != PLUS) goto L299; + if (GET_MODE (x) != SImode) goto L299; + x = XEXP (XEXP (pat, 1), 0); + if (GET_CODE (x) != REG) goto L299; + if (GET_MODE (x) != SImode) goto L299; + if (XINT (x, 0) != 15) goto L299; + x = XEXP (XEXP (pat, 1), 1); + if (GET_CODE (x) != CONST_INT) goto L299; + if (XWINT (x, 0) != 4) goto L299; + do { insn = NEXT_INSN (insn); + if (insn == 0) goto L299; } + while (GET_CODE (insn) == NOTE + || (GET_CODE (insn) == INSN + && (GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER))); + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == BARRIER) + goto L299; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L299; + x = XEXP (pat, 0); + operands[0] = x; + if (! register_operand (x, DFmode)) goto L299; + x = XEXP (pat, 1); + operands[1] = x; + if (! register_operand (x, DFmode)) goto L299; + if (! (FP_REG_P (operands[0]) && ! FP_REG_P (operands[1]))) goto L299; + PATTERN (ins1) = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (2, operands)); + INSN_CODE (ins1) = 299; + delete_for_peephole (NEXT_INSN (ins1), insn); + return NEXT_INSN (insn); + L299: + + insn = ins1; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L300; + x = XEXP (pat, 0); + if (GET_CODE (x) != REG) goto L300; + if (GET_MODE (x) != SImode) goto L300; + if (XINT (x, 0) != 15) goto L300; + x = XEXP (pat, 1); + if (GET_CODE (x) != PLUS) goto L300; + if (GET_MODE (x) != SImode) goto L300; + x = XEXP (XEXP (pat, 1), 0); + if (GET_CODE (x) != REG) goto L300; + if (GET_MODE (x) != SImode) goto L300; + if (XINT (x, 0) != 15) goto L300; + x = XEXP (XEXP (pat, 1), 1); + operands[0] = x; + if (! immediate_operand (x, SImode)) goto L300; + do { insn = NEXT_INSN (insn); + if (insn == 0) goto L300; } + while (GET_CODE (insn) == NOTE + || (GET_CODE (insn) == INSN + && (GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER))); + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == BARRIER) + goto L300; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L300; + x = XEXP (pat, 0); + operands[1] = x; + if (! push_operand (x, SFmode)) goto L300; + x = XEXP (pat, 1); + operands[2] = x; + if (! general_operand (x, SFmode)) goto L300; + if (! (GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) >= 4 + && ! reg_mentioned_p (stack_pointer_rtx, operands[2]))) goto L300; + PATTERN (ins1) = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (3, operands)); + INSN_CODE (ins1) = 300; + delete_for_peephole (NEXT_INSN (ins1), insn); + return NEXT_INSN (insn); + L300: + + insn = ins1; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L301; + x = XEXP (pat, 0); + if (GET_CODE (x) != REG) goto L301; + if (GET_MODE (x) != SImode) goto L301; + if (XINT (x, 0) != 15) goto L301; + x = XEXP (pat, 1); + if (GET_CODE (x) != PLUS) goto L301; + if (GET_MODE (x) != SImode) goto L301; + x = XEXP (XEXP (pat, 1), 0); + if (GET_CODE (x) != REG) goto L301; + if (GET_MODE (x) != SImode) goto L301; + if (XINT (x, 0) != 15) goto L301; + x = XEXP (XEXP (pat, 1), 1); + operands[0] = x; + if (! immediate_operand (x, SImode)) goto L301; + do { insn = NEXT_INSN (insn); + if (insn == 0) goto L301; } + while (GET_CODE (insn) == NOTE + || (GET_CODE (insn) == INSN + && (GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER))); + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == BARRIER) + goto L301; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L301; + x = XEXP (pat, 0); + operands[1] = x; + if (! push_operand (x, SImode)) goto L301; + x = XEXP (pat, 1); + operands[2] = x; + if (! general_operand (x, SImode)) goto L301; + if (! (GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) >= 4 + && ! reg_mentioned_p (stack_pointer_rtx, operands[2]))) goto L301; + PATTERN (ins1) = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (3, operands)); + INSN_CODE (ins1) = 301; + delete_for_peephole (NEXT_INSN (ins1), insn); + return NEXT_INSN (insn); + L301: + + insn = ins1; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L302; + x = XEXP (pat, 0); + if (GET_CODE (x) != MEM) goto L302; + if (GET_MODE (x) != QImode) goto L302; + x = XEXP (XEXP (pat, 0), 0); + if (GET_CODE (x) != PRE_DEC) goto L302; + if (GET_MODE (x) != SImode) goto L302; + x = XEXP (XEXP (XEXP (pat, 0), 0), 0); + if (GET_CODE (x) != REG) goto L302; + if (GET_MODE (x) != SImode) goto L302; + if (XINT (x, 0) != 15) goto L302; + x = XEXP (pat, 1); + operands[1] = x; + if (! general_operand (x, QImode)) goto L302; + do { insn = NEXT_INSN (insn); + if (insn == 0) goto L302; } + while (GET_CODE (insn) == NOTE + || (GET_CODE (insn) == INSN + && (GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER))); + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == BARRIER) + goto L302; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L302; + x = XEXP (pat, 0); + if (GET_CODE (x) != REG) goto L302; + if (GET_MODE (x) != SImode) goto L302; + if (XINT (x, 0) != 15) goto L302; + x = XEXP (pat, 1); + if (GET_CODE (x) != MINUS) goto L302; + if (GET_MODE (x) != SImode) goto L302; + x = XEXP (XEXP (pat, 1), 0); + if (GET_CODE (x) != REG) goto L302; + if (GET_MODE (x) != SImode) goto L302; + if (XINT (x, 0) != 15) goto L302; + x = XEXP (XEXP (pat, 1), 1); + if (GET_CODE (x) != CONST_INT) goto L302; + if (XWINT (x, 0) != 2) goto L302; + if (! (! reg_mentioned_p (stack_pointer_rtx, operands[1]))) goto L302; + PATTERN (ins1) = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (2, operands)); + INSN_CODE (ins1) = 302; + delete_for_peephole (NEXT_INSN (ins1), insn); + return NEXT_INSN (insn); + L302: + + insn = ins1; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L303; + x = XEXP (pat, 0); + operands[0] = x; + if (! register_operand (x, SImode)) goto L303; + x = XEXP (pat, 1); + if (GET_CODE (x) != CONST_INT) goto L303; + if (XWINT (x, 0) != 0) goto L303; + do { insn = NEXT_INSN (insn); + if (insn == 0) goto L303; } + while (GET_CODE (insn) == NOTE + || (GET_CODE (insn) == INSN + && (GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER))); + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == BARRIER) + goto L303; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L303; + x = XEXP (pat, 0); + if (GET_CODE (x) != STRICT_LOW_PART) goto L303; + x = XEXP (XEXP (pat, 0), 0); + if (GET_CODE (x) != SUBREG) goto L303; + if (GET_MODE (x) != HImode) goto L303; + x = XEXP (XEXP (XEXP (pat, 0), 0), 0); + if (!rtx_equal_p (operands[0], x)) goto L303; + x = XEXP (XEXP (pat, 0), 0); + if (XINT (x, 1) != 0) goto L303; + x = XEXP (pat, 1); + operands[1] = x; + if (! general_operand (x, HImode)) goto L303; + if (! (strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0]))) goto L303; + PATTERN (ins1) = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (2, operands)); + INSN_CODE (ins1) = 303; + delete_for_peephole (NEXT_INSN (ins1), insn); + return NEXT_INSN (insn); + L303: + + insn = ins1; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L304; + x = XEXP (pat, 0); + if (GET_CODE (x) != PC) goto L304; + x = XEXP (pat, 1); + if (GET_CODE (x) != IF_THEN_ELSE) goto L304; + x = XEXP (XEXP (pat, 1), 0); + operands[3] = x; + if (! valid_dbcc_comparison_p (x, VOIDmode)) goto L304; + x = XEXP (XEXP (XEXP (pat, 1), 0), 0); + if (GET_CODE (x) != CC0) goto L304; + x = XEXP (XEXP (XEXP (pat, 1), 0), 1); + if (GET_CODE (x) != CONST_INT) goto L304; + if (XWINT (x, 0) != 0) goto L304; + x = XEXP (XEXP (pat, 1), 1); + if (GET_CODE (x) != LABEL_REF) goto L304; + x = XEXP (XEXP (XEXP (pat, 1), 1), 0); + operands[2] = x; + x = XEXP (XEXP (pat, 1), 2); + if (GET_CODE (x) != PC) goto L304; + do { insn = NEXT_INSN (insn); + if (insn == 0) goto L304; } + while (GET_CODE (insn) == NOTE + || (GET_CODE (insn) == INSN + && (GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER))); + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == BARRIER) + goto L304; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != PARALLEL) goto L304; + if (XVECLEN (x, 0) != 2) goto L304; + x = XVECEXP (pat, 0, 0); + if (GET_CODE (x) != SET) goto L304; + x = XEXP (XVECEXP (pat, 0, 0), 0); + if (GET_CODE (x) != PC) goto L304; + x = XEXP (XVECEXP (pat, 0, 0), 1); + if (GET_CODE (x) != IF_THEN_ELSE) goto L304; + x = XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0); + if (GET_CODE (x) != GE) goto L304; + x = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0); + if (GET_CODE (x) != PLUS) goto L304; + if (GET_MODE (x) != HImode) goto L304; + x = XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0), 0); + operands[0] = x; + if (! register_operand (x, HImode)) goto L304; + x = XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0), 1); + if (GET_CODE (x) != CONST_INT) goto L304; + if (XWINT (x, 0) != -1) goto L304; + x = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 1); + if (GET_CODE (x) != CONST_INT) goto L304; + if (XWINT (x, 0) != 0) goto L304; + x = XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1); + if (GET_CODE (x) != LABEL_REF) goto L304; + x = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0); + operands[1] = x; + x = XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 2); + if (GET_CODE (x) != PC) goto L304; + x = XVECEXP (pat, 0, 1); + if (GET_CODE (x) != SET) goto L304; + x = XEXP (XVECEXP (pat, 0, 1), 0); + if (!rtx_equal_p (operands[0], x)) goto L304; + x = XEXP (XVECEXP (pat, 0, 1), 1); + if (GET_CODE (x) != PLUS) goto L304; + if (GET_MODE (x) != HImode) goto L304; + x = XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0); + if (!rtx_equal_p (operands[0], x)) goto L304; + x = XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1); + if (GET_CODE (x) != CONST_INT) goto L304; + if (XWINT (x, 0) != -1) goto L304; + if (! (DATA_REG_P (operands[0]))) goto L304; + PATTERN (ins1) = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (4, operands)); + INSN_CODE (ins1) = 304; + delete_for_peephole (NEXT_INSN (ins1), insn); + return NEXT_INSN (insn); + L304: + + insn = ins1; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != SET) goto L305; + x = XEXP (pat, 0); + if (GET_CODE (x) != PC) goto L305; + x = XEXP (pat, 1); + if (GET_CODE (x) != IF_THEN_ELSE) goto L305; + x = XEXP (XEXP (pat, 1), 0); + operands[3] = x; + if (! valid_dbcc_comparison_p (x, VOIDmode)) goto L305; + x = XEXP (XEXP (XEXP (pat, 1), 0), 0); + if (GET_CODE (x) != CC0) goto L305; + x = XEXP (XEXP (XEXP (pat, 1), 0), 1); + if (GET_CODE (x) != CONST_INT) goto L305; + if (XWINT (x, 0) != 0) goto L305; + x = XEXP (XEXP (pat, 1), 1); + if (GET_CODE (x) != LABEL_REF) goto L305; + x = XEXP (XEXP (XEXP (pat, 1), 1), 0); + operands[2] = x; + x = XEXP (XEXP (pat, 1), 2); + if (GET_CODE (x) != PC) goto L305; + do { insn = NEXT_INSN (insn); + if (insn == 0) goto L305; } + while (GET_CODE (insn) == NOTE + || (GET_CODE (insn) == INSN + && (GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER))); + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == BARRIER) + goto L305; + pat = PATTERN (insn); + x = pat; + if (GET_CODE (x) != PARALLEL) goto L305; + if (XVECLEN (x, 0) != 2) goto L305; + x = XVECEXP (pat, 0, 0); + if (GET_CODE (x) != SET) goto L305; + x = XEXP (XVECEXP (pat, 0, 0), 0); + if (GET_CODE (x) != PC) goto L305; + x = XEXP (XVECEXP (pat, 0, 0), 1); + if (GET_CODE (x) != IF_THEN_ELSE) goto L305; + x = XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0); + if (GET_CODE (x) != GE) goto L305; + x = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0); + if (GET_CODE (x) != PLUS) goto L305; + if (GET_MODE (x) != SImode) goto L305; + x = XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0), 0); + operands[0] = x; + if (! register_operand (x, SImode)) goto L305; + x = XEXP (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0), 1); + if (GET_CODE (x) != CONST_INT) goto L305; + if (XWINT (x, 0) != -1) goto L305; + x = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 1); + if (GET_CODE (x) != CONST_INT) goto L305; + if (XWINT (x, 0) != 0) goto L305; + x = XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1); + if (GET_CODE (x) != LABEL_REF) goto L305; + x = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0); + operands[1] = x; + x = XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 2); + if (GET_CODE (x) != PC) goto L305; + x = XVECEXP (pat, 0, 1); + if (GET_CODE (x) != SET) goto L305; + x = XEXP (XVECEXP (pat, 0, 1), 0); + if (!rtx_equal_p (operands[0], x)) goto L305; + x = XEXP (XVECEXP (pat, 0, 1), 1); + if (GET_CODE (x) != PLUS) goto L305; + if (GET_MODE (x) != SImode) goto L305; + x = XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0); + if (!rtx_equal_p (operands[0], x)) goto L305; + x = XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1); + if (GET_CODE (x) != CONST_INT) goto L305; + if (XWINT (x, 0) != -1) goto L305; + if (! (DATA_REG_P (operands[0]))) goto L305; + PATTERN (ins1) = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (4, operands)); + INSN_CODE (ins1) = 305; + delete_for_peephole (NEXT_INSN (ins1), insn); + return NEXT_INSN (insn); + L305: + + return 0; +} + +rtx peep_operand[4]; diff --git a/gnu/usr.bin/gcc2/arch/m68k/insn-recog.c b/gnu/usr.bin/gcc2/arch/m68k/insn-recog.c new file mode 100644 index 000000000000..1aea9785e4b5 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/insn-recog.c @@ -0,0 +1,6589 @@ +/* Generated automatically by the program `genrecog' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "recog.h" +#include "real.h" +#include "output.h" +#include "flags.h" + + +/* `recog' contains a decision tree + that recognizes whether the rtx X0 is a valid instruction. + + recog returns -1 if the rtx is not valid. + If the rtx is valid, recog returns a nonnegative number + which is the insn code number for the pattern that matched. + This is the same as the order in the machine description of + the entry that matched. This number can be used as an index into + entry that matched. This number can be used as an index into various + insn_* tables, such as insn_templates, insn_outfun, and insn_n_operands + (found in insn-output.c). + + The third argument to recog is an optional pointer to an int. + If present, recog will accept a pattern if it matches except for + missing CLOBBER expressions at the end. In that case, the value + pointed to by the optional pointer will be set to the number of + CLOBBERs that need to be added (it should be initialized to zero by + the caller). If it is set nonzero, the caller should allocate a + PARALLEL of the appropriate size, copy the initial entries, and call + add_clobbers (found in insn-emit.c) to fill in the CLOBBERs.*/ + +rtx recog_operand[MAX_RECOG_OPERANDS]; + +rtx *recog_operand_loc[MAX_RECOG_OPERANDS]; + +rtx *recog_dup_loc[MAX_DUP_OPERANDS]; + +char recog_dup_num[MAX_DUP_OPERANDS]; + +#define operands recog_operand + +int +recog_1 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case HImode: + switch (GET_CODE (x1)) + { + case TRUNCATE: + goto L628; + case ZERO_EXTEND: + goto L208; + case SIGN_EXTEND: + goto L220; + case FIX: + goto L313; + case PLUS: + goto L386; + case MINUS: + goto L455; + case MULT: + goto L501; + case DIV: + goto L623; + case UDIV: + goto L641; + case MOD: + goto L683; + case UMOD: + goto L701; + case AND: + goto L746; + case IOR: + goto L785; + case XOR: + goto L824; + case NEG: + goto L862; + case NOT: + goto L928; + } + } + if (general_operand (x1, HImode)) + { + ro[1] = x1; + return 30; + } + goto ret0; + + L628: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + switch (GET_CODE (x2)) + { + case DIV: + goto L629; + case UDIV: + goto L647; + case MOD: + goto L689; + case UMOD: + goto L707; + } + } + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 43; + } + goto ret0; + + L629: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L630; + } + goto ret0; + + L630: + x3 = XEXP (x2, 1); + switch (GET_CODE (x3)) + { + case SIGN_EXTEND: + if (GET_MODE (x3) == SImode && 1) + goto L631; + break; + case CONST_INT: + ro[2] = x3; + return 129; + } + goto ret0; + + L631: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, HImode)) + { + ro[2] = x4; + return 128; + } + goto ret0; + + L647: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L648; + } + goto ret0; + + L648: + x3 = XEXP (x2, 1); + switch (GET_CODE (x3)) + { + case ZERO_EXTEND: + if (GET_MODE (x3) == SImode && 1) + goto L649; + break; + case CONST_INT: + ro[2] = x3; + return 132; + } + goto ret0; + + L649: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, HImode)) + { + ro[2] = x4; + return 131; + } + goto ret0; + + L689: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L690; + } + goto ret0; + + L690: + x3 = XEXP (x2, 1); + switch (GET_CODE (x3)) + { + case SIGN_EXTEND: + if (GET_MODE (x3) == SImode && 1) + goto L691; + break; + case CONST_INT: + ro[2] = x3; + return 141; + } + goto ret0; + + L691: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, HImode)) + { + ro[2] = x4; + return 140; + } + goto ret0; + + L707: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L708; + } + goto ret0; + + L708: + x3 = XEXP (x2, 1); + switch (GET_CODE (x3)) + { + case ZERO_EXTEND: + if (GET_MODE (x3) == SImode && 1) + goto L709; + break; + case CONST_INT: + ro[2] = x3; + return 144; + } + goto ret0; + + L709: + x4 = XEXP (x3, 0); + if (nonimmediate_operand (x4, HImode)) + { + ro[2] = x4; + return 143; + } + goto ret0; + + L208: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return 48; + } + goto ret0; + + L220: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 51; + } + goto ret0; + + L313: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == FIX && 1) + goto L314; + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 76; + } + L357: + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 79; + } + goto ret0; + + L314: + x3 = XEXP (x2, 0); + if (pnum_clobbers != 0 && register_operand (x3, DFmode)) + { + ro[1] = x3; + if (TARGET_68040) + { + *pnum_clobbers = 2; + return 71; + } + } + goto ret0; + + L386: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L387; + } + goto ret0; + + L387: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 85; + } + goto ret0; + + L455: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L456; + } + goto ret0; + + L456: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 99; + } + goto ret0; + + L501: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L502; + } + goto ret0; + + L502: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 109; + } + goto ret0; + + L623: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L624; + } + goto ret0; + + L624: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 127; + } + goto ret0; + + L641: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L642; + } + goto ret0; + + L642: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 130; + } + goto ret0; + + L683: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L684; + } + goto ret0; + + L684: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 139; + } + goto ret0; + + L701: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L702; + } + goto ret0; + + L702: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 142; + } + goto ret0; + + L746: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L747; + } + goto ret0; + + L747: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 148; + } + goto ret0; + + L785: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L786; + } + goto ret0; + + L786: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 155; + } + goto ret0; + + L824: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L825; + } + goto ret0; + + L825: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 162; + } + goto ret0; + + L862: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 169; + } + goto ret0; + + L928: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 187; + } + goto ret0; + ret0: return -1; +} + +int +recog_2 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case QImode: + switch (GET_CODE (x1)) + { + case TRUNCATE: + goto L192; + case FIX: + goto L328; + case PLUS: + goto L403; + case MINUS: + goto L466; + case AND: + goto L763; + case IOR: + goto L802; + case XOR: + goto L841; + case NEG: + goto L871; + case NOT: + goto L937; + case EQ: + goto L1275; + case NE: + goto L1280; + case GT: + goto L1285; + case GTU: + goto L1290; + case LT: + goto L1295; + case LTU: + goto L1300; + case GE: + goto L1305; + case GEU: + goto L1310; + case LE: + goto L1315; + case LEU: + goto L1320; + } + } + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 32; + } + goto ret0; + + L192: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 41; + } + L196: + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 42; + } + goto ret0; + + L328: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == FIX && 1) + goto L329; + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 75; + } + L353: + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 78; + } + goto ret0; + + L329: + x3 = XEXP (x2, 0); + if (pnum_clobbers != 0 && register_operand (x3, DFmode)) + { + ro[1] = x3; + if (TARGET_68040) + { + *pnum_clobbers = 2; + return 72; + } + } + goto ret0; + + L403: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L404; + } + goto ret0; + + L404: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 88; + } + goto ret0; + + L466: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L467; + } + goto ret0; + + L467: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 101; + } + goto ret0; + + L763: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L764; + } + goto ret0; + + L764: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 151; + } + goto ret0; + + L802: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L803; + } + goto ret0; + + L803: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 158; + } + goto ret0; + + L841: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L842; + } + goto ret0; + + L842: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 165; + } + goto ret0; + + L871: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 171; + } + goto ret0; + + L937: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 189; + } + goto ret0; + + L1275: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1276; + goto ret0; + + L1276: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 248; + goto ret0; + + L1280: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1281; + goto ret0; + + L1281: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 249; + goto ret0; + + L1285: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1286; + goto ret0; + + L1286: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 250; + goto ret0; + + L1290: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1291; + goto ret0; + + L1291: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 251; + goto ret0; + + L1295: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1296; + goto ret0; + + L1296: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 252; + goto ret0; + + L1300: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1301; + goto ret0; + + L1301: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 253; + goto ret0; + + L1305: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1306; + goto ret0; + + L1306: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 254; + goto ret0; + + L1310: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1311; + goto ret0; + + L1311: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 255; + goto ret0; + + L1315: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1316; + goto ret0; + + L1316: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 256; + goto ret0; + + L1320: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1321; + goto ret0; + + L1321: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 257; + goto ret0; + ret0: return -1; +} + +int +recog_3 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != SImode) + goto ret0; + switch (GET_CODE (x1)) + { + case PLUS: + goto L375; + case MINUS: + goto L444; + case MULT: + goto L506; + case IOR: + goto L780; + case XOR: + goto L819; + case NEG: + goto L858; + case NOT: + goto L924; + case ZERO_EXTRACT: + goto L1168; + case SIGN_EXTRACT: + goto L1180; + } + goto ret0; + + L375: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L381; + } + goto ret0; + + L381: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == SIGN_EXTEND && 1) + goto L382; + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 83; + } + goto ret0; + + L382: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, HImode)) + { + ro[2] = x3; + return 84; + } + goto ret0; + + L444: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L450; + } + goto ret0; + + L450: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == SIGN_EXTEND && 1) + goto L451; + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 97; + } + goto ret0; + + L451: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, HImode)) + { + ro[2] = x3; + return 98; + } + goto ret0; + + L506: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + switch (GET_CODE (x2)) + { + case SIGN_EXTEND: + goto L507; + case ZERO_EXTEND: + goto L525; + } + } + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L520; + } + goto ret0; + + L507: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, HImode)) + { + ro[1] = x3; + goto L508; + } + goto ret0; + + L508: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case SIGN_EXTEND: + if (GET_MODE (x2) == SImode && 1) + goto L509; + break; + case CONST_INT: + ro[2] = x2; + if (INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff) + return 111; + } + goto ret0; + + L509: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, HImode)) + { + ro[2] = x3; + return 110; + } + goto ret0; + + L525: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, HImode)) + { + ro[1] = x3; + goto L526; + } + goto ret0; + + L526: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case ZERO_EXTEND: + if (GET_MODE (x2) == SImode && 1) + goto L527; + break; + case CONST_INT: + ro[2] = x2; + if (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff) + return 114; + } + goto ret0; + + L527: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, HImode)) + { + ro[2] = x3; + return 113; + } + goto ret0; + + L520: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + if (TARGET_68020) + return 112; + } + goto ret0; + + L780: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L781; + } + goto ret0; + + L781: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 154; + } + goto ret0; + + L819: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L820; + } + goto ret0; + + L820: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 161; + } + goto ret0; + + L858: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 168; + } + goto ret0; + + L924: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 186; + } + goto ret0; + + L1168: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + goto L1169; + } + break; + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[1] = x2; + goto L1175; + } + } + goto ret0; + + L1169: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + goto L1170; + } + L1199: + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L1200; + } + goto ret0; + + L1170: + x2 = XEXP (x1, 2); + if (immediate_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) == 32) + && GET_CODE (operands[3]) == CONST_INT + && (INTVAL (operands[3]) % 8) == 0 + && ! mode_dependent_address_p (XEXP (operands[1], 0))) + return 231; + } + x2 = XEXP (x1, 1); + goto L1199; + + L1200: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68020 && TARGET_BITFIELD) + return 236; + } + goto ret0; + + L1175: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + goto L1176; + } + L1240: + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L1241; + } + goto ret0; + + L1176: + x2 = XEXP (x1, 2); + if (immediate_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) + && GET_CODE (operands[3]) == CONST_INT + && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 + && (GET_CODE (operands[1]) == REG + || ! mode_dependent_address_p (XEXP (operands[1], 0)))) + return 232; + } + x2 = XEXP (x1, 1); + goto L1240; + + L1241: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68020 && TARGET_BITFIELD) + return 242; + } + goto ret0; + + L1180: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + goto L1181; + } + break; + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[1] = x2; + goto L1187; + } + } + goto ret0; + + L1181: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + goto L1182; + } + L1193: + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L1194; + } + goto ret0; + + L1182: + x2 = XEXP (x1, 2); + if (immediate_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) == 32) + && GET_CODE (operands[3]) == CONST_INT + && (INTVAL (operands[3]) % 8) == 0 + && ! mode_dependent_address_p (XEXP (operands[1], 0))) + return 233; + } + x2 = XEXP (x1, 1); + goto L1193; + + L1194: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68020 && TARGET_BITFIELD) + return 235; + } + goto ret0; + + L1187: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + goto L1188; + } + L1234: + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L1235; + } + goto ret0; + + L1188: + x2 = XEXP (x1, 2); + if (immediate_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) + && GET_CODE (operands[3]) == CONST_INT + && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 + && (GET_CODE (operands[1]) == REG + || ! mode_dependent_address_p (XEXP (operands[1], 0)))) + return 234; + } + x2 = XEXP (x1, 1); + goto L1234; + + L1235: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68020 && TARGET_BITFIELD) + return 241; + } + goto ret0; + ret0: return -1; +} + +int +recog_4 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (general_operand (x2, HImode)) + { + ro[0] = x2; + goto L391; + } + L967: + if (register_operand (x2, HImode)) + { + ro[0] = x2; + goto L968; + } + break; + case QImode: + if (general_operand (x2, QImode)) + { + ro[0] = x2; + goto L408; + } + L978: + if (register_operand (x2, QImode)) + { + ro[0] = x2; + goto L979; + } + } + goto ret0; + + L391: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case HImode: + switch (GET_CODE (x1)) + { + case PLUS: + goto L392; + case MINUS: + goto L461; + case AND: + goto L752; + case IOR: + goto L791; + case XOR: + goto L830; + case NEG: + goto L867; + case NOT: + goto L933; + } + } + if (general_operand (x1, HImode)) + { + ro[1] = x1; + return 31; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L392: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L393; + L398: + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L399; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L393: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 86; + } + x2 = XEXP (x1, 0); + goto L398; + + L399: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 87; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L461: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L462; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L462: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 100; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L752: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L753; + L758: + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L759; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L753: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 149; + } + x2 = XEXP (x1, 0); + goto L758; + + L759: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 150; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L791: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L792; + L797: + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L798; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L792: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 156; + } + x2 = XEXP (x1, 0); + goto L797; + + L798: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 157; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L830: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L831; + L836: + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L837; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L831: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 163; + } + x2 = XEXP (x1, 0); + goto L836; + + L837: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 164; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L867: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + return 170; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L933: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + return 188; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L967; + + L968: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != HImode) + goto ret0; + switch (GET_CODE (x1)) + { + case ASHIFT: + goto L969; + case ASHIFTRT: + goto L1008; + case LSHIFT: + goto L1047; + case LSHIFTRT: + goto L1086; + case ROTATE: + goto L1113; + case ROTATERT: + goto L1140; + } + goto ret0; + + L969: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L970; + goto ret0; + + L970: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 195; + } + goto ret0; + + L1008: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1009; + goto ret0; + + L1009: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 202; + } + goto ret0; + + L1047: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1048; + goto ret0; + + L1048: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 209; + } + goto ret0; + + L1086: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1087; + goto ret0; + + L1087: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 216; + } + goto ret0; + + L1113: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1114; + goto ret0; + + L1114: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 221; + } + goto ret0; + + L1140: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1141; + goto ret0; + + L1141: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 226; + } + goto ret0; + + L408: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case QImode: + switch (GET_CODE (x1)) + { + case PLUS: + goto L409; + case MINUS: + goto L472; + case AND: + goto L769; + case IOR: + goto L808; + case XOR: + goto L847; + case NEG: + goto L876; + case NOT: + goto L942; + } + } + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 33; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L409: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L410; + L415: + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L416; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L410: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 89; + } + x2 = XEXP (x1, 0); + goto L415; + + L416: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 90; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L472: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L473; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L473: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 102; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L769: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L770; + L775: + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L776; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L770: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 152; + } + x2 = XEXP (x1, 0); + goto L775; + + L776: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 153; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L808: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L809; + L814: + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L815; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L809: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 159; + } + x2 = XEXP (x1, 0); + goto L814; + + L815: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 160; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L847: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L848; + L853: + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L854; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L848: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 166; + } + x2 = XEXP (x1, 0); + goto L853; + + L854: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 167; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L876: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + return 172; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L942: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + return 190; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L978; + + L979: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != QImode) + goto ret0; + switch (GET_CODE (x1)) + { + case ASHIFT: + goto L980; + case ASHIFTRT: + goto L1019; + case LSHIFT: + goto L1058; + case LSHIFTRT: + goto L1097; + case ROTATE: + goto L1124; + case ROTATERT: + goto L1151; + } + goto ret0; + + L980: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L981; + goto ret0; + + L981: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 197; + } + goto ret0; + + L1019: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1020; + goto ret0; + + L1020: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 204; + } + goto ret0; + + L1058: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1059; + goto ret0; + + L1059: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 211; + } + goto ret0; + + L1097: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1098; + goto ret0; + + L1098: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 218; + } + goto ret0; + + L1124: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1125; + goto ret0; + + L1125: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 223; + } + goto ret0; + + L1151: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1152; + goto ret0; + + L1152: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 228; + } + goto ret0; + ret0: return -1; +} + +int +recog_5 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 1); + x2 = XEXP (x1, 0); + switch (GET_CODE (x2)) + { + case EQ: + goto L1326; + case NE: + goto L1335; + case GT: + goto L1344; + case GTU: + goto L1353; + case LT: + goto L1362; + case LTU: + goto L1371; + case GE: + goto L1380; + case GEU: + goto L1389; + case LE: + goto L1398; + case LEU: + goto L1407; + } + goto ret0; + + L1326: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L1327; + goto ret0; + + L1327: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L1328; + goto ret0; + + L1328: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L1329; + case PC: + goto L1419; + } + goto ret0; + + L1329: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L1330; + + L1330: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 258; + goto ret0; + + L1419: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1420; + goto ret0; + + L1420: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 268; + + L1335: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L1336; + goto ret0; + + L1336: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L1337; + goto ret0; + + L1337: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L1338; + case PC: + goto L1428; + } + goto ret0; + + L1338: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L1339; + + L1339: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 259; + goto ret0; + + L1428: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1429; + goto ret0; + + L1429: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 269; + + L1344: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L1345; + goto ret0; + + L1345: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L1346; + goto ret0; + + L1346: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L1347; + case PC: + goto L1437; + } + goto ret0; + + L1347: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L1348; + + L1348: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 260; + goto ret0; + + L1437: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1438; + goto ret0; + + L1438: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 270; + + L1353: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L1354; + goto ret0; + + L1354: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L1355; + goto ret0; + + L1355: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L1356; + case PC: + goto L1446; + } + goto ret0; + + L1356: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L1357; + + L1357: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 261; + goto ret0; + + L1446: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1447; + goto ret0; + + L1447: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 271; + + L1362: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L1363; + goto ret0; + + L1363: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L1364; + goto ret0; + + L1364: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L1365; + case PC: + goto L1455; + } + goto ret0; + + L1365: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L1366; + + L1366: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 262; + goto ret0; + + L1455: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1456; + goto ret0; + + L1456: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 272; + + L1371: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L1372; + goto ret0; + + L1372: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L1373; + goto ret0; + + L1373: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L1374; + case PC: + goto L1464; + } + goto ret0; + + L1374: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L1375; + + L1375: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 263; + goto ret0; + + L1464: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1465; + goto ret0; + + L1465: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 273; + + L1380: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L1381; + goto ret0; + + L1381: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L1382; + goto ret0; + + L1382: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L1383; + case PC: + goto L1473; + } + goto ret0; + + L1383: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L1384; + + L1384: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 264; + goto ret0; + + L1473: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1474; + goto ret0; + + L1474: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 274; + + L1389: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L1390; + goto ret0; + + L1390: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L1391; + goto ret0; + + L1391: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L1392; + case PC: + goto L1482; + } + goto ret0; + + L1392: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L1393; + + L1393: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 265; + goto ret0; + + L1482: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1483; + goto ret0; + + L1483: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 275; + + L1398: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L1399; + goto ret0; + + L1399: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L1400; + goto ret0; + + L1400: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L1401; + case PC: + goto L1491; + } + goto ret0; + + L1401: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L1402; + + L1402: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 266; + goto ret0; + + L1491: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1492; + goto ret0; + + L1492: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 276; + + L1407: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L1408; + goto ret0; + + L1408: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L1409; + goto ret0; + + L1409: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L1410; + case PC: + goto L1500; + } + goto ret0; + + L1410: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L1411; + + L1411: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 267; + goto ret0; + + L1500: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1501; + goto ret0; + + L1501: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 277; + ret0: return -1; +} + +int +recog_6 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XEXP (x0, 0); + switch (GET_MODE (x1)) + { + case DFmode: + if (GET_CODE (x1) == MEM && push_operand (x1, DFmode)) + { + ro[0] = x1; + goto L2; + } + L173: + if (general_operand (x1, DFmode)) + { + ro[0] = x1; + goto L227; + } + break; + case DImode: + if (GET_CODE (x1) == MEM && push_operand (x1, DImode)) + { + ro[0] = x1; + goto L5; + } + L184: + if (general_operand (x1, DImode)) + { + ro[0] = x1; + goto L185; + } + break; + case SImode: + if (GET_CODE (x1) == MEM && push_operand (x1, SImode)) + { + ro[0] = x1; + goto L148; + } + L150: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + goto L203; + } + break; + case HImode: + if (general_operand (x1, HImode)) + { + ro[0] = x1; + goto L199; + } + L961: + if (register_operand (x1, HImode)) + { + ro[0] = x1; + goto L962; + } + break; + case QImode: + if (general_operand (x1, QImode)) + { + ro[0] = x1; + goto L191; + } + L972: + if (register_operand (x1, QImode)) + { + ro[0] = x1; + goto L973; + } + break; + case SFmode: + if (general_operand (x1, SFmode)) + { + ro[0] = x1; + goto L237; + } + break; + case XFmode: + if (nonimmediate_operand (x1, XFmode)) + { + ro[0] = x1; + goto L177; + } + } + L187: + switch (GET_MODE (x1)) + { + case SImode: + switch (GET_CODE (x1)) + { + case MEM: + if (push_operand (x1, SImode)) + { + ro[0] = x1; + goto L188; + } + break; + case ZERO_EXTRACT: + goto L1155; + } + L373: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + goto L374; + } + L739: + if (not_sp_operand (x1, SImode)) + { + ro[0] = x1; + goto L740; + } + L944: + if (register_operand (x1, SImode)) + { + ro[0] = x1; + goto L945; + } + } + switch (GET_CODE (x1)) + { + case CC0: + goto L8; + case STRICT_LOW_PART: + goto L160; + case PC: + goto L1324; + } + L1595: + ro[0] = x1; + goto L1596; + L1612: + switch (GET_CODE (x1)) + { + case PC: + goto L1613; + case CC0: + goto L1703; + } + switch (GET_MODE (x1)) + { + case SImode: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + goto L1751; + } + break; + case DFmode: + if (register_operand (x1, DFmode)) + { + ro[0] = x1; + goto L1619; + } + L1718: + if (general_operand (x1, DFmode)) + { + ro[0] = x1; + goto L1719; + } + break; + case SFmode: + if (register_operand (x1, SFmode)) + { + ro[0] = x1; + goto L1626; + } + L1722: + if (general_operand (x1, SFmode)) + { + ro[0] = x1; + goto L1723; + } + break; + case XFmode: + if (general_operand (x1, XFmode)) + { + ro[0] = x1; + goto L1711; + } + break; + case QImode: + if (general_operand (x1, QImode)) + { + ro[0] = x1; + goto L1743; + } + break; + case HImode: + if (general_operand (x1, HImode)) + { + ro[0] = x1; + goto L1747; + } + } + goto ret0; + + L2: + x1 = XEXP (x0, 1); + if (general_operand (x1, DFmode)) + { + ro[1] = x1; + return 0; + } + x1 = XEXP (x0, 0); + goto L173; + + L227: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case DFmode: + switch (GET_CODE (x1)) + { + case FLOAT_EXTEND: + goto L228; + case FLOAT: + goto L262; + case FIX: + goto L333; + case PLUS: + goto L420; + case MINUS: + goto L477; + case MULT: + goto L599; + case DIV: + goto L659; + case NEG: + goto L890; + case SQRT: + goto L900; + case ABS: + goto L914; + } + } + if (general_operand (x1, DFmode)) + { + ro[1] = x1; + return 35; + } + x1 = XEXP (x0, 0); + goto L1595; + + L228: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + goto L233; + x1 = XEXP (x0, 0); + goto L1595; + + L233: + ro[1] = x2; + if (TARGET_FPA) + return 54; + L234: + ro[1] = x2; + if (TARGET_68881) + return 55; + x1 = XEXP (x0, 0); + goto L1595; + + L262: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + goto L267; + L276: + if (general_operand (x2, HImode)) + { + ro[1] = x2; + if (TARGET_68881) + return 67; + } + L284: + if (general_operand (x2, QImode)) + { + ro[1] = x2; + if (TARGET_68881) + return 69; + } + x1 = XEXP (x0, 0); + goto L1595; + + L267: + ro[1] = x2; + if (TARGET_FPA) + return 64; + L268: + ro[1] = x2; + if (TARGET_68881) + return 65; + goto L276; + + L333: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_68881 && !TARGET_68040) + return 73; + } + x1 = XEXP (x0, 0); + goto L1595; + + L420: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L421; + } + x1 = XEXP (x0, 0); + goto L1595; + + L421: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + goto L427; + x1 = XEXP (x0, 0); + goto L1595; + + L427: + ro[2] = x2; + if (TARGET_FPA) + return 92; + L428: + ro[2] = x2; + if (TARGET_68881) + return 93; + x1 = XEXP (x0, 0); + goto L1595; + + L477: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L478; + } + x1 = XEXP (x0, 0); + goto L1595; + + L478: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + goto L484; + x1 = XEXP (x0, 0); + goto L1595; + + L484: + ro[2] = x2; + if (TARGET_FPA) + return 104; + L485: + ro[2] = x2; + if (TARGET_68881) + return 105; + x1 = XEXP (x0, 0); + goto L1595; + + L599: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L600; + } + x1 = XEXP (x0, 0); + goto L1595; + + L600: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + goto L606; + x1 = XEXP (x0, 0); + goto L1595; + + L606: + ro[2] = x2; + if (TARGET_FPA) + return 122; + L607: + ro[2] = x2; + if (TARGET_68881) + return 123; + x1 = XEXP (x0, 0); + goto L1595; + + L659: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L660; + } + x1 = XEXP (x0, 0); + goto L1595; + + L660: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + goto L666; + x1 = XEXP (x0, 0); + goto L1595; + + L666: + ro[2] = x2; + if (TARGET_FPA) + return 134; + L667: + ro[2] = x2; + if (TARGET_68881) + return 135; + x1 = XEXP (x0, 0); + goto L1595; + + L890: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + goto L895; + x1 = XEXP (x0, 0); + goto L1595; + + L895: + ro[1] = x2; + if (TARGET_FPA) + return 177; + L896: + ro[1] = x2; + if (TARGET_68881) + return 178; + x1 = XEXP (x0, 0); + goto L1595; + + L900: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 179; + } + x1 = XEXP (x0, 0); + goto L1595; + + L914: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + goto L919; + x1 = XEXP (x0, 0); + goto L1595; + + L919: + ro[1] = x2; + if (TARGET_FPA) + return 184; + L920: + ro[1] = x2; + if (TARGET_68881) + return 185; + x1 = XEXP (x0, 0); + goto L1595; + + L5: + x1 = XEXP (x0, 1); + if (general_operand (x1, DImode)) + { + ro[1] = x1; + return 1; + } + x1 = XEXP (x0, 0); + goto L184; + + L185: + x1 = XEXP (x0, 1); + if (general_operand (x1, DImode)) + { + ro[1] = x1; + return 39; + } + x1 = XEXP (x0, 0); + goto L1595; + + L148: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + { + ro[1] = x1; + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >= -0x8000 + && INTVAL (operands[1]) < 0x8000) + return 26; + } + x1 = XEXP (x0, 0); + goto L150; + + L203: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SImode: + switch (GET_CODE (x1)) + { + case ZERO_EXTEND: + goto L204; + case SIGN_EXTEND: + goto L216; + case FIX: + goto L298; + } + } + if (GET_CODE (x1) == CONST_INT && XWINT (x1, 0) == 0 && 1) + if ((TARGET_68020 + || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) + return 27; + L154: + if (general_operand (x1, SImode)) + { + ro[1] = x1; + return 29; + } + x1 = XEXP (x0, 0); + goto L187; + + L204: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[1] = x2; + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return 47; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return 49; + } + } + x1 = XEXP (x0, 0); + goto L187; + + L216: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[1] = x2; + return 50; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + if (TARGET_68020) + return 52; + } + } + x1 = XEXP (x0, 0); + goto L187; + + L298: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DFmode: + switch (GET_CODE (x2)) + { + case FIX: + goto L299; + } + break; + case SFmode: + if (GET_CODE (x2) == FIX && 1) + goto L366; + } + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 77; + } + L361: + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 80; + } + x1 = XEXP (x0, 0); + goto L187; + + L299: + x3 = XEXP (x2, 0); + if (pnum_clobbers != 0 && register_operand (x3, DFmode)) + { + ro[1] = x3; + if (TARGET_68040) + { + *pnum_clobbers = 2; + return 70; + } + } + L371: + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + if (TARGET_FPA) + return 82; + } + x1 = XEXP (x0, 0); + goto L187; + + L366: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_FPA) + return 81; + } + x1 = XEXP (x0, 0); + goto L187; + L199: + tem = recog_1 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L961; + + L962: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != HImode) + { + x1 = XEXP (x0, 0); + goto L1595; + } + switch (GET_CODE (x1)) + { + case ASHIFT: + goto L963; + case ASHIFTRT: + goto L1002; + case LSHIFT: + goto L1041; + case LSHIFTRT: + goto L1080; + case ROTATE: + goto L1107; + case ROTATERT: + goto L1134; + } + x1 = XEXP (x0, 0); + goto L1595; + + L963: + x2 = XEXP (x1, 0); + if (register_operand (x2, HImode)) + { + ro[1] = x2; + goto L964; + } + x1 = XEXP (x0, 0); + goto L1595; + + L964: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 194; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1002: + x2 = XEXP (x1, 0); + if (register_operand (x2, HImode)) + { + ro[1] = x2; + goto L1003; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1003: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 201; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1041: + x2 = XEXP (x1, 0); + if (register_operand (x2, HImode)) + { + ro[1] = x2; + goto L1042; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1042: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 208; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1080: + x2 = XEXP (x1, 0); + if (register_operand (x2, HImode)) + { + ro[1] = x2; + goto L1081; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1081: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 215; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1107: + x2 = XEXP (x1, 0); + if (register_operand (x2, HImode)) + { + ro[1] = x2; + goto L1108; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1108: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 220; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1134: + x2 = XEXP (x1, 0); + if (register_operand (x2, HImode)) + { + ro[1] = x2; + goto L1135; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1135: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 225; + } + x1 = XEXP (x0, 0); + goto L1595; + L191: + tem = recog_2 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L972; + + L973: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != QImode) + { + x1 = XEXP (x0, 0); + goto L1595; + } + switch (GET_CODE (x1)) + { + case ASHIFT: + goto L974; + case ASHIFTRT: + goto L1013; + case LSHIFT: + goto L1052; + case LSHIFTRT: + goto L1091; + case ROTATE: + goto L1118; + case ROTATERT: + goto L1145; + } + x1 = XEXP (x0, 0); + goto L1595; + + L974: + x2 = XEXP (x1, 0); + if (register_operand (x2, QImode)) + { + ro[1] = x2; + goto L975; + } + x1 = XEXP (x0, 0); + goto L1595; + + L975: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 196; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1013: + x2 = XEXP (x1, 0); + if (register_operand (x2, QImode)) + { + ro[1] = x2; + goto L1014; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1014: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 203; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1052: + x2 = XEXP (x1, 0); + if (register_operand (x2, QImode)) + { + ro[1] = x2; + goto L1053; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1053: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 210; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1091: + x2 = XEXP (x1, 0); + if (register_operand (x2, QImode)) + { + ro[1] = x2; + goto L1092; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1092: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 217; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1118: + x2 = XEXP (x1, 0); + if (register_operand (x2, QImode)) + { + ro[1] = x2; + goto L1119; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1119: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 222; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1145: + x2 = XEXP (x1, 0); + if (register_operand (x2, QImode)) + { + ro[1] = x2; + goto L1146; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1146: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 227; + } + x1 = XEXP (x0, 0); + goto L1595; + + L237: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SFmode: + switch (GET_CODE (x1)) + { + case FLOAT_TRUNCATE: + goto L238; + case FLOAT: + goto L252; + case FIX: + goto L337; + case PLUS: + goto L432; + case MINUS: + goto L489; + case MULT: + goto L611; + case DIV: + goto L671; + case NEG: + goto L880; + case ABS: + goto L904; + } + } + if (general_operand (x1, SFmode)) + { + ro[1] = x1; + return 34; + } + x1 = XEXP (x0, 0); + goto L1595; + + L238: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + goto L243; + L248: + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 59; + } + x1 = XEXP (x0, 0); + goto L1595; + + L243: + ro[1] = x2; + if (TARGET_FPA) + return 57; + L244: + ro[1] = x2; + if (TARGET_68040_ONLY) + return 58; + goto L248; + + L252: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + goto L257; + L272: + if (general_operand (x2, HImode)) + { + ro[1] = x2; + if (TARGET_68881) + return 66; + } + L280: + if (general_operand (x2, QImode)) + { + ro[1] = x2; + if (TARGET_68881) + return 68; + } + x1 = XEXP (x0, 0); + goto L1595; + + L257: + ro[1] = x2; + if (TARGET_FPA) + return 61; + L258: + ro[1] = x2; + if (TARGET_68881) + return 62; + goto L272; + + L337: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_68881 && !TARGET_68040) + return 74; + } + x1 = XEXP (x0, 0); + goto L1595; + + L432: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L433; + } + x1 = XEXP (x0, 0); + goto L1595; + + L433: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + goto L439; + x1 = XEXP (x0, 0); + goto L1595; + + L439: + ro[2] = x2; + if (TARGET_FPA) + return 95; + L440: + ro[2] = x2; + if (TARGET_68881) + return 96; + x1 = XEXP (x0, 0); + goto L1595; + + L489: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L490; + } + x1 = XEXP (x0, 0); + goto L1595; + + L490: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + goto L496; + x1 = XEXP (x0, 0); + goto L1595; + + L496: + ro[2] = x2; + if (TARGET_FPA) + return 107; + L497: + ro[2] = x2; + if (TARGET_68881) + return 108; + x1 = XEXP (x0, 0); + goto L1595; + + L611: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L612; + } + x1 = XEXP (x0, 0); + goto L1595; + + L612: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + goto L618; + x1 = XEXP (x0, 0); + goto L1595; + + L618: + ro[2] = x2; + if (TARGET_FPA) + return 125; + L619: + ro[2] = x2; + if (TARGET_68881) + return 126; + x1 = XEXP (x0, 0); + goto L1595; + + L671: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L672; + } + x1 = XEXP (x0, 0); + goto L1595; + + L672: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + goto L678; + x1 = XEXP (x0, 0); + goto L1595; + + L678: + ro[2] = x2; + if (TARGET_FPA) + return 137; + L679: + ro[2] = x2; + if (TARGET_68881) + return 138; + x1 = XEXP (x0, 0); + goto L1595; + + L880: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + goto L885; + x1 = XEXP (x0, 0); + goto L1595; + + L885: + ro[1] = x2; + if (TARGET_FPA) + return 174; + L886: + ro[1] = x2; + if (TARGET_68881) + return 175; + x1 = XEXP (x0, 0); + goto L1595; + + L904: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + goto L909; + x1 = XEXP (x0, 0); + goto L1595; + + L909: + ro[1] = x2; + if (TARGET_FPA) + return 181; + L910: + ro[1] = x2; + if (TARGET_68881) + return 182; + x1 = XEXP (x0, 0); + goto L1595; + + L177: + x1 = XEXP (x0, 1); + if (nonimmediate_operand (x1, XFmode)) + goto L181; + x1 = XEXP (x0, 0); + goto L1595; + + L181: + ro[1] = x1; + if (TARGET_68881) + return 37; + L182: + ro[1] = x1; + if (! TARGET_68881) + return 38; + x1 = XEXP (x0, 0); + goto L1595; + + L188: + x1 = XEXP (x0, 1); + if (address_operand (x1, SImode)) + { + ro[1] = x1; + return 40; + } + x1 = XEXP (x0, 0); + goto L373; + + L1155: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[0] = x2; + goto L1156; + } + break; + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[0] = x2; + goto L1162; + } + } + goto L739; + + L1156: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + { + ro[1] = x2; + goto L1157; + } + L1204: + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L1205; + } + goto L739; + + L1157: + x2 = XEXP (x1, 2); + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + goto L1158; + } + x2 = XEXP (x1, 1); + goto L1204; + + L1158: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + { + ro[3] = x1; + if (TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[1]) == CONST_INT + && (INTVAL (operands[1]) == 32) + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) % 8) == 0 + && ! mode_dependent_address_p (XEXP (operands[0], 0))) + return 229; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 1); + goto L1204; + + L1205: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L1206; + } + goto L739; + + L1206: + x1 = XEXP (x0, 1); + switch (GET_CODE (x1)) + { + case XOR: + if (GET_MODE (x1) == SImode && 1) + goto L1207; + break; + case CONST_INT: + if (XWINT (x1, 0) == 0 && 1) + if (TARGET_68020 && TARGET_BITFIELD) + return 238; + if (XWINT (x1, 0) == -1 && 1) + if (TARGET_68020 && TARGET_BITFIELD) + return 239; + } + L1229: + if (general_operand (x1, SImode)) + { + ro[3] = x1; + if (TARGET_68020 && TARGET_BITFIELD) + return 240; + } + x1 = XEXP (x0, 0); + goto L739; + + L1207: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == ZERO_EXTRACT && 1) + goto L1208; + x1 = XEXP (x0, 0); + goto L739; + + L1208: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[0]) && 1) + goto L1209; + x1 = XEXP (x0, 0); + goto L739; + + L1209: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L1210; + x1 = XEXP (x0, 0); + goto L739; + + L1210: + x3 = XEXP (x2, 2); + if (rtx_equal_p (x3, ro[2]) && 1) + goto L1211; + x1 = XEXP (x0, 0); + goto L739; + + L1211: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, VOIDmode)) + { + ro[3] = x2; + if (TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[3]) == CONST_INT + && (INTVAL (operands[3]) == -1 + || (GET_CODE (operands[1]) == CONST_INT + && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))) + return 237; + } + x1 = XEXP (x0, 0); + goto L739; + + L1162: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + { + ro[1] = x2; + goto L1163; + } + L1245: + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L1246; + } + goto L739; + + L1163: + x2 = XEXP (x1, 2); + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + goto L1164; + } + x2 = XEXP (x1, 1); + goto L1245; + + L1164: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + { + ro[3] = x1; + if (TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[1]) == CONST_INT + && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 + && (GET_CODE (operands[0]) == REG + || ! mode_dependent_address_p (XEXP (operands[0], 0)))) + return 230; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 1); + goto L1245; + + L1246: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L1247; + } + goto L739; + + L1247: + x1 = XEXP (x0, 1); + switch (GET_CODE (x1)) + { + case CONST_INT: + if (XWINT (x1, 0) == 0 && 1) + if (TARGET_68020 && TARGET_BITFIELD) + return 243; + if (XWINT (x1, 0) == -1 && 1) + if (TARGET_68020 && TARGET_BITFIELD) + return 244; + } + L1259: + if (general_operand (x1, SImode)) + { + ro[3] = x1; + if (TARGET_68020 && TARGET_BITFIELD) + return 245; + } + x1 = XEXP (x0, 0); + goto L739; + L374: + tem = recog_3 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L739; + + L740: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == SImode && GET_CODE (x1) == AND && 1) + goto L741; + x1 = XEXP (x0, 0); + goto L944; + + L741: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L742; + } + x1 = XEXP (x0, 0); + goto L944; + + L742: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 147; + } + x1 = XEXP (x0, 0); + goto L944; + + L945: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != SImode) + { + x1 = XEXP (x0, 0); + goto L1595; + } + switch (GET_CODE (x1)) + { + case ASHIFT: + goto L946; + case ASHIFTRT: + goto L985; + case LSHIFT: + goto L1024; + case LSHIFTRT: + goto L1063; + case ROTATE: + goto L1102; + case ROTATERT: + goto L1129; + } + x1 = XEXP (x0, 0); + goto L1595; + + L946: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[1] = x2; + goto L947; + } + x1 = XEXP (x0, 0); + goto L1595; + + L947: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + goto L953; + L959: + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 193; + } + x1 = XEXP (x0, 0); + goto L1595; + + L953: + ro[2] = x2; + if ((GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)) + return 191; + L954: + ro[2] = x2; + if ((! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)) + return 192; + goto L959; + + L985: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[1] = x2; + goto L986; + } + x1 = XEXP (x0, 0); + goto L1595; + + L986: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + goto L992; + L998: + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 200; + } + x1 = XEXP (x0, 0); + goto L1595; + + L992: + ro[2] = x2; + if ((GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)) + return 198; + L993: + ro[2] = x2; + if ((! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)) + return 199; + goto L998; + + L1024: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[1] = x2; + goto L1025; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1025: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + goto L1031; + L1037: + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 207; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1031: + ro[2] = x2; + if ((GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)) + return 205; + L1032: + ro[2] = x2; + if ((! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)) + return 206; + goto L1037; + + L1063: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[1] = x2; + goto L1064; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1064: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + goto L1070; + L1076: + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 214; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1070: + ro[2] = x2; + if ((GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)) + return 212; + L1071: + ro[2] = x2; + if ((! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)) + return 213; + goto L1076; + + L1102: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[1] = x2; + goto L1103; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1103: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 219; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1129: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[1] = x2; + goto L1130; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1130: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 224; + } + x1 = XEXP (x0, 0); + goto L1595; + + L8: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SImode: + if (nonimmediate_operand (x1, SImode)) + { + ro[0] = x1; + return 2; + } + break; + case HImode: + if (nonimmediate_operand (x1, HImode)) + { + ro[0] = x1; + return 3; + } + break; + case QImode: + if (nonimmediate_operand (x1, QImode)) + { + ro[0] = x1; + return 4; + } + } + switch (GET_CODE (x1)) + { + case COMPARE: + goto L46; + case ZERO_EXTRACT: + goto L101; + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + case SUBREG: + case REG: + case MEM: + L23: + if (general_operand (x1, SFmode)) + goto L27; + } + L37: + if (general_operand (x1, DFmode)) + goto L41; + L1262: + if (GET_MODE (x1) == SImode && GET_CODE (x1) == ZERO_EXTRACT && 1) + goto L1263; + x1 = XEXP (x0, 0); + goto L1595; + + L46: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[0] = x2; + goto L47; + } + break; + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[0] = x2; + goto L52; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[0] = x2; + goto L57; + } + break; + case DFmode: + if (general_operand (x2, DFmode)) + { + ro[0] = x2; + goto L70; + } + break; + case SFmode: + if (general_operand (x2, SFmode)) + { + ro[0] = x2; + goto L90; + } + } + x1 = XEXP (x0, 0); + goto L1595; + + L47: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 11; + } + x1 = XEXP (x0, 0); + goto L1595; + + L52: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 12; + } + x1 = XEXP (x0, 0); + goto L1595; + + L57: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 13; + } + x1 = XEXP (x0, 0); + goto L1595; + + L70: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + goto L76; + x1 = XEXP (x0, 0); + goto L1595; + + L76: + if (pnum_clobbers != 0 && 1) + { + ro[1] = x2; + if (TARGET_FPA) + { + *pnum_clobbers = 1; + return 15; + } + } + L77: + ro[1] = x2; + if (TARGET_68881) + return 16; + x1 = XEXP (x0, 0); + goto L1595; + + L90: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + goto L96; + x1 = XEXP (x0, 0); + goto L1595; + + L96: + if (pnum_clobbers != 0 && 1) + { + ro[1] = x2; + if (TARGET_FPA) + { + *pnum_clobbers = 1; + return 18; + } + } + L97: + ro[1] = x2; + if (TARGET_68881) + return 19; + x1 = XEXP (x0, 0); + goto L1595; + + L101: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[0] = x2; + goto L102; + } + break; + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[0] = x2; + goto L110; + } + } + goto L1262; + + L102: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 1 && 1) + goto L103; + goto L1262; + + L103: + x2 = XEXP (x1, 2); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == MINUS && 1) + goto L104; + if (general_operand (x2, SImode)) + { + ro[1] = x2; + if (GET_CODE (operands[1]) == CONST_INT + && (unsigned) INTVAL (operands[1]) < 8) + return 24; + } + goto L1262; + + L104: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 7 && 1) + goto L121; + goto L1262; + + L121: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == AND && 1) + goto L122; + if (general_operand (x3, SImode)) + { + ro[1] = x3; + return 20; + } + goto L1262; + + L122: + x4 = XEXP (x3, 0); + if (general_operand (x4, SImode)) + { + ro[1] = x4; + goto L123; + } + goto L1262; + + L123: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 7 && 1) + return 22; + goto L1262; + + L110: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 1 && 1) + goto L111; + goto L1262; + + L111: + x2 = XEXP (x1, 2); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == MINUS && 1) + goto L112; + if (general_operand (x2, SImode)) + { + ro[1] = x2; + if (GET_CODE (operands[1]) == CONST_INT) + return 25; + } + goto L1262; + + L112: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 31 && 1) + goto L131; + goto L1262; + + L131: + x3 = XEXP (x2, 1); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == AND && 1) + goto L132; + if (general_operand (x3, SImode)) + { + ro[1] = x3; + return 21; + } + goto L1262; + + L132: + x4 = XEXP (x3, 0); + if (general_operand (x4, SImode)) + { + ro[1] = x4; + goto L133; + } + goto L1262; + + L133: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 31 && 1) + return 23; + goto L1262; + + L27: + if (pnum_clobbers != 0 && 1) + { + ro[0] = x1; + if (TARGET_FPA) + { + *pnum_clobbers = 1; + return 6; + } + } + L28: + ro[0] = x1; + if (TARGET_68881) + return 7; + goto L37; + + L41: + if (pnum_clobbers != 0 && 1) + { + ro[0] = x1; + if (TARGET_FPA) + { + *pnum_clobbers = 1; + return 9; + } + } + L42: + ro[0] = x1; + if (TARGET_68881) + return 10; + x1 = XEXP (x0, 0); + goto L1595; + + L1263: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case QImode: + if (memory_operand (x2, QImode)) + { + ro[0] = x2; + goto L1264; + } + break; + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[0] = x2; + goto L1270; + } + } + x1 = XEXP (x0, 0); + goto L1595; + + L1264: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L1265; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1265: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + if (TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[1]) == CONST_INT) + return 246; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1270: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L1271; + } + x1 = XEXP (x0, 0); + goto L1595; + + L1271: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + if (TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[1]) == CONST_INT) + return 247; + } + x1 = XEXP (x0, 0); + goto L1595; + L160: + tem = recog_4 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + goto L1595; + + L1324: + x1 = XEXP (x0, 1); + switch (GET_CODE (x1)) + { + case IF_THEN_ELSE: + goto L1325; + case LABEL_REF: + goto L1505; + } + x1 = XEXP (x0, 0); + goto L1595; + L1325: + tem = recog_5 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L1595; + + L1505: + x2 = XEXP (x1, 0); + ro[0] = x2; + return 278; + + L1596: + x1 = XEXP (x0, 1); + if (GET_CODE (x1) == CALL && 1) + goto L1597; + x1 = XEXP (x0, 0); + goto L1612; + + L1597: + x2 = XEXP (x1, 0); + if (memory_operand (x2, QImode)) + { + ro[1] = x2; + goto L1598; + } + x1 = XEXP (x0, 0); + goto L1612; + + L1598: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + goto L1604; + x1 = XEXP (x0, 0); + goto L1612; + + L1604: + ro[2] = x2; + if (! flag_pic) + return 290; + L1605: + ro[2] = x2; + if (flag_pic) + return 291; + x1 = XEXP (x0, 0); + goto L1612; + + L1613: + x1 = XEXP (x0, 1); + if (address_operand (x1, SImode)) + { + ro[0] = x1; + return 297; + } + goto ret0; + + L1703: + x1 = XEXP (x0, 1); + if (nonimmediate_operand (x1, XFmode)) + { + ro[0] = x1; + if (TARGET_68881) + return 318; + } + if (GET_CODE (x1) == COMPARE && 1) + goto L1707; + goto ret0; + + L1707: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, XFmode)) + { + ro[0] = x2; + goto L1708; + } + goto ret0; + + L1708: + x2 = XEXP (x1, 1); + if (nonimmediate_operand (x2, XFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 320; + } + goto ret0; + + L1751: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == SImode && GET_CODE (x1) == FIX && 1) + goto L1752; + if (address_operand (x1, QImode)) + { + ro[1] = x1; + return 298; + } + goto ret0; + + L1752: + x2 = XEXP (x1, 0); + if (general_operand (x2, XFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 331; + } + goto ret0; + + L1619: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != DFmode) + { + x1 = XEXP (x0, 0); + goto L1718; + } + switch (GET_CODE (x1)) + { + case PLUS: + goto L1620; + case MINUS: + goto L1648; + case MULT: + goto L1662; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1620: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == MULT && 1) + goto L1621; + x1 = XEXP (x0, 0); + goto L1718; + + L1621: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + goto L1622; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1622: + x3 = XEXP (x2, 1); + if (general_operand (x3, DFmode)) + { + ro[2] = x3; + goto L1623; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1623: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[3] = x2; + if (TARGET_FPA) + return 306; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1648: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == MULT && 1) + goto L1649; + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L1635; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1649: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + goto L1650; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1650: + x3 = XEXP (x2, 1); + if (general_operand (x3, DFmode)) + { + ro[2] = x3; + goto L1651; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1651: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[3] = x2; + if (TARGET_FPA) + return 310; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1635: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == MULT && 1) + goto L1636; + x1 = XEXP (x0, 0); + goto L1718; + + L1636: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[2] = x3; + goto L1637; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1637: + x3 = XEXP (x2, 1); + if (general_operand (x3, DFmode)) + { + ro[3] = x3; + if (TARGET_FPA) + return 308; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1662: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case DFmode: + switch (GET_CODE (x2)) + { + case PLUS: + goto L1663; + case MINUS: + goto L1677; + } + } + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L1684; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1663: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + goto L1664; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1664: + x3 = XEXP (x2, 1); + if (general_operand (x3, DFmode)) + { + ro[2] = x3; + goto L1665; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1665: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[3] = x2; + if (TARGET_FPA) + return 312; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1677: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + goto L1678; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1678: + x3 = XEXP (x2, 1); + if (general_operand (x3, DFmode)) + { + ro[2] = x3; + goto L1679; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1679: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[3] = x2; + if (TARGET_FPA) + return 314; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1684: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == DFmode && GET_CODE (x2) == MINUS && 1) + goto L1685; + x1 = XEXP (x0, 0); + goto L1718; + + L1685: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[2] = x3; + goto L1686; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1686: + x3 = XEXP (x2, 1); + if (general_operand (x3, DFmode)) + { + ro[3] = x3; + if (TARGET_FPA) + return 315; + } + x1 = XEXP (x0, 0); + goto L1718; + + L1719: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == DFmode && GET_CODE (x1) == FLOAT_TRUNCATE && 1) + goto L1720; + goto ret0; + + L1720: + x2 = XEXP (x1, 0); + if (general_operand (x2, XFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 323; + } + goto ret0; + + L1626: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != SFmode) + { + x1 = XEXP (x0, 0); + goto L1722; + } + switch (GET_CODE (x1)) + { + case PLUS: + goto L1627; + case MINUS: + goto L1655; + case MULT: + goto L1669; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1627: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SFmode && GET_CODE (x2) == MULT && 1) + goto L1628; + x1 = XEXP (x0, 0); + goto L1722; + + L1628: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + goto L1629; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1629: + x3 = XEXP (x2, 1); + if (general_operand (x3, SFmode)) + { + ro[2] = x3; + goto L1630; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1630: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[3] = x2; + if (TARGET_FPA) + return 307; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1655: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SFmode && GET_CODE (x2) == MULT && 1) + goto L1656; + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L1642; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1656: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + goto L1657; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1657: + x3 = XEXP (x2, 1); + if (general_operand (x3, SFmode)) + { + ro[2] = x3; + goto L1658; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1658: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[3] = x2; + if (TARGET_FPA) + return 311; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1642: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SFmode && GET_CODE (x2) == MULT && 1) + goto L1643; + x1 = XEXP (x0, 0); + goto L1722; + + L1643: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[2] = x3; + goto L1644; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1644: + x3 = XEXP (x2, 1); + if (general_operand (x3, SFmode)) + { + ro[3] = x3; + if (TARGET_FPA) + return 309; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1669: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SFmode: + switch (GET_CODE (x2)) + { + case PLUS: + goto L1670; + case MINUS: + goto L1691; + } + } + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L1698; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1670: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + goto L1671; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1671: + x3 = XEXP (x2, 1); + if (general_operand (x3, SFmode)) + { + ro[2] = x3; + goto L1672; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1672: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[3] = x2; + if (TARGET_FPA) + return 313; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1691: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + goto L1692; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1692: + x3 = XEXP (x2, 1); + if (general_operand (x3, SFmode)) + { + ro[2] = x3; + goto L1693; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1693: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[3] = x2; + if (TARGET_FPA) + return 316; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1698: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SFmode && GET_CODE (x2) == MINUS && 1) + goto L1699; + x1 = XEXP (x0, 0); + goto L1722; + + L1699: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[2] = x3; + goto L1700; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1700: + x3 = XEXP (x2, 1); + if (general_operand (x3, SFmode)) + { + ro[3] = x3; + if (TARGET_FPA) + return 317; + } + x1 = XEXP (x0, 0); + goto L1722; + + L1723: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == SFmode && GET_CODE (x1) == FLOAT_TRUNCATE && 1) + goto L1724; + goto ret0; + + L1724: + x2 = XEXP (x1, 0); + if (general_operand (x2, XFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 324; + } + goto ret0; + + L1711: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != XFmode) + goto ret0; + switch (GET_CODE (x1)) + { + case FLOAT_EXTEND: + goto L1712; + case FLOAT: + goto L1728; + case FIX: + goto L1740; + case PLUS: + goto L1756; + case MINUS: + goto L1761; + case MULT: + goto L1766; + case DIV: + goto L1771; + case NEG: + goto L1776; + case ABS: + goto L1780; + case SQRT: + goto L1784; + } + goto ret0; + + L1712: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 321; + } + L1716: + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 322; + } + goto ret0; + + L1728: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + if (TARGET_68881) + return 325; + } + L1732: + if (general_operand (x2, HImode)) + { + ro[1] = x2; + if (TARGET_68881) + return 326; + } + L1736: + if (general_operand (x2, QImode)) + { + ro[1] = x2; + if (TARGET_68881) + return 327; + } + goto ret0; + + L1740: + x2 = XEXP (x1, 0); + if (general_operand (x2, XFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 328; + } + goto ret0; + + L1756: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, XFmode)) + { + ro[1] = x2; + goto L1757; + } + goto ret0; + + L1757: + x2 = XEXP (x1, 1); + if (nonimmediate_operand (x2, XFmode)) + { + ro[2] = x2; + if (TARGET_68881) + return 333; + } + goto ret0; + + L1761: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, XFmode)) + { + ro[1] = x2; + goto L1762; + } + goto ret0; + + L1762: + x2 = XEXP (x1, 1); + if (nonimmediate_operand (x2, XFmode)) + { + ro[2] = x2; + if (TARGET_68881) + return 335; + } + goto ret0; + + L1766: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, XFmode)) + { + ro[1] = x2; + goto L1767; + } + goto ret0; + + L1767: + x2 = XEXP (x1, 1); + if (nonimmediate_operand (x2, XFmode)) + { + ro[2] = x2; + if (TARGET_68881) + return 337; + } + goto ret0; + + L1771: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, XFmode)) + { + ro[1] = x2; + goto L1772; + } + goto ret0; + + L1772: + x2 = XEXP (x1, 1); + if (nonimmediate_operand (x2, XFmode)) + { + ro[2] = x2; + if (TARGET_68881) + return 339; + } + goto ret0; + + L1776: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, XFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 340; + } + goto ret0; + + L1780: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, XFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 341; + } + goto ret0; + + L1784: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 342; + } + goto ret0; + + L1743: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == QImode && GET_CODE (x1) == FIX && 1) + goto L1744; + goto ret0; + + L1744: + x2 = XEXP (x1, 0); + if (general_operand (x2, XFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 329; + } + goto ret0; + + L1747: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == HImode && GET_CODE (x1) == FIX && 1) + goto L1748; + goto ret0; + + L1748: + x2 = XEXP (x1, 0); + if (general_operand (x2, XFmode)) + { + ro[1] = x2; + if (TARGET_68881) + return 330; + } + goto ret0; + ret0: return -1; +} + +int +recog_7 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + switch (GET_MODE (x2)) + { + case SImode: + if (GET_CODE (x2) == PLUS && 1) + goto L1517; + if (register_operand (x2, SImode)) + { + ro[0] = x2; + goto L1510; + } + } + if (GET_CODE (x2) == IF_THEN_ELSE && 1) + goto L1526; + goto ret0; + + L1517: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == PC && 1) + goto L1518; + goto ret0; + + L1518: + x3 = XEXP (x2, 1); + if (register_operand (x3, HImode)) + { + ro[0] = x3; + goto L1519; + } + goto ret0; + + L1519: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1520; + goto ret0; + + L1520: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1521; + goto ret0; + + L1521: + x3 = XEXP (x2, 0); + ro[1] = x3; + return 281; + + L1510: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1511; + goto ret0; + + L1511: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1512; + goto ret0; + + L1512: + x3 = XEXP (x2, 0); + ro[1] = x3; + return 280; + + L1526: + x3 = XEXP (x2, 0); + switch (GET_CODE (x3)) + { + case NE: + goto L1527; + case GE: + goto L1557; + } + goto ret0; + + L1527: + x4 = XEXP (x3, 0); + switch (GET_MODE (x4)) + { + case HImode: + if (general_operand (x4, HImode)) + { + ro[0] = x4; + goto L1528; + } + break; + case SImode: + if (general_operand (x4, SImode)) + { + ro[0] = x4; + goto L1543; + } + } + goto ret0; + + L1528: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 0 && 1) + goto L1529; + goto ret0; + + L1529: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == LABEL_REF && 1) + goto L1530; + goto ret0; + + L1530: + x4 = XEXP (x3, 0); + ro[1] = x4; + goto L1531; + + L1531: + x3 = XEXP (x2, 2); + if (GET_CODE (x3) == PC && 1) + goto L1532; + goto ret0; + + L1532: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1533; + goto ret0; + + L1533: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1534; + goto ret0; + + L1534: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == PLUS && 1) + goto L1535; + goto ret0; + + L1535: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[0]) && 1) + goto L1536; + goto ret0; + + L1536: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == -1 && 1) + return 282; + goto ret0; + + L1543: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 0 && 1) + goto L1544; + goto ret0; + + L1544: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == LABEL_REF && 1) + goto L1545; + goto ret0; + + L1545: + x4 = XEXP (x3, 0); + ro[1] = x4; + goto L1546; + + L1546: + x3 = XEXP (x2, 2); + if (GET_CODE (x3) == PC && 1) + goto L1547; + goto ret0; + + L1547: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1548; + goto ret0; + + L1548: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1549; + goto ret0; + + L1549: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == PLUS && 1) + goto L1550; + goto ret0; + + L1550: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[0]) && 1) + goto L1551; + goto ret0; + + L1551: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == -1 && 1) + return 283; + goto ret0; + + L1557: + x4 = XEXP (x3, 0); + if (GET_CODE (x4) != PLUS) + goto ret0; + switch (GET_MODE (x4)) + { + case HImode: + goto L1558; + case SImode: + goto L1575; + } + goto ret0; + + L1558: + x5 = XEXP (x4, 0); + if (general_operand (x5, HImode)) + { + ro[0] = x5; + goto L1559; + } + goto ret0; + + L1559: + x5 = XEXP (x4, 1); + if (GET_CODE (x5) == CONST_INT && XWINT (x5, 0) == -1 && 1) + goto L1560; + goto ret0; + + L1560: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 0 && 1) + goto L1561; + goto ret0; + + L1561: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == LABEL_REF && 1) + goto L1562; + goto ret0; + + L1562: + x4 = XEXP (x3, 0); + ro[1] = x4; + goto L1563; + + L1563: + x3 = XEXP (x2, 2); + if (GET_CODE (x3) == PC && 1) + goto L1564; + goto ret0; + + L1564: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1565; + goto ret0; + + L1565: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1566; + goto ret0; + + L1566: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == PLUS && 1) + goto L1567; + goto ret0; + + L1567: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[0]) && 1) + goto L1568; + goto ret0; + + L1568: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == -1 && 1) + if (find_reg_note (insn, REG_NONNEG, 0)) + return 284; + goto ret0; + + L1575: + x5 = XEXP (x4, 0); + if (general_operand (x5, SImode)) + { + ro[0] = x5; + goto L1576; + } + goto ret0; + + L1576: + x5 = XEXP (x4, 1); + if (GET_CODE (x5) == CONST_INT && XWINT (x5, 0) == -1 && 1) + goto L1577; + goto ret0; + + L1577: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 0 && 1) + goto L1578; + goto ret0; + + L1578: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == LABEL_REF && 1) + goto L1579; + goto ret0; + + L1579: + x4 = XEXP (x3, 0); + ro[1] = x4; + goto L1580; + + L1580: + x3 = XEXP (x2, 2); + if (GET_CODE (x3) == PC && 1) + goto L1581; + goto ret0; + + L1581: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L1582; + goto ret0; + + L1582: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L1583; + goto ret0; + + L1583: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == PLUS && 1) + goto L1584; + goto ret0; + + L1584: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[0]) && 1) + goto L1585; + goto ret0; + + L1585: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == -1 && 1) + if (find_reg_note (insn, REG_NONNEG, 0)) + return 285; + goto ret0; + ret0: return -1; +} + +int +recog_8 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (register_operand (x2, SImode)) + { + ro[0] = x2; + goto L537; + } + L718: + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L719; + } + } + switch (GET_CODE (x2)) + { + case CC0: + goto L18; + case PC: + goto L1516; + } + goto ret0; + + L537: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == MULT && 1) + goto L538; + x2 = XEXP (x1, 0); + goto L718; + + L538: + x3 = XEXP (x2, 0); + if (register_operand (x3, SImode)) + { + ro[1] = x3; + goto L539; + } + x2 = XEXP (x1, 0); + goto L718; + + L539: + x3 = XEXP (x2, 1); + if (nonimmediate_operand (x3, SImode)) + { + ro[2] = x3; + goto L540; + } + if (GET_CODE (x3) == CONST_INT && 1) + { + ro[2] = x3; + goto L556; + } + x2 = XEXP (x1, 0); + goto L718; + + L540: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L541; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L541: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[3] = x2; + goto L542; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L542: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == TRUNCATE && 1) + goto L543; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L543: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) != DImode) + { + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + } + switch (GET_CODE (x3)) + { + case LSHIFTRT: + goto L544; + case ASHIFT: + goto L575; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L544: + x4 = XEXP (x3, 0); + if (GET_MODE (x4) == DImode && GET_CODE (x4) == MULT && 1) + goto L545; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L545: + x5 = XEXP (x4, 0); + if (GET_MODE (x5) == DImode && GET_CODE (x5) == ZERO_EXTEND && 1) + goto L546; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L546: + x6 = XEXP (x5, 0); + if (rtx_equal_p (x6, ro[1]) && 1) + goto L547; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L547: + x5 = XEXP (x4, 1); + if (GET_MODE (x5) == DImode && GET_CODE (x5) == ZERO_EXTEND && 1) + goto L548; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L548: + x6 = XEXP (x5, 0); + if (rtx_equal_p (x6, ro[2]) && 1) + goto L549; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L549: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 32 && 1) + if (TARGET_68020) + return 116; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L575: + x4 = XEXP (x3, 0); + if (GET_MODE (x4) == DImode && GET_CODE (x4) == MULT && 1) + goto L576; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L576: + x5 = XEXP (x4, 0); + if (GET_MODE (x5) == DImode && GET_CODE (x5) == SIGN_EXTEND && 1) + goto L577; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L577: + x6 = XEXP (x5, 0); + if (rtx_equal_p (x6, ro[1]) && 1) + goto L578; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L578: + x5 = XEXP (x4, 1); + if (GET_MODE (x5) == DImode && GET_CODE (x5) == SIGN_EXTEND && 1) + goto L579; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L579: + x6 = XEXP (x5, 0); + if (rtx_equal_p (x6, ro[2]) && 1) + goto L580; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L580: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 32 && 1) + if (TARGET_68020) + return 119; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L556: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L557; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L557: + x2 = XEXP (x1, 0); + if (register_operand (x2, SImode)) + { + ro[3] = x2; + goto L558; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L558: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == TRUNCATE && 1) + goto L559; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L559: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) != DImode) + { + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + } + switch (GET_CODE (x3)) + { + case LSHIFTRT: + goto L560; + case ASHIFT: + goto L591; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L560: + x4 = XEXP (x3, 0); + if (GET_MODE (x4) == DImode && GET_CODE (x4) == MULT && 1) + goto L561; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L561: + x5 = XEXP (x4, 0); + if (GET_MODE (x5) == DImode && GET_CODE (x5) == ZERO_EXTEND && 1) + goto L562; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L562: + x6 = XEXP (x5, 0); + if (rtx_equal_p (x6, ro[1]) && 1) + goto L563; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L563: + x5 = XEXP (x4, 1); + if (rtx_equal_p (x5, ro[2]) && 1) + goto L564; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L564: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 32 && 1) + if (TARGET_68020 + && (unsigned) INTVAL (operands[2]) <= 0x7fffffff) + return 117; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L591: + x4 = XEXP (x3, 0); + if (GET_MODE (x4) == DImode && GET_CODE (x4) == MULT && 1) + goto L592; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L592: + x5 = XEXP (x4, 0); + if (GET_MODE (x5) == DImode && GET_CODE (x5) == SIGN_EXTEND && 1) + goto L593; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L593: + x6 = XEXP (x5, 0); + if (rtx_equal_p (x6, ro[1]) && 1) + goto L594; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L594: + x5 = XEXP (x4, 1); + if (rtx_equal_p (x5, ro[2]) && 1) + goto L595; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L595: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 32 && 1) + if (TARGET_68020 + /* This test is a noop on 32 bit machines, + but important for a cross-compiler hosted on 64-bit machines. */ + && INTVAL (operands[2]) <= 0x7fffffff + && INTVAL (operands[2]) >= -0x80000000) + return 120; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 0); + goto L718; + + L719: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != SImode) + goto ret0; + switch (GET_CODE (x2)) + { + case DIV: + goto L720; + case UDIV: + goto L731; + } + goto ret0; + + L720: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L721; + } + goto ret0; + + L721: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + goto L722; + } + goto ret0; + + L722: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L723; + goto ret0; + + L723: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && general_operand (x2, SImode)) + { + ro[3] = x2; + goto L724; + } + goto ret0; + + L724: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == MOD && 1) + goto L725; + goto ret0; + + L725: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L726; + goto ret0; + + L726: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[2]) && 1) + if (TARGET_68020) + return 145; + goto ret0; + + L731: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L732; + } + goto ret0; + + L732: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + goto L733; + } + goto ret0; + + L733: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L734; + goto ret0; + + L734: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && general_operand (x2, SImode)) + { + ro[3] = x2; + goto L735; + } + goto ret0; + + L735: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == UMOD && 1) + goto L736; + goto ret0; + + L736: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[1]) && 1) + goto L737; + goto ret0; + + L737: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[2]) && 1) + if (TARGET_68020) + return 146; + goto ret0; + + L18: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[0] = x2; + goto L19; + } + L32: + if (general_operand (x2, DFmode)) + { + ro[0] = x2; + goto L33; + } + if (GET_CODE (x2) == COMPARE && 1) + goto L62; + goto ret0; + + L19: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L20; + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L32; + + L20: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[1] = x2; + if (TARGET_FPA) + return 6; + } + x1 = XVECEXP (x0, 0, 0); + x2 = XEXP (x1, 1); + goto L32; + + L33: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L34; + goto ret0; + + L34: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[1] = x2; + if (TARGET_FPA) + return 9; + } + goto ret0; + + L62: + x3 = XEXP (x2, 0); + switch (GET_MODE (x3)) + { + case DFmode: + if (general_operand (x3, DFmode)) + { + ro[0] = x3; + goto L63; + } + break; + case SFmode: + if (general_operand (x3, SFmode)) + { + ro[0] = x3; + goto L83; + } + } + goto ret0; + + L63: + x3 = XEXP (x2, 1); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + goto L64; + } + goto ret0; + + L64: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L65; + goto ret0; + + L65: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[2] = x2; + if (TARGET_FPA) + return 15; + } + goto ret0; + + L83: + x3 = XEXP (x2, 1); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + goto L84; + } + goto ret0; + + L84: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L85; + goto ret0; + + L85: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[2] = x2; + if (TARGET_FPA) + return 18; + } + goto ret0; + L1516: + return recog_7 (x0, insn, pnum_clobbers); + ret0: return -1; +} + +int +recog (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + int tem; + + L1609: + switch (GET_CODE (x0)) + { + case REG: + if (GET_MODE (x0) == SImode && XINT (x0, 0) == 15 && 1) + if (NEED_PROBE) + return 295; + break; + case SET: + goto L1; + case PARALLEL: + if (XVECLEN (x0, 0) == 2 && 1) + goto L16; + if (XVECLEN (x0, 0) == 3 && 1) + goto L286; + break; + case CALL: + goto L1587; + case UNSPEC_VOLATILE: + if (XINT (x0, 1) == 0 && XVECLEN (x0, 0) == 1 && 1) + goto L1607; + break; + case CONST_INT: + if (XWINT (x0, 0) == 0 && 1) + return 294; + break; + case RETURN: + if (USE_RETURN_INSN) + return 296; + } + goto ret0; + L1: + return recog_6 (x0, insn, pnum_clobbers); + + L16: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == SET && 1) + goto L536; + goto ret0; + L536: + return recog_8 (x0, insn, pnum_clobbers); + + L286: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == SET && 1) + goto L287; + goto ret0; + + L287: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L288; + } + break; + case HImode: + if (general_operand (x2, HImode)) + { + ro[0] = x2; + goto L303; + } + break; + case QImode: + if (general_operand (x2, QImode)) + { + ro[0] = x2; + goto L318; + } + } + goto ret0; + + L288: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == FIX && 1) + goto L289; + goto ret0; + + L289: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == DFmode && GET_CODE (x3) == FIX && 1) + goto L290; + goto ret0; + + L290: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L291; + } + goto ret0; + + L291: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L292; + goto ret0; + + L292: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[2] = x2; + goto L293; + } + goto ret0; + + L293: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L294; + goto ret0; + + L294: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68040) + return 70; + } + goto ret0; + + L303: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == FIX && 1) + goto L304; + goto ret0; + + L304: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == DFmode && GET_CODE (x3) == FIX && 1) + goto L305; + goto ret0; + + L305: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L306; + } + goto ret0; + + L306: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L307; + goto ret0; + + L307: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[2] = x2; + goto L308; + } + goto ret0; + + L308: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L309; + goto ret0; + + L309: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68040) + return 71; + } + goto ret0; + + L318: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == QImode && GET_CODE (x2) == FIX && 1) + goto L319; + goto ret0; + + L319: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == DFmode && GET_CODE (x3) == FIX && 1) + goto L320; + goto ret0; + + L320: + x4 = XEXP (x3, 0); + if (register_operand (x4, DFmode)) + { + ro[1] = x4; + goto L321; + } + goto ret0; + + L321: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == CLOBBER && 1) + goto L322; + goto ret0; + + L322: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[2] = x2; + goto L323; + } + goto ret0; + + L323: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L324; + goto ret0; + + L324: + x2 = XEXP (x1, 0); + if (scratch_operand (x2, SImode)) + { + ro[3] = x2; + if (TARGET_68040) + return 72; + } + goto ret0; + + L1587: + x1 = XEXP (x0, 0); + if (memory_operand (x1, QImode)) + { + ro[0] = x1; + goto L1588; + } + goto ret0; + + L1588: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + goto L1592; + goto ret0; + + L1592: + ro[1] = x1; + if (! flag_pic) + return 287; + L1593: + ro[1] = x1; + if (flag_pic) + return 288; + goto ret0; + + L1607: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == CONST_INT && XWINT (x1, 0) == 0 && 1) + return 293; + goto ret0; + ret0: return -1; +} + +rtx +split_insns (x0, insn) + register rtx x0; + rtx insn; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4, x5, x6; + rtx tem; + + goto ret0; + ret0: return 0; +} + diff --git a/gnu/usr.bin/gcc2/arch/m68k/m68k.h b/gnu/usr.bin/gcc2/arch/m68k/m68k.h new file mode 100644 index 000000000000..9e82ddb32d63 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/m68k.h @@ -0,0 +1,1796 @@ +/* Definitions of target machine for GNU compiler. Sun 68000/68020 version. + Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + + $Id: m68k.h,v 1.1 1993/11/25 01:26:21 paulus Exp $ +*/ + + +/* Note that some other tm.h files include this one and then override + many of the definitions that relate to assembler syntax. */ + + +/* Names to predefine in the preprocessor for this target machine. */ + +/* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */ + +/* Print subsidiary information on the compiler version in use. */ +#ifdef MOTOROLA +#define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)"); +#else +#define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)"); +#endif + +/* Define SUPPORT_SUN_FPA to include support for generating code for + the Sun Floating Point Accelerator, an optional product for Sun 3 + machines. By default, it is not defined. Avoid defining it unless + you need to output code for the Sun3+FPA architecture, as it has the + effect of slowing down the register set operations in hard-reg-set.h + (total number of registers will exceed number of bits in a long, + if defined, causing the set operations to expand to loops). + SUPPORT_SUN_FPA is typically defined in sun3.h. */ + +/* Run-time compilation parameters selecting different hardware subsets. */ + +extern int target_flags; + +/* Macros used in the machine description to test the flags. */ + +/* Compile for a 68020 (not a 68000 or 68010). */ +#define TARGET_68020 (target_flags & 1) + +/* Compile 68881 insns for floating point (not library calls). */ +#define TARGET_68881 (target_flags & 2) + +/* Compile using 68020 bitfield insns. */ +#define TARGET_BITFIELD (target_flags & 4) + +/* Compile using rtd insn calling sequence. + This will not work unless you use prototypes at least + for all functions that can take varying numbers of args. */ +#define TARGET_RTD (target_flags & 8) + +/* Compile passing first two args in regs 0 and 1. + This exists only to test compiler features that will + be needed for RISC chips. It is not usable + and is not intended to be usable on this cpu. */ +#define TARGET_REGPARM (target_flags & 020) + +/* Compile with 16-bit `int'. */ +#define TARGET_SHORT (target_flags & 040) + +/* Compile with special insns for Sun FPA. */ +#ifdef SUPPORT_SUN_FPA +#define TARGET_FPA (target_flags & 0100) +#else +#define TARGET_FPA 0 +#endif + +/* Compile (actually, link) for Sun SKY board. */ +#define TARGET_SKY (target_flags & 0200) + +/* Optimize for 68040, but still allow execution on 68020 + (-m68020-40 or -m68040). + The 68040 will execute all 68030 and 68881/2 instructions, but some + of them must be emulated in software by the OS. When TARGET_68040 is + turned on, these instructions won't be used. This code will still + run on a 68030 and 68881/2. */ +#define TARGET_68040 (target_flags & 01400) + +/* Use the 68040-only fp instructions (-m68040). */ +#define TARGET_68040_ONLY (target_flags & 01000) + +/* Macro to define tables used to set the flags. + This is a list in braces of pairs in braces, + each pair being { "NAME", VALUE } + where VALUE is the bits to set or minus the bits to clear. + An empty string NAME is used to identify the default VALUE. */ + +#define TARGET_SWITCHES \ + { { "68020", -01400}, \ + { "c68020", -01400}, \ + { "68020", 5}, \ + { "c68020", 5}, \ + { "68881", 2}, \ + { "bitfield", 4}, \ + { "68000", -01405}, \ + { "c68000", -01405}, \ + { "soft-float", -01102}, \ + { "nobitfield", -4}, \ + { "rtd", 8}, \ + { "nortd", -8}, \ + { "short", 040}, \ + { "noshort", -040}, \ + { "fpa", 0100}, \ + { "nofpa", -0100}, \ + { "sky", 0200}, \ + { "nosky", -0200}, \ + { "68020-40", 0407}, \ + { "68030", -01400}, \ + { "68030", 5}, \ + { "68040", 01007}, \ + { "", TARGET_DEFAULT}} +/* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */ + +/* For PIC, function CSE is undesirable since it causes all function + calls to go via the GOT rather than the PLT. */ +#ifdef SUPPORT_SUN_FPA +/* Blow away 68881 flag silently on TARGET_FPA (since we can't clear + any bits in TARGET_SWITCHES above) */ +#define OVERRIDE_OPTIONS \ +{ \ + if (TARGET_FPA) target_flags &= ~2; \ + if (! TARGET_68020 && flag_pic == 2) \ + error("-fPIC is not currently supported on the 68000 or 68010\n"); \ + if (flag_pic) \ + flag_no_function_cse = 1; \ +} +#else +#define OVERRIDE_OPTIONS \ +{ \ + if (! TARGET_68020 && flag_pic == 2) \ + error("-fPIC is not currently supported on the 68000 or 68010\n"); \ + if (flag_pic) \ + flag_no_function_cse = 1; \ +} +#endif /* defined SUPPORT_SUN_FPA */ + +/* target machine storage layout */ + +/* Define for XFmode extended real floating point support. + This will automatically cause REAL_ARITHMETIC to be defined. */ +#define LONG_DOUBLE_TYPE_SIZE 96 + +/* Define if you don't want extended real, but do want to use the + software floating point emulator for REAL_ARITHMETIC and + decimal <-> binary conversion. */ +/* #define REAL_ARITHMETIC */ + +/* Define this if most significant bit is lowest numbered + in instructions that operate on numbered bit-fields. + This is true for 68020 insns such as bfins and bfexts. + We make it true always by avoiding using the single-bit insns + except in special cases with constant bit numbers. */ +#define BITS_BIG_ENDIAN 1 + +/* Define this if most significant byte of a word is the lowest numbered. */ +/* That is true on the 68000. */ +#define BYTES_BIG_ENDIAN 1 + +/* Define this if most significant word of a multiword number is the lowest + numbered. */ +/* For 68000 we can decide arbitrarily + since there are no machine instructions for them. + So let's be consistent. */ +#define WORDS_BIG_ENDIAN 1 + +/* number of bits in an addressable storage unit */ +#define BITS_PER_UNIT 8 + +/* Width in bits of a "word", which is the contents of a machine register. + Note that this is not necessarily the width of data type `int'; + if using 16-bit ints on a 68000, this would still be 32. + But on a machine with 16-bit registers, this would be 16. */ +#define BITS_PER_WORD 32 + +/* Width of a word, in units (bytes). */ +#define UNITS_PER_WORD 4 + +/* Width in bits of a pointer. + See also the macro `Pmode' defined below. */ +#define POINTER_SIZE 32 + +/* Allocation boundary (in *bits*) for storing arguments in argument list. */ +#define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) + +/* Boundary (in *bits*) on which stack pointer should be aligned. */ +#define STACK_BOUNDARY 16 + +/* Allocation boundary (in *bits*) for the code of a function. */ +#define FUNCTION_BOUNDARY 16 + +/* Alignment of field after `int : 0' in a structure. */ +#define EMPTY_FIELD_BOUNDARY 16 + +/* No data type wants to be aligned rounder than this. */ +#define BIGGEST_ALIGNMENT 16 + +/* Set this nonzero if move instructions will actually fail to work + when given unaligned data. */ +#define STRICT_ALIGNMENT 1 + +#define SELECT_RTX_SECTION(MODE, X) \ +{ \ + if (!flag_pic) \ + readonly_data_section(); \ + else if (LEGITIMATE_PIC_OPERAND_P (X)) \ + readonly_data_section(); \ + else \ + data_section(); \ +} + +/* Define number of bits in most basic integer type. + (If undefined, default is BITS_PER_WORD). */ + +#define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) + +/* Define these to avoid dependence on meaning of `int'. + Note that WCHAR_TYPE_SIZE is used in cexp.y, + where TARGET_SHORT is not available. */ + +#define WCHAR_TYPE "long int" +#define WCHAR_TYPE_SIZE 32 + +/* Standard register usage. */ + +/* Number of actual hardware registers. + The hardware registers are assigned numbers for the compiler + from 0 to just below FIRST_PSEUDO_REGISTER. + All registers that the compiler knows about must be given numbers, + even those that are not normally considered general registers. + For the 68000, we give the data registers numbers 0-7, + the address registers numbers 010-017, + and the 68881 floating point registers numbers 020-027. */ +#ifndef SUPPORT_SUN_FPA +#define FIRST_PSEUDO_REGISTER 24 +#else +#define FIRST_PSEUDO_REGISTER 56 +#endif + +/* This defines the register which is used to hold the offset table for PIC. */ +#define PIC_OFFSET_TABLE_REGNUM 13 + +/* Used to output a (use pic_offset_table_rtx) so that we + always save/restore a5 in functions that use PIC relocation + at *any* time during the compilation process. */ +#define FINALIZE_PIC finalize_pic() + +#ifndef SUPPORT_SUN_FPA + +/* 1 for registers that have pervasive standard uses + and are not available for the register allocator. + On the 68000, only the stack pointer is such. */ + +#define FIXED_REGISTERS \ + {/* Data registers. */ \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + \ + /* Address registers. */ \ + 0, 0, 0, 0, 0, 0, 0, 1, \ + \ + /* Floating point registers \ + (if available). */ \ + 0, 0, 0, 0, 0, 0, 0, 0 } + +/* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ +#define CALL_USED_REGISTERS \ + {1, 1, 0, 0, 0, 0, 0, 0, \ + 1, 1, 0, 0, 0, 0, 0, 1, \ + 1, 1, 0, 0, 0, 0, 0, 0 } + +#else /* SUPPORT_SUN_FPA */ + +/* 1 for registers that have pervasive standard uses + and are not available for the register allocator. + On the 68000, only the stack pointer is such. */ + +/* fpa0 is also reserved so that it can be used to move shit back and + forth between high fpa regs and everything else. */ + +#define FIXED_REGISTERS \ + {/* Data registers. */ \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + \ + /* Address registers. */ \ + 0, 0, 0, 0, 0, 0, 0, 1, \ + \ + /* Floating point registers \ + (if available). */ \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + \ + /* Sun3 FPA registers. */ \ + 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0 } + +/* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ +#define CALL_USED_REGISTERS \ + {1, 1, 0, 0, 0, 0, 0, 0, \ + 1, 1, 0, 0, 0, 0, 0, 1, \ + 1, 1, 0, 0, 0, 0, 0, 0, \ + /* FPA registers. */ \ + 1, 1, 1, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0 } + +#endif /* defined SUPPORT_SUN_FPA */ + + +/* Make sure everything's fine if we *don't* have a given processor. + This assumes that putting a register in fixed_regs will keep the + compiler's mitts completely off it. We don't bother to zero it out + of register classes. If neither TARGET_FPA or TARGET_68881 is set, + the compiler won't touch since no instructions that use these + registers will be valid. + + Reserve PIC_OFFSET_TABLE_REGNUM (a5) for doing PIC relocation if + position independent code is being generated by making it a + fixed register */ + +#ifndef SUPPORT_SUN_FPA + +#define CONDITIONAL_REGISTER_USAGE \ +{ \ + if (flag_pic) \ + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ +} + +#else /* defined SUPPORT_SUN_FPA */ + +#define CONDITIONAL_REGISTER_USAGE \ +{ \ + int i; \ + HARD_REG_SET x; \ + if (!TARGET_FPA) \ + { \ + COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ + if (TEST_HARD_REG_BIT (x, i)) \ + fixed_regs[i] = call_used_regs[i] = 1; \ + } \ + if (TARGET_FPA) \ + { \ + COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ + if (TEST_HARD_REG_BIT (x, i)) \ + fixed_regs[i] = call_used_regs[i] = 1; \ + } \ + if (flag_pic) \ + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ +} + +#endif /* defined SUPPORT_SUN_FPA */ + +/* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. + + On the 68000, ordinary registers hold 32 bits worth; + for the 68881 registers, a single register is always enough for + anything that can be stored in them at all. */ +#define HARD_REGNO_NREGS(REGNO, MODE) \ + ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +#ifndef SUPPORT_SUN_FPA + +/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. + On the 68000, the cpu registers can hold any mode but the 68881 registers + can hold only SFmode or DFmode. The 68881 registers can't hold anything + if 68881 use is disabled. */ + +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ + (((REGNO) < 16) \ + || ((REGNO) < 24 \ + && TARGET_68881 \ + && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ + || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT))) + +#else /* defined SUPPORT_SUN_FPA */ + +/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. + On the 68000, the cpu registers can hold any mode but the 68881 registers + can hold only SFmode or DFmode. And the 68881 registers can't hold anything + if 68881 use is disabled. However, the Sun FPA register can + (apparently) hold whatever you feel like putting in them. + If using the fpa, don't put a double in d7/a0. */ + +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ +(((REGNO) < 16 \ + && !(TARGET_FPA \ + && GET_MODE_CLASS ((MODE)) != MODE_INT \ + && GET_MODE_UNIT_SIZE ((MODE)) > 4 \ + && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \ + && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \ + || ((REGNO) < 24 \ + ? TARGET_68881 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ + || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ + : ((REGNO) < 56 ? TARGET_FPA : 0))) + +#endif /* defined SUPPORT_SUN_FPA */ + +/* Value is 1 if it is a good idea to tie two pseudo registers + when one has mode MODE1 and one has mode MODE2. + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, + for any hard reg, then this must be 0 for correct output. */ +#define MODES_TIEABLE_P(MODE1, MODE2) \ + (! TARGET_68881 \ + || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ + || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ + == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ + || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) + +/* Specify the registers used for certain standard purposes. + The values of these macros are register numbers. */ + +/* m68000 pc isn't overloaded on a register. */ +/* #define PC_REGNUM */ + +/* Register to use for pushing function arguments. */ +#define STACK_POINTER_REGNUM 15 + +/* Base register for access to local variables of the function. */ +#define FRAME_POINTER_REGNUM 14 + +/* Value should be nonzero if functions must have frame pointers. + Zero means the frame pointer need not be set up (and parms + may be accessed via the stack pointer) in functions that seem suitable. + This is computed in `reload', in reload1.c. */ +#define FRAME_POINTER_REQUIRED 0 + +/* Base register for access to arguments of the function. */ +#define ARG_POINTER_REGNUM 14 + +/* Register in which static-chain is passed to a function. */ +#define STATIC_CHAIN_REGNUM 8 + +/* Register in which address to store a structure value + is passed to a function. */ +#define STRUCT_VALUE_REGNUM 9 + +/* Define the classes of registers for register constraints in the + machine description. Also define ranges of constants. + + One of the classes must always be named ALL_REGS and include all hard regs. + If there is more than one class, another class must be named NO_REGS + and contain no registers. + + The name GENERAL_REGS must be the name of a class (or an alias for + another name such as ALL_REGS). This is the class of registers + that is allowed by "g" or "r" in a register constraint. + Also, registers outside this class are allocated only when + instructions express preferences for them. + + The classes must be numbered in nondecreasing order; that is, + a larger-numbered class must never be contained completely + in a smaller-numbered class. + + For any two classes, it is very desirable that there be another + class that represents their union. */ + +/* The 68000 has three kinds of registers, so eight classes would be + a complete set. One of them is not needed. */ + +#ifndef SUPPORT_SUN_FPA + +enum reg_class { + NO_REGS, DATA_REGS, + ADDR_REGS, FP_REGS, + GENERAL_REGS, DATA_OR_FP_REGS, + ADDR_OR_FP_REGS, ALL_REGS, + LIM_REG_CLASSES }; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +/* Give names of register classes as strings for dump file. */ + +#define REG_CLASS_NAMES \ + { "NO_REGS", "DATA_REGS", \ + "ADDR_REGS", "FP_REGS", \ + "GENERAL_REGS", "DATA_OR_FP_REGS", \ + "ADDR_OR_FP_REGS", "ALL_REGS" } + +/* Define which registers fit in which classes. + This is an initializer for a vector of HARD_REG_SET + of length N_REG_CLASSES. */ + +#define REG_CLASS_CONTENTS \ +{ \ + 0x00000000, /* NO_REGS */ \ + 0x000000ff, /* DATA_REGS */ \ + 0x0000ff00, /* ADDR_REGS */ \ + 0x00ff0000, /* FP_REGS */ \ + 0x0000ffff, /* GENERAL_REGS */ \ + 0x00ff00ff, /* DATA_OR_FP_REGS */ \ + 0x00ffff00, /* ADDR_OR_FP_REGS */ \ + 0x00ffffff, /* ALL_REGS */ \ +} + +/* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + +#define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1) + +#else /* defined SUPPORT_SUN_FPA */ + +/* + * Notes on final choices: + * + * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything + * else. + * 2) Removed all unions that involve address registers with + * floating point registers (left in unions of address and data with + * floating point). + * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS. + * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS. + * 4) Left in everything else. + */ +enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS, + FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS, + DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS, + GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS, + LIM_REG_CLASSES }; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +/* Give names of register classes as strings for dump file. */ + +#define REG_CLASS_NAMES \ + { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \ + "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \ + "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \ + "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" } + +/* Define which registers fit in which classes. + This is an initializer for a vector of HARD_REG_SET + of length N_REG_CLASSES. */ + +#define REG_CLASS_CONTENTS \ +{ \ + {0, 0}, /* NO_REGS */ \ + {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \ + {0xff000000, 0x00ffffff}, /* FPA_REGS */ \ + {0x00ff0000, 0x00000000}, /* FP_REGS */ \ + {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \ + {0x000000ff, 0x00000000}, /* DATA_REGS */ \ + {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \ + {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \ + {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\ + {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \ + {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \ + {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\ + {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\ + {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \ +} + +/* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + +extern enum reg_class regno_reg_class[]; +#define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3]) + +#endif /* SUPPORT_SUN_FPA */ + +/* The class value for index registers, and the one for base regs. */ + +#define INDEX_REG_CLASS GENERAL_REGS +#define BASE_REG_CLASS ADDR_REGS + +/* Get reg_class from a letter such as appears in the machine description. + We do a trick here to modify the effective constraints on the + machine description; we zorch the constraint letters that aren't + appropriate for a specific target. This allows us to guarantee + that a specific kind of register will not be used for a given target + without fiddling with the register classes above. */ + +#ifndef SUPPORT_SUN_FPA + +#define REG_CLASS_FROM_LETTER(C) \ + ((C) == 'a' ? ADDR_REGS : \ + ((C) == 'd' ? DATA_REGS : \ + ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ + NO_REGS) : \ + NO_REGS))) + +#else /* defined SUPPORT_SUN_FPA */ + +#define REG_CLASS_FROM_LETTER(C) \ + ((C) == 'a' ? ADDR_REGS : \ + ((C) == 'd' ? DATA_REGS : \ + ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ + NO_REGS) : \ + ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \ + NO_REGS) : \ + ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \ + NO_REGS) : \ + NO_REGS))))) + +#endif /* defined SUPPORT_SUN_FPA */ + +/* The letters I, J, K, L and M in a register constraint string + can be used to stand for particular ranges of immediate operands. + This macro defines what the ranges are. + C is the letter, and VALUE is a constant value. + Return 1 if VALUE is in the range specified by C. + + For the 68000, `I' is used for the range 1 to 8 + allowed as immediate shift counts and in addq. + `J' is used for the range of signed numbers that fit in 16 bits. + `K' is for numbers that moveq can't handle. + `L' is for range -8 to -1, range of values that can be added with subq. */ + +#define CONST_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ + (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ + (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ + (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0) + +/* + * A small bit of explanation: + * "G" defines all of the floating constants that are *NOT* 68881 + * constants. this is so 68881 constants get reloaded and the + * fpmovecr is used. "H" defines *only* the class of constants that + * the fpa can use, because these can be gotten at in any fpa + * instruction and there is no need to force reloads. + */ +#ifndef SUPPORT_SUN_FPA +#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) +#else /* defined SUPPORT_SUN_FPA */ +#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \ + (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0) +#endif /* defined SUPPORT_SUN_FPA */ + +/* Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. + On the 68000 series, use a data reg if possible when the + value is a constant in the range where moveq could be used + and we ensure that QImodes are reloaded into data regs. + Also, if a floating constant needs reloading, put it in memory + if possible. */ + +#define PREFERRED_RELOAD_CLASS(X,CLASS) \ + ((GET_CODE (X) == CONST_INT \ + && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ + && (CLASS) != ADDR_REGS) \ + ? DATA_REGS \ + : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ + ? DATA_REGS \ + : (GET_CODE (X) == CONST_DOUBLE \ + && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ + ? NO_REGS \ + : (CLASS)) + +/* Return the maximum number of consecutive registers + needed to represent mode MODE in a register of class CLASS. */ +/* On the 68000, this is the size of MODE in words, + except in the FP regs, where a single reg is always enough. */ +#ifndef SUPPORT_SUN_FPA + +#define CLASS_MAX_NREGS(CLASS, MODE) \ + ((CLASS) == FP_REGS ? 1 \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +/* Moves between fp regs and other regs are two insns. */ +#define REGISTER_MOVE_COST(CLASS1, CLASS2) \ + (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ + || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ + ? 4 : 2) + +#else /* defined SUPPORT_SUN_FPA */ + +#define CLASS_MAX_NREGS(CLASS, MODE) \ + ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +/* Moves between fp regs and other regs are two insns. */ +/* Likewise for high fpa regs and other regs. */ +#define REGISTER_MOVE_COST(CLASS1, CLASS2) \ + ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ + || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ + || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \ + || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \ + ? 4 : 2) + +#endif /* define SUPPORT_SUN_FPA */ + +/* Stack layout; function entry, exit and calling. */ + +/* Define this if pushing a word on the stack + makes the stack pointer a smaller address. */ +#define STACK_GROWS_DOWNWARD + +/* Nonzero if we need to generate stack-probe insns. + On most systems they are not needed. + When they are needed, define this as the stack offset to probe at. */ +#define NEED_PROBE 0 + +/* Define this if the nominal address of the stack frame + is at the high-address end of the local variables; + that is, each additional local variable allocated + goes at a more negative offset in the frame. */ +#define FRAME_GROWS_DOWNWARD + +/* Offset within stack frame to start allocating local variables at. + If FRAME_GROWS_DOWNWARD, this is the offset to the END of the + first local allocated. Otherwise, it is the offset to the BEGINNING + of the first local allocated. */ +#define STARTING_FRAME_OFFSET 0 + +/* If we generate an insn to push BYTES bytes, + this says how many the stack pointer really advances by. + On the 68000, sp@- in a byte insn really pushes a word. */ +#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) + +/* Offset of first parameter from the argument pointer register value. */ +#define FIRST_PARM_OFFSET(FNDECL) 8 + +/* Value is the number of byte of arguments automatically + popped when returning from a subroutine call. + FUNTYPE is the data type of the function (as a tree), + or for a library call it is an identifier node for the subroutine name. + SIZE is the number of bytes of arguments passed on the stack. + + On the 68000, the RTS insn cannot pop anything. + On the 68010, the RTD insn may be used to pop them if the number + of args is fixed, but if the number is variable then the caller + must pop them all. RTD can't be used for library calls now + because the library is compiled with the Unix compiler. + Use of RTD is a selectable option, since it is incompatible with + standard Unix calling sequences. If the option is not selected, + the caller must always pop the args. */ + +#define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ + ((TARGET_RTD && TREE_CODE (FUNTYPE) != IDENTIFIER_NODE \ + && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ + || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ + == void_type_node))) \ + ? (SIZE) : 0) + +/* Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ + +/* On the 68000 the return value is in D0 regardless. */ + +#define FUNCTION_VALUE(VALTYPE, FUNC) \ + gen_rtx (REG, TYPE_MODE (VALTYPE), 0) + +/* Define how to find the value returned by a library function + assuming the value has mode MODE. */ + +/* On the 68000 the return value is in D0 regardless. */ + +#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0) + +/* 1 if N is a possible register number for a function value. + On the 68000, d0 is the only register thus used. */ + +#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) + +/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for + more than one register. */ + +#define NEEDS_UNTYPED_CALL 0 + +/* Define this if PCC uses the nonreentrant convention for returning + structure and union values. */ + +#define PCC_STATIC_STRUCT_RETURN + +/* 1 if N is a possible register number for function argument passing. + On the 68000, no registers are used in this way. */ + +#define FUNCTION_ARG_REGNO_P(N) 0 + +/* Define a data type for recording info about an argument list + during the scan of that argument list. This data type should + hold all necessary information about the function itself + and about the args processed so far, enough to enable macros + such as FUNCTION_ARG to determine where the next arg should go. + + On the m68k, this is a single integer, which is a number of bytes + of arguments scanned so far. */ + +#define CUMULATIVE_ARGS int + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. + + On the m68k, the offset starts at 0. */ + +#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ + ((CUM) = 0) + +/* Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + (TYPE is null for libcalls where that information may not be available.) */ + +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ + ((CUM) += ((MODE) != BLKmode \ + ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ + : (int_size_in_bytes (TYPE) + 3) & ~3)) + +/* Define where to put the arguments to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). */ + +/* On the 68000 all args are pushed, except if -mregparm is specified + then the first two words of arguments are passed in d0, d1. + *NOTE* -mregparm does not work. + It exists only to test register calling conventions. */ + +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ +((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0) + +/* For an arg passed partly in registers and partly in memory, + this is the number of registers used. + For args passed entirely in registers or entirely in memory, zero. */ + +#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ +((TARGET_REGPARM && (CUM) < 8 \ + && 8 < ((CUM) + ((MODE) == BLKmode \ + ? int_size_in_bytes (TYPE) \ + : GET_MODE_SIZE (MODE)))) \ + ? 2 - (CUM) / 4 : 0) + +/* Generate the assembly code for function entry. */ +#define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE) + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#define FUNCTION_PROFILER(FILE, LABELNO) \ + asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) + +/* Output assembler code to FILE to initialize this source file's + basic block profiling info, if that has not already been done. */ + +#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ + asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \ + LABELNO, LABELNO); + +/* Output assembler code to FILE to increment the entry-count for + the BLOCKNO'th basic block in this source file. */ + +#define BLOCK_PROFILER(FILE, BLOCKNO) \ + asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO) + +/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, + the stack pointer does not matter. The value is tested only in + functions that have frame pointers. + No definition is equivalent to always zero. */ + +#define EXIT_IGNORE_STACK 1 + +/* Generate the assembly code for function exit. */ +#define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE) + +/* This is a hook for other tm files to change. */ +/* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */ + +/* Determine if the epilogue should be output as RTL. + You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ +#define USE_RETURN_INSN use_return_insn () + +/* Store in the variable DEPTH the initial difference between the + frame pointer reg contents and the stack pointer reg contents, + as of the start of the function body. This depends on the layout + of the fixed parts of the stack frame and on how registers are saved. + + On the 68k, if we have a frame, we must add one word to its length + to allow for the place that a6 is stored when we do have a frame pointer. + Otherwise, we would need to compute the offset from the frame pointer + of a local variable as a function of frame_pointer_needed, which + is hard. */ + +#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ +{ int regno; \ + int offset = -4; \ + for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ + if (regs_ever_live[regno] && ! call_used_regs[regno]) \ + offset += 12; \ + for (regno = 0; regno < 16; regno++) \ + if (regs_ever_live[regno] && ! call_used_regs[regno]) \ + offset += 4; \ + (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \ + + (get_frame_size () == 0 ? 0 : 4)); \ +} + +/* Output assembler code for a block containing the constant parts + of a trampoline, leaving space for the variable parts. */ + +/* On the 68k, the trampoline looks like this: + mov @#.,a0 + jsr @#___trampoline + jsr @#___trampoline + .long STATIC + .long FUNCTION +The reason for having three jsr insns is so that an entire line +of the instruction cache is filled in a predictable way +that will always be the same. + +We always use the assembler label ___trampoline +regardless of whether the system adds underscores. */ + +#define TRAMPOLINE_TEMPLATE(FILE) \ +{ \ + ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x207c)); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4eb9)); \ + ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "*___trampoline"));\ + ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4eb9)); \ + ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "*___trampoline"));\ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ +} + +/* Length in units of the trampoline for entering a nested function. */ + +#define TRAMPOLINE_SIZE 26 + +/* Alignment required for a trampoline. 16 is used to find the + beginning of a line in the instruction cache. */ + +#define TRAMPOLINE_ALIGN 16 + +/* Emit RTL insns to initialize the variable parts of a trampoline. + FNADDR is an RTX for the address of the function's pure code. + CXT is an RTX for the static chain value for the function. */ + +#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ +{ \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), TRAMP); \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 18)), CXT); \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 22)), FNADDR); \ +} + +/* This is the library routine that is used + to transfer control from the trampoline + to the actual nested function. */ + +/* A colon is used with no explicit operands + to cause the template string to be scanned for %-constructs. */ +/* The function name __transfer_from_trampoline is not actually used. + The function definition just permits use of "asm with operands" + (though the operand list is empty). */ +#define TRANSFER_FROM_TRAMPOLINE \ +void \ +__transfer_from_trampoline () \ +{ \ + register char *a0 asm ("%a0"); \ + asm (GLOBAL_ASM_OP " ___trampoline"); \ + asm ("___trampoline:"); \ + asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ + asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ + asm ("rts":); \ +} + +/* Addressing modes, and classification of registers for them. */ + +#define HAVE_POST_INCREMENT +/* #define HAVE_POST_DECREMENT */ + +#define HAVE_PRE_DECREMENT +/* #define HAVE_PRE_INCREMENT */ + +/* Macros to check register numbers against specific register classes. */ + +/* These assume that REGNO is a hard or pseudo reg number. + They give nonzero only if REGNO is a hard reg of the suitable class + or a pseudo reg currently allocated to a suitable hard reg. + Since they use reg_renumber, they are safe only once reg_renumber + has been allocated, which happens in local-alloc.c. */ + +#define REGNO_OK_FOR_INDEX_P(REGNO) \ +((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) +#define REGNO_OK_FOR_BASE_P(REGNO) \ +(((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) +#define REGNO_OK_FOR_DATA_P(REGNO) \ +((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) +#define REGNO_OK_FOR_FP_P(REGNO) \ +(((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) +#ifdef SUPPORT_SUN_FPA +#define REGNO_OK_FOR_FPA_P(REGNO) \ +(((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56)) +#endif + +/* Now macros that check whether X is a register and also, + strictly, whether it is in a specified class. + + These macros are specific to the 68000, and may be used only + in code for printing assembler insns and in conditions for + define_optimization. */ + +/* 1 if X is a data register. */ + +#define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) + +/* 1 if X is an fp register. */ + +#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) + +/* 1 if X is an address register */ + +#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) + +#ifdef SUPPORT_SUN_FPA +/* 1 if X is a register in the Sun FPA. */ +#define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X))) +#else +/* Answer must be no if we don't have an FPA. */ +#define FPA_REG_P(X) 0 +#endif + +/* Maximum number of registers that can appear in a valid memory address. */ + +#define MAX_REGS_PER_ADDRESS 2 + +/* Recognize any constant value that is a valid address. */ + +#define CONSTANT_ADDRESS_P(X) \ + (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ + || GET_CODE (X) == HIGH) + +/* Nonzero if the constant value X is a legitimate general operand. + It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_CONSTANT_P(X) 1 + +/* Nonzero if the constant value X is a legitimate general operand + when generating PIC code. It is given that flag_pic is on and + that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_PIC_OPERAND_P(X) \ + (! symbolic_operand (X, VOIDmode) \ + || ((GET_CODE(X) == SYMBOL_REF) && SYMBOL_REF_FLAG(X))) + +/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx + and check its validity for a certain class. + We have two alternate definitions for each of them. + The usual definition accepts all pseudo regs; the other rejects + them unless they have been allocated suitable hard regs. + The symbol REG_OK_STRICT causes the latter definition to be used. + + Most source files want to accept pseudo regs in the hope that + they will get allocated to the class that the insn wants them to be in. + Source files for reload pass need to be strict. + After reload, it makes no difference, since pseudo regs have + been eliminated by then. */ + +#ifndef REG_OK_STRICT + +/* Nonzero if X is a hard reg that can be used as an index + or if it is a pseudo reg. */ +#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) +/* Nonzero if X is a hard reg that can be used as a base reg + or if it is a pseudo reg. */ +#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) + +#else + +/* Nonzero if X is a hard reg that can be used as an index. */ +#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) +/* Nonzero if X is a hard reg that can be used as a base reg. */ +#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) + +#endif + +/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + When generating PIC, an address involving a SYMBOL_REF is legitimate + if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. + We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, + and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. + + Likewise for a LABEL_REF when generating PIC. + + The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ + +#define INDIRECTABLE_1_ADDRESS_P(X) \ + ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ + || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ + || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ + && REG_P (XEXP (X, 0)) \ + && REG_OK_FOR_BASE_P (XEXP (X, 0))) \ + || (GET_CODE (X) == PLUS \ + && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ + && GET_CODE (XEXP (X, 1)) == CONST_INT \ + && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000) \ + || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ + && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ + || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ + && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) \ + +#if 0 +/* This should replace the last two (non-pic) lines + except that Sun's assembler does not seem to handle such operands. */ + && (TARGET_68020 ? CONSTANT_ADDRESS_P (XEXP (X, 1)) \ + : (GET_CODE (XEXP (X, 1)) == CONST_INT \ + && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) +#endif + + +#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ +{ if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } + +/* Only labels on dispatch tables are valid for indexing from. */ +#define GO_IF_INDEXABLE_BASE(X, ADDR) \ +{ rtx temp; \ + if (GET_CODE (X) == LABEL_REF \ + && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ + && GET_CODE (temp) == JUMP_INSN \ + && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ + || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ + goto ADDR; \ + if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; } + +#define GO_IF_INDEXING(X, ADDR) \ +{ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ + { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ + if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ + { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } + +#define GO_IF_INDEXED_ADDRESS(X, ADDR) \ +{ GO_IF_INDEXING (X, ADDR); \ + if (GET_CODE (X) == PLUS) \ + { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ + && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \ + { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ + if (GET_CODE (XEXP (X, 0)) == CONST_INT \ + && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \ + { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } + +#define LEGITIMATE_INDEX_REG_P(X) \ + ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ + || (GET_CODE (X) == SIGN_EXTEND \ + && GET_CODE (XEXP (X, 0)) == REG \ + && GET_MODE (XEXP (X, 0)) == HImode \ + && REG_OK_FOR_INDEX_P (XEXP (X, 0)))) + +#define LEGITIMATE_INDEX_P(X) \ + (LEGITIMATE_INDEX_REG_P (X) \ + || (TARGET_68020 && GET_CODE (X) == MULT \ + && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ + && GET_CODE (XEXP (X, 1)) == CONST_INT \ + && (INTVAL (XEXP (X, 1)) == 2 \ + || INTVAL (XEXP (X, 1)) == 4 \ + || INTVAL (XEXP (X, 1)) == 8))) + +#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +{ GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ + GO_IF_INDEXED_ADDRESS (X, ADDR); } + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was called. + In some cases it is useful to look at this to decide what needs to be done. + + MODE and WIN are passed so that this macro can use + GO_IF_LEGITIMATE_ADDRESS. + + It is always safe for this macro to do nothing. It exists to recognize + opportunities to optimize the output. + + For the 68000, we handle X+REG by loading X into a register R and + using R+REG. R will go in an address reg and indexing will be used. + However, if REG is a broken-out memory address or multiplication, + nothing needs to be done because REG can certainly go in an address reg. */ + +#define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } +#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ +{ register int ch = (X) != (OLDX); \ + if (GET_CODE (X) == PLUS) \ + { int copied = 0; \ + if (GET_CODE (XEXP (X, 0)) == MULT) \ + { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ + if (GET_CODE (XEXP (X, 1)) == MULT) \ + { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ + if (ch && GET_CODE (XEXP (X, 1)) == REG \ + && GET_CODE (XEXP (X, 0)) == REG) \ + goto WIN; \ + if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ + if (GET_CODE (XEXP (X, 0)) == REG \ + || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ + && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ + && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ + { register rtx temp = gen_reg_rtx (Pmode); \ + register rtx val = force_operand (XEXP (X, 1), 0); \ + emit_move_insn (temp, val); \ + COPY_ONCE (X); \ + XEXP (X, 1) = temp; \ + goto WIN; } \ + else if (GET_CODE (XEXP (X, 1)) == REG \ + || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ + && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ + && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ + { register rtx temp = gen_reg_rtx (Pmode); \ + register rtx val = force_operand (XEXP (X, 0), 0); \ + emit_move_insn (temp, val); \ + COPY_ONCE (X); \ + XEXP (X, 0) = temp; \ + goto WIN; }}} + +/* Go to LABEL if ADDR (a legitimate address expression) + has an effect that depends on the machine mode it is used for. + On the 68000, only predecrement and postincrement address depend thus + (the amount of decrement or increment being the length of the operand). */ + +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ + if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL + +/* Specify the machine mode that this machine uses + for the index in the tablejump instruction. */ +#define CASE_VECTOR_MODE HImode + +/* Define this if the tablejump instruction expects the table + to contain offsets from the address of the table. + Do not define this if the table should contain absolute addresses. */ +#define CASE_VECTOR_PC_RELATIVE + +/* Specify the tree operation to be used to convert reals to integers. */ +#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR + +/* This is the kind of divide that is easiest to do in the general case. */ +#define EASY_DIV_EXPR TRUNC_DIV_EXPR + +/* Define this as 1 if `char' should by default be signed; else as 0. */ +#define DEFAULT_SIGNED_CHAR 1 + +/* Don't cse the address of the function being compiled. */ +#define NO_RECURSIVE_FUNCTION_CSE + +/* Max number of bytes we can move from memory to memory + in one reasonably fast instruction. */ +#define MOVE_MAX 4 + +/* Define this if zero-extension is slow (more than one real instruction). */ +#define SLOW_ZERO_EXTEND + +/* Nonzero if access to memory by bytes is slow and undesirable. */ +#define SLOW_BYTE_ACCESS 0 + +/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +/* We assume that the store-condition-codes instructions store 0 for false + and some other value for true. This is the value stored for true. */ + +#define STORE_FLAG_VALUE -1 + +/* When a prototype says `char' or `short', really pass an `int'. */ +#define PROMOTE_PROTOTYPES + +/* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. */ +#define Pmode SImode + +/* A function address in a call instruction + is a byte address (for indexing purposes) + so give the MEM rtx a byte's mode. */ +#define FUNCTION_MODE QImode + +/* Compute the cost of computing a constant rtl expression RTX + whose rtx-code is CODE. The body of this macro is a portion + of a switch statement. If the code is computed here, + return it with a return statement. Otherwise, break from the switch. */ + +#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ + case CONST_INT: \ + /* Constant zero is super cheap due to clr instruction. */ \ + if (RTX == const0_rtx) return 0; \ + /* Constants between -128 and 127 are cheap due to moveq */ \ + if (INTVAL (RTX) >= -128 && INTVAL (RTX) <= 127) return 1; \ + /* Constants between -136 and 254 are easily generated */ \ + /* by intelligent uses of moveq, add[q], and subq */ \ + if ((OUTER_CODE) == SET && INTVAL (RTX) >= -136 \ + && INTVAL (RTX) <= 254) return 2; \ + case CONST: \ + case LABEL_REF: \ + case SYMBOL_REF: \ + return 3; \ + case CONST_DOUBLE: \ + return 5; + +/* Compute the cost of various arithmetic operations. + These are vaguely right for a 68020. */ +/* The costs for long multiply have been adjusted to + work properly in synth_mult on the 68020, + relative to an average of the time for add and the time for shift, + taking away a little more because sometimes move insns are needed. */ +#define MULL_COST (TARGET_68040 ? 5 : 13) +#define MULW_COST (TARGET_68040 ? 3 : 8) + +#define RTX_COSTS(X,CODE,OUTER_CODE) \ + case PLUS: \ + /* An lea costs about three times as much as a simple add. */ \ + if (GET_MODE (X) == SImode \ + && GET_CODE (XEXP (X, 0)) == REG \ + && GET_CODE (XEXP (X, 1)) == MULT \ + && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ + && GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \ + && (INTVAL (XEXP (XEXP (X, 1), 1)) == 2 \ + || INTVAL (XEXP (XEXP (X, 1), 1)) == 4 \ + || INTVAL (XEXP (XEXP (X, 1), 1)) == 8)) \ + return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \ + break; \ + case ASHIFT: \ + case ASHIFTRT: \ + case LSHIFT: \ + case LSHIFTRT: \ + /* A shift by a big integer takes an extra instruction. */ \ + if (GET_CODE (XEXP (X, 1)) == CONST_INT \ + && (INTVAL (XEXP (X, 1)) == 16)) \ + return COSTS_N_INSNS (2); /* clrw;swap */ \ + if (GET_CODE (XEXP (X, 1)) == CONST_INT \ + && !(INTVAL (XEXP (X, 1)) > 0 \ + && INTVAL (XEXP (X, 1)) <= 8)) \ + return COSTS_N_INSNS (3); /* lsr #i,dn */ \ + break; \ + case MULT: \ + if (GET_CODE (XEXP (x, 1)) == CONST_INT \ + && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) \ + { \ + /* A shift by a big integer takes an extra instruction. */ \ + if (GET_CODE (XEXP (X, 1)) == CONST_INT \ + && (INTVAL (XEXP (X, 1)) == (1 << 16))) \ + return COSTS_N_INSNS (2); /* clrw;swap */ \ + if (GET_CODE (XEXP (X, 1)) == CONST_INT \ + && !(INTVAL (XEXP (X, 1)) > 1 \ + && INTVAL (XEXP (X, 1)) <= 256)) \ + return COSTS_N_INSNS (3); /* lsr #i,dn */ \ + break; \ + } \ + else if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ + return COSTS_N_INSNS (MULW_COST); \ + else \ + return COSTS_N_INSNS (MULL_COST); \ + break; \ + case DIV: \ + case UDIV: \ + case MOD: \ + case UMOD: \ + if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ + return COSTS_N_INSNS (27); /* div.w */ \ + return COSTS_N_INSNS (43); /* div.l */ + +/* Tell final.c how to eliminate redundant test instructions. */ + +/* Here we define machine-dependent flags and fields in cc_status + (see `conditions.h'). */ + +/* Set if the cc value is actually in the 68881, so a floating point + conditional branch must be output. */ +#define CC_IN_68881 04000 + +/* Store in cc_status the expressions that the condition codes will + describe after execution of an instruction whose pattern is EXP. + Do not alter them if the instruction would not alter the cc's. */ + +/* On the 68000, all the insns to store in an address register fail to + set the cc's. However, in some cases these instructions can make it + possibly invalid to use the saved cc's. In those cases we clear out + some or all of the saved cc's so they won't be used. */ + +#define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) + +#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ +{ if (cc_prev_status.flags & CC_IN_68881) \ + return FLOAT; \ + if (cc_prev_status.flags & CC_NO_OVERFLOW) \ + return NO_OV; \ + return NORMAL; } + +/* Control the assembler format that we output. */ + +/* Output at beginning of assembler file. */ + +#define ASM_FILE_START(FILE) \ + fprintf (FILE, "#NO_APP\n"); + +/* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + +#define ASM_APP_ON "#APP\n" + +/* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + +#define ASM_APP_OFF "#NO_APP\n" + +/* Output before read-only data. */ + +#define TEXT_SECTION_ASM_OP ".text" + +/* Output before writable data. */ + +#define DATA_SECTION_ASM_OP ".data" + +/* Here are four prefixes that are used by asm_fprintf to + facilitate customization for alternate assembler syntaxes. + Machines with no likelihood of an alternate syntax need not + define these and need not use asm_fprintf. */ + +/* The prefix for register names. Note that REGISTER_NAMES + is supposed to include this prefix. */ + +#define REGISTER_PREFIX "" + +/* The prefix for local labels. You should be able to define this as + an empty string, or any arbitrary string (such as ".", ".L%", etc) + without having to make any other changes to account for the specific + definition. Note it is a string literal, not interpreted by printf + and friends. */ + +#define LOCAL_LABEL_PREFIX "" + +/* The prefix to add to user-visible assembler symbols. */ + +#define USER_LABEL_PREFIX "_" + +/* The prefix for immediate operands. */ + +#define IMMEDIATE_PREFIX "#" + +/* How to refer to registers in assembler output. + This sequence is indexed by compiler's hard-register-number (see above). */ + +#ifndef SUPPORT_SUN_FPA + +#define REGISTER_NAMES \ +{"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ + "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ + "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" } + +#else /* SUPPORTED_SUN_FPA */ + +#define REGISTER_NAMES \ +{"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ + "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ + "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \ + "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \ + "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \ + "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \ + "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" } + +#endif /* defined SUPPORT_SUN_FPA */ + +/* How to renumber registers for dbx and gdb. + On the Sun-3, the floating point registers have numbers + 18 to 25, not 16 to 23 as they do in the compiler. */ + +#define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) + +/* This is how to output the definition of a user-level label named NAME, + such as the label on a static function or variable NAME. */ + +#define ASM_OUTPUT_LABEL(FILE,NAME) \ + do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) + +/* This is how to output a command to make the user-level label named NAME + defined for reference from other files. */ + +#define GLOBAL_ASM_OP ".globl" +#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ + do { fprintf (FILE, "%s ", GLOBAL_ASM_OP); \ + assemble_name (FILE, NAME); \ + fputs ("\n", FILE);} while (0) + +/* This is how to output a reference to a user-level label named NAME. + `assemble_name' uses this. */ + +#define ASM_OUTPUT_LABELREF(FILE,NAME) \ + asm_fprintf (FILE, "%0U%s", NAME) + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM) + +/* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM) + +/* This is how to output a `long double' extended real constant. */ + +#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ +do { long l[3]; \ + REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ + if (sizeof (int) == sizeof (long)) \ + fprintf (FILE, "\t.long 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]); \ + else \ + fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]); \ + } while (0) + +/* This is how to output an assembler line defining a `double' constant. */ + +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + do { char dstr[30]; \ + REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ + fprintf (FILE, "\t.double 0r%s\n", dstr); \ + } while (0) + +/* This is how to output an assembler line defining a `float' constant. */ + +#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ +do { long l; \ + REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ + if (sizeof (int) == sizeof (long)) \ + fprintf (FILE, "\t.long 0x%x\n", l); \ + else \ + fprintf (FILE, "\t.long 0x%lx\n", l); \ + } while (0) + +/* This is how to output an assembler line defining an `int' constant. */ + +#define ASM_OUTPUT_INT(FILE,VALUE) \ +( fprintf (FILE, "\t.long "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +/* Likewise for `char' and `short' constants. */ + +#define ASM_OUTPUT_SHORT(FILE,VALUE) \ +( fprintf (FILE, "\t.word "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +#define ASM_OUTPUT_CHAR(FILE,VALUE) \ +( fprintf (FILE, "\t.byte "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +/* This is how to output an assembler line for a numeric constant byte. */ + +#define ASM_OUTPUT_BYTE(FILE,VALUE) \ + fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) + +/* This is how to output an insn to push a register on the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) + +/* This is how to output an insn to pop a register from the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) + +/* This is how to output an element of a case-vector that is absolute. + (The 68000 does not use such vectors, + but we must define this macro anyway.) */ + +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ + asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) + +/* This is how to output an element of a case-vector that is relative. */ + +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +/* We don't have a way to align to more than a two-byte boundary, so do the + best we can and don't complain. */ +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG) >= 1) \ + fprintf (FILE, "\t.even\n"); + +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.skip %u\n", (SIZE)) + +/* This says how to output an assembler line + to define a global common symbol. */ + +#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".comm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* This says how to output an assembler line + to define a local common symbol. */ + +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".lcomm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable named NAME. + LABELNO is an integer which is different for each call. */ + +#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ +( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ + sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) + +/* Define the parentheses used to group arithmetic operations + in assembler code. */ + +#define ASM_OPEN_PAREN "(" +#define ASM_CLOSE_PAREN ")" + +/* Define results of standard character escape sequences. */ +#define TARGET_BELL 007 +#define TARGET_BS 010 +#define TARGET_TAB 011 +#define TARGET_NEWLINE 012 +#define TARGET_VT 013 +#define TARGET_FF 014 +#define TARGET_CR 015 + +/* Output a float value (represented as a C double) as an immediate operand. + This macro is a 68k-specific macro. */ + +#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ + do { \ + if (CODE == 'f') \ + { \ + char dstr[30]; \ + REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \ + asm_fprintf ((FILE), "%I0r%s", dstr); \ + } \ + else \ + { \ + long l; \ + REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ + if (sizeof (int) == sizeof (long)) \ + asm_fprintf ((FILE), "%I0x%x", l); \ + else \ + asm_fprintf ((FILE), "%I0x%lx", l); \ + } \ + } while (0) + +/* Output a double value (represented as a C double) as an immediate operand. + This macro is a 68k-specific macro. */ +#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ + do { char dstr[30]; \ + REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ + asm_fprintf (FILE, "%I0r%s", dstr); \ + } while (0) + +/* Note, long double immediate operands are not actually + generated by m68k.md. */ +#define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ + do { char dstr[30]; \ + REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ + asm_fprintf (FILE, "%I0r%s", dstr); \ + } while (0) + +/* Print operand X (an rtx) in assembler syntax to file FILE. + CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. + For `%' followed by punctuation, CODE is the punctuation and X is null. + + On the 68000, we use several CODE characters: + '.' for dot needed in Motorola-style opcode names. + '-' for an operand pushing on the stack: + sp@-, -(sp) or -(%sp) depending on the style of syntax. + '+' for an operand pushing on the stack: + sp@+, (sp)+ or (%sp)+ depending on the style of syntax. + '@' for a reference to the top word on the stack: + sp@, (sp) or (%sp) depending on the style of syntax. + '#' for an immediate operand prefix (# in MIT and Motorola syntax + but & in SGS syntax). + '!' for the fpcr register (used in some float-to-fixed conversions). + '$' for the letter `s' in an op code, but only on the 68040. + '&' for the letter `d' in an op code, but only on the 68040. + '/' for register prefix needed by longlong.h. + + 'b' for byte insn (no effect, on the Sun; this is for the ISI). + 'd' to force memory addressing to be absolute, not relative. + 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) + 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather + than directly). Second part of 'y' below. + 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), + or print pair of registers as rx:ry. + 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs + CONST_DOUBLE's as SunFPA constant RAM registers if + possible, so it should not be used except for the SunFPA. */ + +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ + ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ + || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ + || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand X. X is an RTL + expression. + + CODE is a value that can be used to specify one of several ways + of printing the operand. It is used when identical operands + must be printed differently depending on the context. CODE + comes from the `%' specification that was used to request + printing of the operand. If the specification was just `%DIGIT' + then CODE is 0; if the specification was `%LTR DIGIT' then CODE + is the ASCII code for LTR. + + If X is a register, this macro should print the register's name. + The names can be found in an array `reg_names' whose type is + `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. + + When the machine description has a specification `%PUNCT' (a `%' + followed by a punctuation character), this macro is called with + a null pointer for X and the punctuation character for CODE. + + See m68k.c for the m68k specific codes. */ + +#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand that is a memory + reference whose address is ADDR. ADDR is an RTL expression. + + On some machines, the syntax for a symbolic address depends on + the section that the address refers to. On these machines, + define the macro `ENCODE_SECTION_INFO' to store the information + into the `symbol_ref', and then check for it here. */ + +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) + + +/* Define functions defined in aux-output.c and used in templates. */ + +extern char *output_move_double (); +extern char *output_move_const_single (); +extern char *output_move_const_double (); +extern char *output_btst (); + +/* +Local variables: +version-control: t +End: +*/ diff --git a/gnu/usr.bin/gcc2/arch/m68k/md b/gnu/usr.bin/gcc2/arch/m68k/md new file mode 100644 index 000000000000..e42792217036 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/md @@ -0,0 +1,5628 @@ +;;- Machine description for GNU compiler +;;- Motorola 68000 Version +;; Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc. + +;; This file is part of GNU CC. + +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. + +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + +;; $Id: md,v 1.1 1993/11/25 01:26:24 paulus Exp $ + + +;;- instruction definitions + +;;- @@The original PO technology requires these to be ordered by speed, +;;- @@ so that assigner will pick the fastest. + +;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. + +;;- When naming insn's (operand 0 of define_insn) be careful about using +;;- names from other targets machine descriptions. + +;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code +;;- updates for most instructions. + +;;- Operand classes for the register allocator: +;;- 'a' one of the address registers can be used. +;;- 'd' one of the data registers can be used. +;;- 'f' one of the m68881 registers can be used +;;- 'r' either a data or an address register can be used. +;;- 'x' if one of the Sun FPA registers +;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15). + +;;- Immediate Floating point operator constraints +;;- 'G' a floating point constant that is *NOT* one of the standard +;; 68881 constant values (to force calling output_move_const_double +;; to get it from rom if it is a 68881 constant). +;;- 'H' one of the standard FPA constant values +;; +;; See the functions standard_XXX_constant_p in output-m68k.c for more +;; info. + +;;- Immediate integer operand constraints: +;;- 'I' 1 .. 8 +;;- 'J' -32768 .. 32767 +;;- 'K' all integers EXCEPT -128 .. 127 +;;- 'L' -8 .. -1 + +;;- Assembler specs: +;;- "%." size separator ("." or "") move%.l d0,d1 +;;- "%#" immediate separator ("#" or "") move%.l %#0,d0 +;;- "%-" push operand "sp@-" move%.l d0,%- +;;- "%+" pop operand "sp@+" move%.l d0,%+ +;;- "%@" top of stack "sp@" move%.l d0,%@ +;;- "%!" fpcr register +;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1 +;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1 + +;;- Information about 68040 port. + +;;- The 68040 executes all 68030 and 68881/2 instructions, but some must +;;- be emulated in software by the OS. It is faster to avoid these +;;- instructions and issue a library call rather than trapping into +;;- the kernel. The affected instructions are fintrz and fscale. The +;;- TARGET_68040 flag turns the use of the opcodes off. + +;;- The '040 also implements a set of new floating-point instructions +;;- which specify the rounding precision in the opcode. This finally +;;- permit the 68k series to be truly IEEE compliant, and solves all +;;- issues of excess precision accumulating in the extended registers. +;;- By default, GCC does not use these instructions, since such code will +;;- not run on an '030. To use these instructions, use the -m68040-only +;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY, +;;- you can make these instructions the default. + +;;- These new instructions aren't directly in the md. They are brought +;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather +;;- than "". + + +;;- FPA port explanation: + +;;- Usage of the Sun FPA and the 68881 together + +;;- The current port of gcc to the sun fpa disallows use of the m68881 +;;- instructions completely if code is targeted for the fpa. This is +;;- for the following reasons: + +;;- 1) Expressing the preference hierarchy (ie. use the fpa if you +;;- can, the 68881 otherwise, and data registers only if you are +;;- forced to it) is a bitch with the current constraint scheme, +;;- especially since it would have to work for any combination of +;;- -mfpa, -m68881. + +;;- 2) There are no instructions to move between the two types of +;;- registers; the stack must be used as an intermediary. + +;;- It could indeed be done; I think the best way would be to have +;;- separate patterns for TARGET_FPA (which implies a 68881), +;;- TARGET_68881, and no floating point co-processor. Use +;;- define_expands for all of the named instruction patterns, and +;;- include code in the FPA instruction to deal with the 68881 with +;;- preferences specifically set to favor the fpa. Some of this has +;;- already been done: +;;- +;;- 1) Separation of most of the patterns out into a TARGET_FPA +;;- case and a TARGET_68881 case (the exceptions are the patterns +;;- which would need one define_expand and three define_insn's under +;;- it (with a lot of duplicate code between them) to replace the +;;- current single define_insn. These are mov{[ds]f,[ds]i} and the +;;- first two patterns in the md. +;;- +;;- Some would still have to be done: +;;- +;;- 1) Add code to the fpa patterns which correspond to 68881 +;;- patterns to deal with the 68881 case (including preferences!). +;;- What you might actually do here is combine the fpa and 68881 code +;;- back together into one pattern for those instructions where it's +;;- absolutely necessary and save yourself some duplicate code. I'm +;;- not completely sure as to whether you could get away with doing +;;- this only for the mov* insns, or if you'd have to do it for all +;;- named insns. +;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle +;;- moving between fpa regs and 68881 regs. + +;;- Since the fpa is more powerful than the 68881 and also has more +;;- registers, and since I think the resultant md would be medium ugly +;;- (lot's of duplicate code, ugly constraint strings), I elected not +;;- to do this change. + +;;- Another reason why someone *might* want to do the change is to +;;- control which register classes are accessed in a slightly cleaner +;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in +;;- the internals manual. + +;;- Yet another reason why someone might want to do this change is to +;;- allow use of some of the 68881 insns which have no equivalent on +;;- the fpa. The sqrt instruction comes fairly quickly to mind. + +;;- If this is ever done, don't forget to change sun3.h so that +;;- it *will* define __HAVE_68881__ when the FPA is in use. + +;;- Condition code hack + +;;- When a floating point compare is done in the fpa, the resulting +;;- condition codes are left in the fpastatus register. The values in +;;- this register must be moved into the 68000 cc register before any +;;- jump is executed. Once this has been done, regular jump +;;- instructions are fine (ie. floating point jumps are not necessary. +;;- They are only done if the cc is in the 68881). + +;;- The instructions that move the fpastatus register to the 68000 +;;- register clobber a data register (the move cannot be done direct). +;;- These instructions might be bundled either with the compare +;;- instruction, or the branch instruction. If we were using both the +;;- fpa and the 68881 together, we would wish to only mark the +;;- register clobbered if we were doing the compare in the fpa, but I +;;- think that that decision (whether to clobber the register or not) +;;- must be done before register allocation (makes sense) and hence we +;;- can't know if the floating point compare will be done in the fpa +;;- or the fp. So whenever we are asked for code that uses the fpa, +;;- we will mark a data register as clobbered. This is reasonable, as +;;- almost all floating point compare operations done with fpa code +;;- enabled will be done in the fpa. It's even more reasonable since +;;- we decided to make the 68881 and the fpa mutually exclusive. + +;;- We place to code to move the fpastatus register inside of a +;;- define_expand so that we can do it conditionally based on whether +;;- we are targeting an fpa or not. + +;;- This still leaves us with the question of where we wish to put the +;;- code to move the fpastatus reg. If we put it in the compare +;;- instruction, we can restrict the clobbering of the register to +;;- floating point compares, but we can't take advantage of floating +;;- point subtracts & etc. that alter the fpastatus register. If we +;;- put it in the branch instruction, all branches compiled with fpa +;;- code enabled will clobber a data register, but we will be able to +;;- take advantage of fpa subtracts. This balance favors putting the +;;- code in with the compare instruction. + +;;- Note that if some enterprising hacker should decide to switch +;;- this, he'll need to modify the code in NOTICE_UPDATE_CC. + +;;- Usage of the top 16 fpa registers + +;;- The only locations which we may transfer fpa registers 16-31 from +;;- or to are the fpa registers 0-15. (68000 registers and memory +;;- locations are impossible). This causes problems in gcc, which +;;- assumes that mov?? instructions require no additional registers +;;- (see section 11.7) and since floating point moves *must* be +;;- supported into general registers (see section 12.3 under +;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere. + +;;- My solution was to reserve fpa0 for moves into or out of these top +;;- 16 registers and to disparage the choice to reload into or out of +;;- these registers as much as I could. That alternative is always +;;- last in the list, so it will not be used unless all else fails. I +;;- will note that according to my current information, sun's compiler +;;- doesn't use these top 16 registers at all. + +;;- There is another possible way to do it. I *believe* that if you +;;- make absolutely sure that the code will not be executed in the +;;- reload pass, you can support the mov?? names with define_expands +;;- which require new registers. This may be possible by the +;;- appropriate juggling of constraints. I may come back to this later. + +;;- Usage of constant RAM + +;;- This has been handled correctly (I believe) but the way I've done +;;- it could use a little explanation. The constant RAM can only be +;;- accessed when the instruction is in "command register" mode. +;;- "command register" mode means that no accessing of memory or the +;;- 68000 registers is being done. This can be expressed easily in +;;- constraints, so generally the mode of the instruction is +;;- determined by a branch off of which_alternative. In outputting +;;- instructions, a 'w' means to output an access to the constant ram +;;- (if the arg is CONST_DOUBLE and is one of the available +;;- constants), and 'x' means to output a register pair (if the arg is +;;- a 68000 register) and a 'y' is the combination of the above two +;;- processes. You use a 'y' in two operand DF instructions where you +;;- *know* the other operand is an fpa register, you use an 'x' in DF +;;- instructions where the arg might be a 68000 register and the +;;- instruction is *not* in "command register" mode, and you use a 'w' +;;- in two situations: 1) The instruction *is* in command register +;;- mode (and hence won't be accessing 68000 registers), or 2) The +;;- instruction is a two operand SF instruction where you know the +;;- other operand is an fpa register. + +;;- Optimization issues + +;;- I actually think that I've included all of the fpa instructions +;;- that should be included. Note that if someone is interested in +;;- doing serious floating point work on the sun fpa, I would advise +;;- the use of the "asm" instruction in gcc to allow you to use the +;;- sin, cos, and exponential functions on the fpa board. + +;;- END FPA Explanation Section. + + +;;- Some of these insn's are composites of several m68000 op codes. +;;- The assembler (or final @@??) insures that the appropriate one is +;;- selected. + +(define_insn "" + [(set (match_operand:DF 0 "push_operand" "=m") + (match_operand:DF 1 "general_operand" "ro<>fyE"))] + "" + "* +{ + if (FP_REG_P (operands[1])) + return \"fmove%.d %f1,%0\"; + if (FPA_REG_P (operands[1])) + return \"fpmove%.d %1, %x0\"; + return output_move_double (operands); +}") + +(define_insn "" + [(set (match_operand:DI 0 "push_operand" "=m") + (match_operand:DI 1 "general_operand" "ro<>Fy"))] + "" + "* +{ + return output_move_double (operands); +}") + +;; We don't want to allow a constant operand for test insns because +;; (set (cc0) (const_int foo)) has no mode information. Such insns will +;; be folded while optimizing anyway. +(define_insn "tstsi" + [(set (cc0) + (match_operand:SI 0 "nonimmediate_operand" "rm"))] + "" + "* +{ +#ifdef ISI_OV + /* ISI's assembler fails to handle tstl a0. */ + if (! ADDRESS_REG_P (operands[0])) +#else + if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) +#endif + return \"tst%.l %0\"; + /* If you think that the 68020 does not support tstl a0, + reread page B-167 of the 68020 manual more carefully. */ + /* On an address reg, cmpw may replace cmpl. */ +#ifdef SGS_CMP_ORDER + return \"cmp%.w %0,%#0\"; +#else + return \"cmp%.w %#0,%0\"; +#endif +}") + +;; This can't use an address register, because comparisons +;; with address registers as second operand always test the whole word. +(define_insn "tsthi" + [(set (cc0) + (match_operand:HI 0 "nonimmediate_operand" "dm"))] + "" + "tst%.w %0") + +(define_insn "tstqi" + [(set (cc0) + (match_operand:QI 0 "nonimmediate_operand" "dm"))] + "" + "tst%.b %0") + +(define_expand "tstsf" + [(set (cc0) + (match_operand:SF 0 "general_operand" ""))] + "TARGET_68881 || TARGET_FPA" + " +{ + if (TARGET_FPA) + { + emit_insn (gen_tstsf_fpa (operands[0])); + DONE; + } +}") + +(define_insn "tstsf_fpa" + [(set (cc0) + (match_operand:SF 0 "general_operand" "xmdF")) + (clobber (match_scratch:SI 1 "=d"))] + "TARGET_FPA" + "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc") + +(define_insn "" + [(set (cc0) + (match_operand:SF 0 "general_operand" "fdm"))] + "TARGET_68881" + "* +{ + cc_status.flags = CC_IN_68881; + if (FP_REG_P (operands[0])) + return \"ftst%.x %0\"; + return \"ftst%.s %0\"; +}") + +(define_expand "tstdf" + [(set (cc0) + (match_operand:DF 0 "general_operand" ""))] + "TARGET_68881 || TARGET_FPA" + " +{ + if (TARGET_FPA) + { + emit_insn (gen_tstsf_fpa (operands[0])); + DONE; + } +}") + +(define_insn "tstdf_fpa" + [(set (cc0) + (match_operand:DF 0 "general_operand" "xrmF")) + (clobber (match_scratch:SI 1 "=d"))] + "TARGET_FPA" + "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc") + +(define_insn "" + [(set (cc0) + (match_operand:DF 0 "general_operand" "fm"))] + "TARGET_68881" + "* +{ + cc_status.flags = CC_IN_68881; + if (FP_REG_P (operands[0])) + return \"ftst%.x %0\"; + return \"ftst%.d %0\"; +}") + +;; compare instructions. + +;; A composite of the cmp, cmpa, & cmpi m68000 op codes. +(define_insn "cmpsi" + [(set (cc0) + (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>") + (match_operand:SI 1 "general_operand" "mr,Ksr,>")))] + "" + "* +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + return \"cmpm%.l %1,%0\"; + if (REG_P (operands[1]) + || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) + { cc_status.flags |= CC_REVERSED; +#ifdef SGS_CMP_ORDER + return \"cmp%.l %d1,%d0\"; +#else + return \"cmp%.l %d0,%d1\"; +#endif + } +#ifdef SGS_CMP_ORDER + return \"cmp%.l %d0,%d1\"; +#else + return \"cmp%.l %d1,%d0\"; +#endif +}") + +(define_insn "cmphi" + [(set (cc0) + (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m") + (match_operand:HI 1 "general_operand" "d,rnm,m,n")))] + "" + "* +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + return \"cmpm%.w %1,%0\"; + if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1])) + || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) + { cc_status.flags |= CC_REVERSED; +#ifdef SGS_CMP_ORDER + return \"cmp%.w %d1,%d0\"; +#else + return \"cmp%.w %d0,%d1\"; +#endif + } +#ifdef SGS_CMP_ORDER + return \"cmp%.w %d0,%d1\"; +#else + return \"cmp%.w %d1,%d0\"; +#endif +}") + +(define_insn "cmpqi" + [(set (cc0) + (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>") + (match_operand:QI 1 "general_operand" "dm,nd,>")))] + "" + "* +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + return \"cmpm%.b %1,%0\"; + if (REG_P (operands[1]) + || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) + { cc_status.flags |= CC_REVERSED; +#ifdef SGS_CMP_ORDER + return \"cmp%.b %d1,%d0\"; +#else + return \"cmp%.b %d0,%d1\"; +#endif + } +#ifdef SGS_CMP_ORDER + return \"cmp%.b %d0,%d1\"; +#else + return \"cmp%.b %d1,%d0\"; +#endif +}") + +(define_expand "cmpdf" + [(set (cc0) + (compare (match_operand:DF 0 "general_operand" "") + (match_operand:DF 1 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + " +{ + if (TARGET_FPA) + { + emit_insn (gen_cmpdf_fpa (operands[0], operands[1])); + DONE; + } +}") + +(define_insn "cmpdf_fpa" + [(set (cc0) + (compare (match_operand:DF 0 "general_operand" "x,y") + (match_operand:DF 1 "general_operand" "xH,rmF"))) + (clobber (match_scratch:SI 2 "=d,d"))] + "TARGET_FPA" + "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc") + +(define_insn "" + [(set (cc0) + (compare (match_operand:DF 0 "general_operand" "f,mG") + (match_operand:DF 1 "general_operand" "fmG,f")))] + "TARGET_68881" + "* +{ + cc_status.flags = CC_IN_68881; +#ifdef SGS_CMP_ORDER + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return \"fcmp%.x %0,%1\"; + else + return \"fcmp%.d %0,%f1\"; + } + cc_status.flags |= CC_REVERSED; + return \"fcmp%.d %1,%f0\"; +#else + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return \"fcmp%.x %1,%0\"; + else + return \"fcmp%.d %f1,%0\"; + } + cc_status.flags |= CC_REVERSED; + return \"fcmp%.d %f0,%1\"; +#endif +}") + +(define_expand "cmpsf" + [(set (cc0) + (compare (match_operand:SF 0 "general_operand" "") + (match_operand:SF 1 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + " +{ + if (TARGET_FPA) + { + emit_insn (gen_cmpsf_fpa (operands[0], operands[1])); + DONE; + } +}") + +(define_insn "cmpsf_fpa" + [(set (cc0) + (compare (match_operand:SF 0 "general_operand" "x,y") + (match_operand:SF 1 "general_operand" "xH,rmF"))) + (clobber (match_scratch:SI 2 "=d,d"))] + "TARGET_FPA" + "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc") + +(define_insn "" + [(set (cc0) + (compare (match_operand:SF 0 "general_operand" "f,mdG") + (match_operand:SF 1 "general_operand" "fmdG,f")))] + "TARGET_68881" + "* +{ + cc_status.flags = CC_IN_68881; +#ifdef SGS_CMP_ORDER + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return \"fcmp%.x %0,%1\"; + else + return \"fcmp%.s %0,%f1\"; + } + cc_status.flags |= CC_REVERSED; + return \"fcmp%.s %1,%f0\"; +#else + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return \"fcmp%.x %1,%0\"; + else + return \"fcmp%.s %f1,%0\"; + } + cc_status.flags |= CC_REVERSED; + return \"fcmp%.s %f0,%1\"; +#endif +}") + +;; Recognizers for btst instructions. + +(define_insn "" + [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do") + (const_int 1) + (minus:SI (const_int 7) + (match_operand:SI 1 "general_operand" "di"))))] + "" + "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") + +(define_insn "" + [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d") + (const_int 1) + (minus:SI (const_int 31) + (match_operand:SI 1 "general_operand" "di"))))] + "" + "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") + +;; The following two patterns are like the previous two +;; except that they use the fact that bit-number operands +;; are automatically masked to 3 or 5 bits. + +(define_insn "" + [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do") + (const_int 1) + (minus:SI (const_int 7) + (and:SI + (match_operand:SI 1 "general_operand" "d") + (const_int 7)))))] + "" + "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") + +(define_insn "" + [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d") + (const_int 1) + (minus:SI (const_int 31) + (and:SI + (match_operand:SI 1 "general_operand" "d") + (const_int 31)))))] + "" + "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") + +;; Nonoffsettable mem refs are ok in this one pattern +;; since we don't try to adjust them. +(define_insn "" + [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md") + (const_int 1) + (match_operand:SI 1 "general_operand" "i")))] + "GET_CODE (operands[1]) == CONST_INT + && (unsigned) INTVAL (operands[1]) < 8" + "* +{ + operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1])); + return output_btst (operands, operands[1], operands[0], insn, 7); +}") + +(define_insn "" + [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do") + (const_int 1) + (match_operand:SI 1 "general_operand" "i")))] + "GET_CODE (operands[1]) == CONST_INT" + "* +{ + if (GET_CODE (operands[0]) == MEM) + { + operands[0] = adj_offsettable_operand (operands[0], + INTVAL (operands[1]) / 8); + operands[1] = gen_rtx (CONST_INT, VOIDmode, + 7 - INTVAL (operands[1]) % 8); + return output_btst (operands, operands[1], operands[0], insn, 7); + } + operands[1] = gen_rtx (CONST_INT, VOIDmode, + 31 - INTVAL (operands[1])); + return output_btst (operands, operands[1], operands[0], insn, 31); +}") + + +;; move instructions + +;; A special case in which it is not desirable +;; to reload the constant into a data register. +(define_insn "" + [(set (match_operand:SI 0 "push_operand" "=m") + (match_operand:SI 1 "general_operand" "J"))] + "GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >= -0x8000 + && INTVAL (operands[1]) < 0x8000" + "* +{ + if (operands[1] == const0_rtx) + return \"clr%.l %0\"; + return \"pea %a1\"; +}") + +;This is never used. +;(define_insn "swapsi" +; [(set (match_operand:SI 0 "general_operand" "+r") +; (match_operand:SI 1 "general_operand" "+r")) +; (set (match_dup 1) (match_dup 0))] +; "" +; "exg %1,%0") + +;; Special case of fullword move when source is zero. +;; The reason this is special is to avoid loading a zero +;; into a data reg with moveq in order to store it elsewhere. + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g") + (const_int 0))] + ;; clr insns on 68000 read before writing. + ;; This isn't so on the 68010, but we have no alternative for it. + "(TARGET_68020 + || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))" + "* +{ + if (ADDRESS_REG_P (operands[0])) + return \"sub%.l %0,%0\"; + /* moveq is faster on the 68000. */ + if (DATA_REG_P (operands[0]) && !TARGET_68020) +#if defined(MOTOROLA) && !defined(CRDS) + return \"moveq%.l %#0,%0\"; +#else + return \"moveq %#0,%0\"; +#endif + return \"clr%.l %0\"; +}") + +;; General case of fullword move. +;; +;; This is the main "hook" for PIC code. When generating +;; PIC, movsi is responsible for determining when the source address +;; needs PIC relocation and appropriately calling legitimize_pic_address +;; to perform the actual relocation. +;; +;; In both the PIC and non-PIC cases the patterns generated will +;; matched by the next define_insn. +(define_expand "movsi" + [(set (match_operand:SI 0 "general_operand" "") + (match_operand:SI 1 "general_operand" ""))] + "" + " +{ + if (flag_pic && symbolic_operand (operands[1], SImode)) + { + /* The source is an address which requires PIC relocation. + Call legitimize_pic_address with the source, mode, and a relocation + register (a new pseudo, or the final destination if reload_in_progress + is set). Then fall through normally */ + extern rtx legitimize_pic_address(); + rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); + operands[1] = legitimize_pic_address (operands[1], SImode, temp); + } +}") + +;; General case of fullword move. The register constraints +;; force integer constants in range for a moveq to be reloaded +;; if they are headed for memory. +(define_insn "" + ;; Notes: make sure no alternative allows g vs g. + ;; We don't allow f-regs since fixed point cannot go in them. + ;; We do allow y and x regs since fixed point is allowed in them. + [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m") + (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))] + "" + "* +{ + if (which_alternative == 3) + return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\"; + if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0])) + return \"fpmove%.l %x1,%x0\"; + if (GET_CODE (operands[1]) == CONST_INT) + { + if (operands[1] == const0_rtx + && (DATA_REG_P (operands[0]) + || GET_CODE (operands[0]) == MEM) + /* clr insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + && (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM + && MEM_VOLATILE_P (operands[0])))) + return \"clr%.l %0\"; + else if (DATA_REG_P (operands[0]) + && INTVAL (operands[1]) < 128 + && INTVAL (operands[1]) >= -128) + { +#if defined(MOTOROLA) && !defined(CRDS) + return \"moveq%.l %1,%0\"; +#else + return \"moveq %1,%0\"; +#endif + } +#ifndef NO_ADDSUB_Q + else if (DATA_REG_P (operands[0]) + /* Do this with a moveq #N-8, dreg; addq #8,dreg */ + && INTVAL (operands[1]) < 136 + && INTVAL (operands[1]) >= 128) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); +#if defined(MOTOROLA) && !defined(CRDS) + return \"moveq%.l %1,%0\;addq%.w %#8,%0\"; +#else + return \"moveq %1,%0\;addq%.w %#8,%0\"; +#endif + } + else if (DATA_REG_P (operands[0]) + /* Do this with a moveq #N+8, dreg; subq #8,dreg */ + && INTVAL (operands[1]) < -128 + && INTVAL (operands[1]) >= -136) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 8); +#if defined(MOTOROLA) && !defined(CRDS) + return \"moveq%.l %1,%0;subq%.w %#8,%0\"; +#else + return \"moveq %1,%0;subq%.w %#8,%0\"; +#endif + } +#endif + else if (DATA_REG_P (operands[0]) + /* If N is in the right range and is even, then use + moveq #N/2, dreg; addl dreg,dreg */ + && INTVAL (operands[1]) > 127 + && INTVAL (operands[1]) <= 254 + && INTVAL (operands[1]) % 2 == 0) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) / 2); +#if defined(MOTOROLA) && !defined(CRDS) + return \"moveq%.l %1,%0\;add%.w %0,%0\"; +#else + return \"moveq %1,%0\;add%.w %0,%0\"; +#endif + } + else if (ADDRESS_REG_P (operands[0]) + && INTVAL (operands[1]) < 0x8000 + && INTVAL (operands[1]) >= -0x8000) + return \"move%.w %1,%0\"; + else if (push_operand (operands[0], SImode) + && INTVAL (operands[1]) < 0x8000 + && INTVAL (operands[1]) >= -0x8000) + return \"pea %a1\"; + } + else if ((GET_CODE (operands[1]) == SYMBOL_REF + || GET_CODE (operands[1]) == CONST) + && push_operand (operands[0], SImode)) + return \"pea %a1\"; + else if ((GET_CODE (operands[1]) == SYMBOL_REF + || GET_CODE (operands[1]) == CONST) + && ADDRESS_REG_P (operands[0])) + return \"lea %a1,%0\"; + return \"move%.l %1,%0\"; +}") + +(define_insn "movhi" + [(set (match_operand:HI 0 "general_operand" "=g") + (match_operand:HI 1 "general_operand" "g"))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + if (operands[1] == const0_rtx + && (DATA_REG_P (operands[0]) + || GET_CODE (operands[0]) == MEM) + /* clr insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + && (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM + && MEM_VOLATILE_P (operands[0])))) + return \"clr%.w %0\"; + else if (DATA_REG_P (operands[0]) + && INTVAL (operands[1]) < 128 + && INTVAL (operands[1]) >= -128) + { +#if defined(MOTOROLA) && !defined(CRDS) + return \"moveq%.l %1,%0\"; +#else + return \"moveq %1,%0\"; +#endif + } + else if (INTVAL (operands[1]) < 0x8000 + && INTVAL (operands[1]) >= -0x8000) + return \"move%.w %1,%0\"; + } + else if (CONSTANT_P (operands[1])) + return \"move%.l %1,%0\"; +#ifndef SGS_NO_LI + /* Recognize the insn before a tablejump, one that refers + to a table of offsets. Such an insn will need to refer + to a label on the insn. So output one. Use the label-number + of the table of offsets to generate this label. */ + if (GET_CODE (operands[1]) == MEM + && GET_CODE (XEXP (operands[1], 0)) == PLUS + && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF + || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF) + && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS + && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS) + { + rtx labelref; + if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF) + labelref = XEXP (XEXP (operands[1], 0), 0); + else + labelref = XEXP (XEXP (operands[1], 0), 1); +#if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES) +#ifdef SGS + asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\", + CODE_LABEL_NUMBER (XEXP (labelref, 0))); +#else /* not SGS */ + asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\", + CODE_LABEL_NUMBER (XEXP (labelref, 0))); +#endif /* not SGS */ +#else /* SGS_SWITCH_TABLES or not MOTOROLA */ + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", + CODE_LABEL_NUMBER (XEXP (labelref, 0))); +#ifdef SGS_SWITCH_TABLES + /* Set flag saying we need to define the symbol + LD%n (with value L%n-LI%n) at the end of the switch table. */ + switch_table_difference_label_flag = 1; +#endif /* SGS_SWITCH_TABLES */ +#endif /* SGS_SWITCH_TABLES or not MOTOROLA */ + } +#endif /* SGS_NO_LI */ + return \"move%.w %1,%0\"; +}") + +(define_insn "movstricthi" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) + (match_operand:HI 1 "general_operand" "rmn"))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + if (operands[1] == const0_rtx + && (DATA_REG_P (operands[0]) + || GET_CODE (operands[0]) == MEM) + /* clr insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + && (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM + && MEM_VOLATILE_P (operands[0])))) + return \"clr%.w %0\"; + } + return \"move%.w %1,%0\"; +}") + +(define_insn "movqi" + [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a") + (match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))] + "" + "* +{ + rtx xoperands[4]; + + /* This is probably useless, since it loses for pushing a struct + of several bytes a byte at a time. */ + if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC + && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx) + { + xoperands[1] = operands[1]; + xoperands[2] + = gen_rtx (MEM, QImode, + gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx)); + /* Just pushing a byte puts it in the high byte of the halfword. */ + /* We must put it in the low-order, high-numbered byte. */ + output_asm_insn (\"move%.b %1,%-\;move%.b %@,%2\", xoperands); + return \"\"; + } + + /* Moving a byte into an address register is not possible. */ + /* Use d0 as an intermediate, but don't clobber its contents. */ + if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM) + { + /* ??? For 2.5, don't allow this choice and use secondary reloads + instead. + + See if the address register is used in the address. If it + is, we have to generate a more complex sequence than those below. */ + if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, + operands[1], NULL_RTX)) + { + /* See if the stack pointer is used in the address. If it isn't, + we can push d0 or d1 (the insn can't use both of them) on + the stack, perform our move into d0/d1, copy the byte from d0/1, + and pop d0/1. */ + if (! reg_mentioned_p (stack_pointer_rtx, operands[1])) + { + if (refers_to_regno_p (0, 1, operands[1], NULL_RTX)) + return \"move%.l %/d0,%-\;move%.b %1,%/d0\;move%.l %/d0,%0\;move%.l %+,%/d0\"; + else + return \"move%.l %/d1,%-\;move%.b %1,%/d1\;move%.l %/d1,%0\;move%.l %+,%/d1\"; + } + else + { + /* Otherwise, we know that d0 cannot be used in the address + (since sp and one address register is). Assume that sp is + being used as a base register and replace the address + register that is our operand[0] with d0. */ + rtx reg_map[FIRST_PSEUDO_REGISTER]; + int i; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + reg_map[i] = 0; + + reg_map[REGNO (operands[0])] = gen_rtx (REG, Pmode, 0); + operands[1] = copy_rtx (operands[1]); + replace_regs (operands[1], reg_map, FIRST_PSEUDO_REGISTER, 0); + return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\"; + } + } + + /* If the address of operand 1 uses d0, choose d1 as intermediate. */ + if (refers_to_regno_p (0, 1, operands[1], NULL_RTX)) + return \"exg %/d1,%0\;move%.b %1,%/d1\;exg %/d1,%0\"; + /* Otherwise d0 is usable. + (An effective address on the 68k can't use two d-regs.) */ + else + return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\"; + } + + /* Likewise for moving from an address reg. */ + if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM) + { + /* ??? For 2.5, don't allow this choice and use secondary reloads + instead. + + See if the address register is used in the address. If it + is, we have to generate a more complex sequence than those below. */ + if (refers_to_regno_p (REGNO (operands[1]), REGNO (operands[1]) + 1, + operands[0], NULL_RTX)) + { + /* See if the stack pointer is used in the address. If it isn't, + we can push d0 or d1 (the insn can't use both of them) on + the stack, copy the byte to d0/1, perform our move from d0/d1, + and pop d0/1. */ + if (! reg_mentioned_p (stack_pointer_rtx, operands[0])) + { + if (refers_to_regno_p (0, 1, operands[0], NULL_RTX)) + return \"move%.l %/d0,%-\;move%.l %1,%/d0\;move%.b %/d0,%0\;move%.l %+,%/d0\"; + else + return \"move%.l %/d1,%-\;move%.l %1,%/d1\;move%.b %/d1,%0\;move%.l %+,%/d1\"; + } + else + { + /* Otherwise, we know that d0 cannot be used in the address + (since sp and one address register is). Assume that sp is + being used as a base register and replace the address + register that is our operand[1] with d0. */ + rtx reg_map[FIRST_PSEUDO_REGISTER]; + int i; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + reg_map[i] = 0; + + reg_map[REGNO (operands[1])] = gen_rtx (REG, Pmode, 0); + operands[0] = copy_rtx (operands[0]); + replace_regs (operands[0], reg_map, FIRST_PSEUDO_REGISTER, 0); + return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\"; + } + } + + if (refers_to_regno_p (0, 1, operands[0], NULL_RTX)) + return \"exg %/d1,%1\;move%.b %/d1,%0\;exg %/d1,%1\"; + else + return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\"; + } + + /* clr and st insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + if (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if (operands[1] == const0_rtx) + return \"clr%.b %0\"; + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) == -1) + { + CC_STATUS_INIT; + return \"st %0\"; + } + } + if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) + return \"move%.l %1,%0\"; + if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) + return \"move%.w %1,%0\"; + return \"move%.b %1,%0\"; +}") + +(define_insn "movstrictqi" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) + (match_operand:QI 1 "general_operand" "dmn"))] + "" + "* +{ + if (operands[1] == const0_rtx + /* clr insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + && (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) + return \"clr%.b %0\"; + return \"move%.b %1,%0\"; +}") + +(define_insn "movsf" + [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm") + (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))] +; [(set (match_operand:SF 0 "general_operand" "=rmf") +; (match_operand:SF 1 "general_operand" "rmfF"))] + "" + "* +{ + if (which_alternative >= 4) + return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\"; + if (FPA_REG_P (operands[0])) + { + if (FPA_REG_P (operands[1])) + return \"fpmove%.s %x1,%x0\"; + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_single (operands); + else if (FP_REG_P (operands[1])) + return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\"; + return \"fpmove%.s %x1,%x0\"; + } + if (FPA_REG_P (operands[1])) + { + if (FP_REG_P (operands[0])) + return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\"; + else + return \"fpmove%.s %x1,%x0\"; + } + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return \"f%$move%.x %1,%0\"; + else if (ADDRESS_REG_P (operands[1])) + return \"move%.l %1,%-\;f%$move%.s %+,%0\"; + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_single (operands); + return \"f%$move%.s %f1,%0\"; + } + if (FP_REG_P (operands[1])) + { + if (ADDRESS_REG_P (operands[0])) + return \"fmove%.s %1,%-\;move%.l %+,%0\"; + return \"fmove%.s %f1,%0\"; + } + return \"move%.l %1,%0\"; +}") + +(define_insn "movdf" + [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>,y,rm,x,!x,!rm") + (match_operand:DF 1 "general_operand" "rf,m,rofE<>,rmE,y,xH,rm,x"))] +; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>") +; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))] + "" + "* +{ + if (which_alternative == 6) + return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\"; + if (FPA_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_double (operands); + if (FP_REG_P (operands[1])) + return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\"; + return \"fpmove%.d %x1,%x0\"; + } + else if (FPA_REG_P (operands[1])) + { + if (FP_REG_P(operands[0])) + return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\"; + else + return \"fpmove%.d %x1,%x0\"; + } + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return \"f%&move%.x %1,%0\"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"move%.l %1,%-\", xoperands); + output_asm_insn (\"move%.l %1,%-\", operands); + return \"f%&move%.d %+,%0\"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_double (operands); + return \"f%&move%.d %f1,%0\"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + { + output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return \"move%.l %+,%0\"; + } + else + return \"fmove%.d %f1,%0\"; + } + return output_move_double (operands); +} +") + +(define_expand "movxf" + [(set (match_operand:XF 0 "nonimmediate_operand" "") + (match_operand:XF 1 "general_operand" ""))] + "" + " +{ + if (CONSTANT_P (operands[1])) + { + operands[1] = force_const_mem (XFmode, operands[1]); + if (! memory_address_p (XFmode, XEXP (operands[1], 0)) + && ! reload_in_progress) + operands[1] = change_address (operands[1], XFmode, + XEXP (operands[1], 0)); + } +}") + +(define_insn "" + [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f") + (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))] + "TARGET_68881" + "* +{ + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return \"fmove%.x %1,%0\"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); + output_asm_insn (\"move%.l %1,%-\", xoperands); + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"move%.l %1,%-\", xoperands); + output_asm_insn (\"move%.l %1,%-\", operands); + return \"fmove%.x %+,%0\"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return \"fmove%.x %1,%0\"; + return \"fmove%.x %f1,%0\"; + } + if (REG_P (operands[0])) + { + output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + output_asm_insn (\"move%.l %+,%0\", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return \"move%.l %+,%0\"; + } + return \"fmove%.x %f1,%0\"; +} +") + +(define_insn "" + [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,&rf,&rof<>") + (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))] + "! TARGET_68881" + "* +{ + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return \"fmove%.x %1,%0\"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); + output_asm_insn (\"move%.l %1,%-\", xoperands); + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"move%.l %1,%-\", xoperands); + output_asm_insn (\"move%.l %1,%-\", operands); + return \"fmove%.x %+,%0\"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return \"fmove%.x %1,%0\"; + return \"fmove%.x %f1,%0\"; + } + if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + { + output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + output_asm_insn (\"move%.l %+,%0\", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return \"move%.l %+,%0\"; + } + else + return \"fmove%.x %f1,%0\"; + } + return output_move_double (operands); +} +") + +;; movdi can apply to fp regs in some cases +(define_insn "movdi" + ;; Let's see if it really still needs to handle fp regs, and, if so, why. + [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,y,rm,!*x,!rm") + (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))] +; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm") +; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))] +; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f") +; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))] + "" + "* +{ + if (which_alternative == 8) + return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\"; + if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1])) + return \"fpmove%.d %x1,%x0\"; + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) + return \"fmove%.x %1,%0\"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"move%.l %1,%-\", xoperands); + output_asm_insn (\"move%.l %1,%-\", operands); + return \"fmove%.d %+,%0\"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_double (operands); + return \"fmove%.d %f1,%0\"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + { + output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return \"move%.l %+,%0\"; + } + else + return \"fmove%.d %f1,%0\"; + } + return output_move_double (operands); +} +") + +;; Thus goes after the move instructions +;; because the move instructions are better (require no spilling) +;; when they can apply. It goes before the add/sub insns +;; so we will prefer it to them. + +(define_insn "pushasi" + [(set (match_operand:SI 0 "push_operand" "=m") + (match_operand:SI 1 "address_operand" "p"))] + "" + "pea %a1") + +;; truncation instructions +(define_insn "truncsiqi2" + [(set (match_operand:QI 0 "general_operand" "=dm,d") + (truncate:QI + (match_operand:SI 1 "general_operand" "doJ,i")))] + "" + "* +{ + if (GET_CODE (operands[0]) == REG) + { + /* Must clear condition codes, since the move.l bases them on + the entire 32 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return \"move%.l %1,%0\"; + } + if (GET_CODE (operands[1]) == MEM) + operands[1] = adj_offsettable_operand (operands[1], 3); + return \"move%.b %1,%0\"; +}") + +(define_insn "trunchiqi2" + [(set (match_operand:QI 0 "general_operand" "=dm,d") + (truncate:QI + (match_operand:HI 1 "general_operand" "doJ,i")))] + "" + "* +{ + if (GET_CODE (operands[0]) == REG + && (GET_CODE (operands[1]) == MEM + || GET_CODE (operands[1]) == CONST_INT)) + { + /* Must clear condition codes, since the move.w bases them on + the entire 16 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return \"move%.w %1,%0\"; + } + if (GET_CODE (operands[0]) == REG) + { + /* Must clear condition codes, since the move.l bases them on + the entire 32 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return \"move%.l %1,%0\"; + } + if (GET_CODE (operands[1]) == MEM) + operands[1] = adj_offsettable_operand (operands[1], 1); + return \"move%.b %1,%0\"; +}") + +(define_insn "truncsihi2" + [(set (match_operand:HI 0 "general_operand" "=dm,d") + (truncate:HI + (match_operand:SI 1 "general_operand" "roJ,i")))] + "" + "* +{ + if (GET_CODE (operands[0]) == REG) + { + /* Must clear condition codes, since the move.l bases them on + the entire 32 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return \"move%.l %1,%0\"; + } + if (GET_CODE (operands[1]) == MEM) + operands[1] = adj_offsettable_operand (operands[1], 2); + return \"move%.w %1,%0\"; +}") + +;; zero extension instructions + +(define_expand "zero_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "") + (const_int 0)) + (set (strict_low_part (match_dup 2)) + (match_operand:HI 1 "general_operand" ""))] + "" + " +{ + operands[1] = make_safe_from (operands[1], operands[0]); + if (GET_CODE (operands[0]) == SUBREG) + operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]), + SUBREG_WORD (operands[0])); + else + operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0); +}") + +(define_expand "zero_extendqihi2" + [(set (match_operand:HI 0 "register_operand" "") + (const_int 0)) + (set (strict_low_part (match_dup 2)) + (match_operand:QI 1 "general_operand" ""))] + "" + " +{ + operands[1] = make_safe_from (operands[1], operands[0]); + if (GET_CODE (operands[0]) == SUBREG) + operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]), + SUBREG_WORD (operands[0])); + else + operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0); +}") + +(define_expand "zero_extendqisi2" + [(set (match_operand:SI 0 "register_operand" "") + (const_int 0)) + (set (strict_low_part (match_dup 2)) + (match_operand:QI 1 "general_operand" ""))] + "" + " +{ + operands[1] = make_safe_from (operands[1], operands[0]); + if (GET_CODE (operands[0]) == SUBREG) + operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]), + SUBREG_WORD (operands[0])); + else + operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0); +}") + +;; Patterns to recognize zero-extend insns produced by the combiner. +;; We don't allow both operands in memory, because of aliasing problems. +;; Explicitly disallow two memory operands via the condition since reloading +;; of this case will result in worse code than the uncombined patterns. + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=do<>,d<") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" + "* +{ + if (DATA_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG + && REGNO (operands[0]) == REGNO (operands[1])) + return \"and%.l %#0xFFFF,%0\"; + if (reg_mentioned_p (operands[0], operands[1])) + return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\"; + return \"clr%.l %0\;move%.w %1,%0\"; + } + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + return \"move%.w %1,%0\;clr%.w %0\"; + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == POST_INC) + return \"clr%.w %0\;move%.w %1,%0\"; + else + { + output_asm_insn (\"clr%.w %0\", operands); + operands[0] = adj_offsettable_operand (operands[0], 2); + return \"move%.w %1,%0\"; + } +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=do<>,d") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] + "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" + "* +{ + if (DATA_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG + && REGNO (operands[0]) == REGNO (operands[1])) + return \"and%.w %#0xFF,%0\"; + if (reg_mentioned_p (operands[0], operands[1])) + return \"move%.b %1,%0\;and%.w %#0xFF,%0\"; + return \"clr%.w %0\;move%.b %1,%0\"; + } + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + { + if (REGNO (XEXP (XEXP (operands[0], 0), 0)) + == STACK_POINTER_REGNUM) + { + output_asm_insn (\"clr%.w %-\", operands); + operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), + plus_constant (stack_pointer_rtx, 1)); + return \"move%.b %1,%0\"; + } + else + return \"move%.b %1,%0\;clr%.b %0\"; + } + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == POST_INC) + return \"clr%.b %0\;move%.b %1,%0\"; + else + { + output_asm_insn (\"clr%.b %0\", operands); + operands[0] = adj_offsettable_operand (operands[0], 1); + return \"move%.b %1,%0\"; + } +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=do<>,d") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] + "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" + "* +{ + if (DATA_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG + && REGNO (operands[0]) == REGNO (operands[1])) + return \"and%.l %#0xFF,%0\"; + if (reg_mentioned_p (operands[0], operands[1])) + return \"move%.b %1,%0\;and%.l %#0xFF,%0\"; + return \"clr%.l %0\;move%.b %1,%0\"; + } + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + { + operands[0] = XEXP (XEXP (operands[0], 0), 0); +#ifdef MOTOROLA +#ifdef SGS + return \"clr%.l -(%0)\;move%.b %1,3(%0)\"; +#else + return \"clr%.l -(%0)\;move%.b %1,(3,%0)\"; +#endif +#else + return \"clrl %0@-\;moveb %1,%0@(3)\"; +#endif + } + else if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == POST_INC) + { + operands[0] = XEXP (XEXP (operands[0], 0), 0); +#ifdef MOTOROLA +#ifdef SGS + return \"clr%.l (%0)+\;move%.b %1,-1(%0)\"; +#else + return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\"; +#endif +#else + return \"clrl %0@+\;moveb %1,%0@(-1)\"; +#endif + } + else + { + output_asm_insn (\"clr%.l %0\", operands); + operands[0] = adj_offsettable_operand (operands[0], 3); + return \"move%.b %1,%0\"; + } +}") + +;; sign extension instructions + +(define_insn "extendhisi2" + [(set (match_operand:SI 0 "general_operand" "=*d,a") + (sign_extend:SI + (match_operand:HI 1 "nonimmediate_operand" "0,rm")))] + "" + "* +{ + if (ADDRESS_REG_P (operands[0])) + return \"move%.w %1,%0\"; + return \"ext%.l %0\"; +}") + +(define_insn "extendqihi2" + [(set (match_operand:HI 0 "general_operand" "=d") + (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))] + "" + "ext%.w %0") + +(define_insn "extendqisi2" + [(set (match_operand:SI 0 "general_operand" "=d") + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] + "TARGET_68020" + "extb%.l %0") + +;; Conversions between float and double. + +(define_expand "extendsfdf2" + [(set (match_operand:DF 0 "general_operand" "") + (float_extend:DF + (match_operand:SF 1 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=x,y") + (float_extend:DF + (match_operand:SF 1 "general_operand" "xH,rmF")))] + "TARGET_FPA" + "fpstod %w1,%0") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=*fdm,f") + (float_extend:DF + (match_operand:SF 1 "general_operand" "f,dmF")))] + "TARGET_68881" + "* +{ + if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) + { + if (REGNO (operands[0]) == REGNO (operands[1])) + { + /* Extending float to double in an fp-reg is a no-op. + NOTICE_UPDATE_CC has already assumed that the + cc will be set. So cancel what it did. */ + cc_status = cc_prev_status; + return \"\"; + } + return \"f%&move%.x %1,%0\"; + } + if (FP_REG_P (operands[0])) + return \"f%&move%.s %f1,%0\"; + if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1])) + { + output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return \"move%.l %+,%0\"; + } + return \"fmove%.d %f1,%0\"; +}") + +;; This cannot output into an f-reg because there is no way to be +;; sure of truncating in that case. +;; But on the Sun FPA, we can be sure. +(define_expand "truncdfsf2" + [(set (match_operand:SF 0 "general_operand" "") + (float_truncate:SF + (match_operand:DF 1 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=x,y") + (float_truncate:SF + (match_operand:DF 1 "general_operand" "xH,rmF")))] + "TARGET_FPA" + "fpdtos %y1,%0") + +;; On the '040 we can truncate in a register accurately and easily. +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=f") + (float_truncate:SF + (match_operand:DF 1 "general_operand" "fmG")))] + "TARGET_68040_ONLY" + "* +{ + if (FP_REG_P (operands[1])) + return \"f%$move%.x %1,%0\"; + return \"f%$move%.d %f1,%0\"; +}") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=dm") + (float_truncate:SF + (match_operand:DF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.s %f1,%0") + +;; Conversion between fixed point and floating point. +;; Note that among the fix-to-float insns +;; the ones that start with SImode come first. +;; That is so that an operand that is a CONST_INT +;; (and therefore lacks a specific machine mode). +;; will be recognized as SImode (which is always valid) +;; rather than as QImode or HImode. + +(define_expand "floatsisf2" + [(set (match_operand:SF 0 "general_operand" "") + (float:SF (match_operand:SI 1 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=y,x") + (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))] + "TARGET_FPA" + "fpltos %1,%0") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=f") + (float:SF (match_operand:SI 1 "general_operand" "dmi")))] + "TARGET_68881" + "f%$move%.l %1,%0") + +(define_expand "floatsidf2" + [(set (match_operand:DF 0 "general_operand" "") + (float:DF (match_operand:SI 1 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=y,x") + (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))] + "TARGET_FPA" + "fpltod %1,%0") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=f") + (float:DF (match_operand:SI 1 "general_operand" "dmi")))] + "TARGET_68881" + "f%&move%.l %1,%0") + +(define_insn "floathisf2" + [(set (match_operand:SF 0 "general_operand" "=f") + (float:SF (match_operand:HI 1 "general_operand" "dmn")))] + "TARGET_68881" + "f%$move%.w %1,%0") + +(define_insn "floathidf2" + [(set (match_operand:DF 0 "general_operand" "=f") + (float:DF (match_operand:HI 1 "general_operand" "dmn")))] + "TARGET_68881" + "fmove%.w %1,%0") + +(define_insn "floatqisf2" + [(set (match_operand:SF 0 "general_operand" "=f") + (float:SF (match_operand:QI 1 "general_operand" "dmn")))] + "TARGET_68881" + "fmove%.b %1,%0") + +(define_insn "floatqidf2" + [(set (match_operand:DF 0 "general_operand" "=f") + (float:DF (match_operand:QI 1 "general_operand" "dmn")))] + "TARGET_68881" + "f%&move%.b %1,%0") + +;; New routines to convert floating-point values to integers +;; to be used on the '040. These should be faster than trapping +;; into the kernel to emulate fintrz. They should also be faster +;; than calling the subroutines fixsfsi or fixdfsi. + +(define_insn "fix_truncdfsi2" + [(set (match_operand:SI 0 "general_operand" "=dm") + (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) + (clobber (match_scratch:SI 2 "=d")) + (clobber (match_scratch:SI 3 "=d"))] + "TARGET_68040" + "* +{ + CC_STATUS_INIT; + return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\"; +}") + +(define_insn "fix_truncdfhi2" + [(set (match_operand:HI 0 "general_operand" "=dm") + (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f")))) + (clobber (match_scratch:SI 2 "=d")) + (clobber (match_scratch:SI 3 "=d"))] + "TARGET_68040" + "* +{ + CC_STATUS_INIT; + return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\"; +}") + +(define_insn "fix_truncdfqi2" + [(set (match_operand:QI 0 "general_operand" "=dm") + (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f")))) + (clobber (match_scratch:SI 2 "=d")) + (clobber (match_scratch:SI 3 "=d"))] + "TARGET_68040" + "* +{ + CC_STATUS_INIT; + return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\"; +}") + +;; Convert a float to a float whose value is an integer. +;; This is the first stage of converting it to an integer type. + +(define_insn "ftruncdf2" + [(set (match_operand:DF 0 "general_operand" "=f") + (fix:DF (match_operand:DF 1 "general_operand" "fFm")))] + "TARGET_68881 && !TARGET_68040" + "* +{ + if (FP_REG_P (operands[1])) + return \"fintrz%.x %f1,%0\"; + return \"fintrz%.d %f1,%0\"; +}") + +(define_insn "ftruncsf2" + [(set (match_operand:SF 0 "general_operand" "=f") + (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))] + "TARGET_68881 && !TARGET_68040" + "* +{ + if (FP_REG_P (operands[1])) + return \"fintrz%.x %f1,%0\"; + return \"fintrz%.s %f1,%0\"; +}") + +;; Convert a float whose value is an integer +;; to an actual integer. Second stage of converting float to integer type. +(define_insn "fixsfqi2" + [(set (match_operand:QI 0 "general_operand" "=dm") + (fix:QI (match_operand:SF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.b %1,%0") + +(define_insn "fixsfhi2" + [(set (match_operand:HI 0 "general_operand" "=dm") + (fix:HI (match_operand:SF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.w %1,%0") + +(define_insn "fixsfsi2" + [(set (match_operand:SI 0 "general_operand" "=dm") + (fix:SI (match_operand:SF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.l %1,%0") + +(define_insn "fixdfqi2" + [(set (match_operand:QI 0 "general_operand" "=dm") + (fix:QI (match_operand:DF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.b %1,%0") + +(define_insn "fixdfhi2" + [(set (match_operand:HI 0 "general_operand" "=dm") + (fix:HI (match_operand:DF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.w %1,%0") + +(define_insn "fixdfsi2" + [(set (match_operand:SI 0 "general_operand" "=dm") + (fix:SI (match_operand:DF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.l %1,%0") + +;; Convert a float to an integer. +;; On the Sun FPA, this is done in one step. + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=x,y") + (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))] + "TARGET_FPA" + "fpstol %w1,%0") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=x,y") + (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))] + "TARGET_FPA" + "fpdtol %y1,%0") + +;; add instructions + +;; Note that the middle two alternatives are near-duplicates +;; in order to handle insns generated by reload. +;; This is needed since they are not themselves reloaded, +;; so commutativity won't apply to them. +(define_insn "addsi3" + [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r") + (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0") + (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))] + "" + "* +{ + if (! operands_match_p (operands[0], operands[1])) + { + if (!ADDRESS_REG_P (operands[1])) + { + rtx tmp = operands[1]; + + operands[1] = operands[2]; + operands[2] = tmp; + } + + /* These insns can result from reloads to access + stack slots over 64k from the frame pointer. */ + if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000) + return \"move%.l %2,%0\;add%.l %1,%0\"; +#ifdef SGS + if (GET_CODE (operands[2]) == REG) + return \"lea 0(%1,%2.l),%0\"; + else + return \"lea %c2(%1),%0\"; +#else /* not SGS */ +#ifdef MOTOROLA + if (GET_CODE (operands[2]) == REG) + return \"lea (%1,%2.l),%0\"; + else + return \"lea (%c2,%1),%0\"; +#else /* not MOTOROLA (MIT syntax) */ + if (GET_CODE (operands[2]) == REG) + return \"lea %1@(0,%2:l),%0\"; + else + return \"lea %1@(%c2),%0\"; +#endif /* not MOTOROLA */ +#endif /* not SGS */ + } + if (GET_CODE (operands[2]) == CONST_INT) + { +#ifndef NO_ADDSUB_Q + if (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) <= 8) + return (ADDRESS_REG_P (operands[0]) + ? \"addq%.w %2,%0\" + : \"addq%.l %2,%0\"); + if (INTVAL (operands[2]) < 0 + && INTVAL (operands[2]) >= -8) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[2])); + return (ADDRESS_REG_P (operands[0]) + ? \"subq%.w %2,%0\" + : \"subq%.l %2,%0\"); + } + /* On everything except the 68000 it is faster to use two + addqw instructions to add a small integer (8 < N <= 16) + to an address register. Likewise for subqw.*/ + if (INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); + return \"addq%.w %#8,%0\;addq%.w %2,%0\"; + } + if (INTVAL (operands[2]) < -8 + && INTVAL (operands[2]) >= -16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[2]) - 8); + return \"subq%.w %#8,%0\;subq%.w %2,%0\"; + } +#endif + if (ADDRESS_REG_P (operands[0]) + && INTVAL (operands[2]) >= -0x8000 + && INTVAL (operands[2]) < 0x8000) + return \"add%.w %2,%0\"; + } + return \"add%.l %2,%0\"; +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=a") + (plus:SI (match_operand:SI 1 "general_operand" "0") + (sign_extend:SI + (match_operand:HI 2 "nonimmediate_operand" "rm"))))] + "" + "add%.w %2,%0") + +(define_insn "addhi3" + [(set (match_operand:HI 0 "general_operand" "=m,r") + (plus:HI (match_operand:HI 1 "general_operand" "%0,0") + (match_operand:HI 2 "general_operand" "dn,rmn")))] + "" + "* +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[2]) == CONST_INT) + { + /* If the constant would be a negative number when interpreted as + HImode, make it negative. This is usually, but not always, done + elsewhere in the compiler. First check for constants out of range, + which could confuse us. */ + + if (INTVAL (operands[2]) >= 32768) + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) - 65536); + + if (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) <= 8) + return \"addq%.w %2,%0\"; + if (INTVAL (operands[2]) < 0 + && INTVAL (operands[2]) >= -8) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[2])); + return \"subq%.w %2,%0\"; + } + /* On everything except the 68000 it is faster to use two + addqw instructions to add a small integer (8 < N <= 16) + to an address register. Likewise for subqw. */ + if (INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); + return \"addq%.w %#8,%0\;addq%.w %2,%0\"; + } + if (INTVAL (operands[2]) < -8 + && INTVAL (operands[2]) >= -16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[2]) - 8); + return \"subq%.w %#8,%0\;subq%.w %2,%0\"; + } + } +#endif + return \"add%.w %2,%0\"; +}") + +;; These insns must use MATCH_DUP instead of the more expected +;; use of a matching constraint because the "output" here is also +;; an input, so you can't use the matching constraint. That also means +;; that you can't use the "%", so you need patterns with the matched +;; operand in both positions. + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) + (plus:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dn,rmn")))] + "" + "* +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[1]) == CONST_INT) + { + /* If the constant would be a negative number when interpreted as + HImode, make it negative. This is usually, but not always, done + elsewhere in the compiler. First check for constants out of range, + which could confuse us. */ + + if (INTVAL (operands[1]) >= 32768) + operands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[1]) - 65536); + + if (INTVAL (operands[1]) > 0 + && INTVAL (operands[1]) <= 8) + return \"addq%.w %1,%0\"; + if (INTVAL (operands[1]) < 0 + && INTVAL (operands[1]) >= -8) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[1])); + return \"subq%.w %1,%0\"; + } + /* On everything except the 68000 it is faster to use two + addqw instructions to add a small integer (8 < N <= 16) + to an address register. Likewise for subqw. */ + if (INTVAL (operands[1]) > 8 + && INTVAL (operands[1]) <= 16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); + return \"addq%.w %#8,%0\;addq%.w %1,%0\"; + } + if (INTVAL (operands[1]) < -8 + && INTVAL (operands[1]) >= -16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[1]) - 8); + return \"subq%.w %#8,%0\;subq%.w %1,%0\"; + } + } +#endif + return \"add%.w %1,%0\"; +}") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) + (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn") + (match_dup 0)))] + "" + "* +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[1]) == CONST_INT) + { + /* If the constant would be a negative number when interpreted as + HImode, make it negative. This is usually, but not always, done + elsewhere in the compiler. First check for constants out of range, + which could confuse us. */ + + if (INTVAL (operands[1]) >= 32768) + operands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[1]) - 65536); + + if (INTVAL (operands[1]) > 0 + && INTVAL (operands[1]) <= 8) + return \"addq%.w %1,%0\"; + if (INTVAL (operands[1]) < 0 + && INTVAL (operands[1]) >= -8) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[1])); + return \"subq%.w %1,%0\"; + } + /* On everything except the 68000 it is faster to use two + addqw instructions to add a small integer (8 < N <= 16) + to an address register. Likewise for subqw. */ + if (INTVAL (operands[1]) > 8 + && INTVAL (operands[1]) <= 16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); + return \"addq%.w %#8,%0\;addq%.w %1,%0\"; + } + if (INTVAL (operands[1]) < -8 + && INTVAL (operands[1]) >= -16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[1]) - 8); + return \"subq%.w %#8,%0\;subq%.w %1,%0\"; + } + } +#endif + return \"add%.w %1,%0\"; +}") + +(define_insn "addqi3" + [(set (match_operand:QI 0 "general_operand" "=m,d") + (plus:QI (match_operand:QI 1 "general_operand" "%0,0") + (match_operand:QI 2 "general_operand" "dn,dmn")))] + "" + "* +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) >= 128) + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) - 256); + + if (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) <= 8) + return \"addq%.b %2,%0\"; + if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); + return \"subq%.b %2,%0\"; + } + } +#endif + return \"add%.b %2,%0\"; +}") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) + (plus:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dn,dmn")))] + "" + "* +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[1]) == CONST_INT) + { + if (INTVAL (operands[1]) >= 128) + operands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[1]) - 256); + + if (INTVAL (operands[1]) > 0 + && INTVAL (operands[1]) <= 8) + return \"addq%.b %1,%0\"; + if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); + return \"subq%.b %1,%0\"; + } + } +#endif + return \"add%.b %1,%0\"; +}") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) + (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn") + (match_dup 0)))] + "" + "* +{ +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[1]) == CONST_INT) + { + if (INTVAL (operands[1]) >= 128) + operands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[1]) - 256); + + if (INTVAL (operands[1]) > 0 + && INTVAL (operands[1]) <= 8) + return \"addq%.b %1,%0\"; + if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); + return \"subq%.b %1,%0\"; + } + } +#endif + return \"add%.b %1,%0\"; +}") + +(define_expand "adddf3" + [(set (match_operand:DF 0 "general_operand" "") + (plus:DF (match_operand:DF 1 "general_operand" "") + (match_operand:DF 2 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=x,y") + (plus:DF (match_operand:DF 1 "general_operand" "%xH,y") + (match_operand:DF 2 "general_operand" "xH,dmF")))] + "TARGET_FPA" + "* +{ + if (rtx_equal_p (operands[0], operands[1])) + return \"fpadd%.d %y2,%0\"; + if (rtx_equal_p (operands[0], operands[2])) + return \"fpadd%.d %y1,%0\"; + if (which_alternative == 0) + return \"fpadd3%.d %w2,%w1,%0\"; + return \"fpadd3%.d %x2,%x1,%0\"; +}") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=f") + (plus:DF (match_operand:DF 1 "general_operand" "%0") + (match_operand:DF 2 "general_operand" "fmG")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[2])) + return \"f%&add%.x %2,%0\"; + return \"f%&add%.d %f2,%0\"; +}") + +(define_expand "addsf3" + [(set (match_operand:SF 0 "general_operand" "") + (plus:SF (match_operand:SF 1 "general_operand" "") + (match_operand:SF 2 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=x,y") + (plus:SF (match_operand:SF 1 "general_operand" "%xH,y") + (match_operand:SF 2 "general_operand" "xH,rmF")))] + "TARGET_FPA" + "* +{ + if (rtx_equal_p (operands[0], operands[1])) + return \"fpadd%.s %w2,%0\"; + if (rtx_equal_p (operands[0], operands[2])) + return \"fpadd%.s %w1,%0\"; + if (which_alternative == 0) + return \"fpadd3%.s %w2,%w1,%0\"; + return \"fpadd3%.s %2,%1,%0\"; +}") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=f") + (plus:SF (match_operand:SF 1 "general_operand" "%0") + (match_operand:SF 2 "general_operand" "fdmF")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return \"f%$add%.x %2,%0\"; + return \"f%$add%.s %f2,%0\"; +}") + +;; subtract instructions + +(define_insn "subsi3" + [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d") + (minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs") + (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))] + "" + "* +{ + if (! operands_match_p (operands[0], operands[1])) + { + if (operands_match_p (operands[0], operands[2])) + { +#ifndef NO_ADDSUB_Q + if (GET_CODE (operands[1]) == CONST_INT) + { + if (INTVAL (operands[1]) > 0 + && INTVAL (operands[1]) <= 8) + return \"subq%.l %1,%0\;neg%.l %0\"; + } +#endif + return \"sub%.l %1,%0\;neg%.l %0\"; + } + /* This case is matched by J, but negating -0x8000 + in an lea would give an invalid displacement. + So do this specially. */ + if (INTVAL (operands[2]) == -0x8000) + return \"move%.l %1,%0\;sub%.l %2,%0\"; +#ifdef SGS + return \"lea %n2(%1),%0\"; +#else +#ifdef MOTOROLA + return \"lea (%n2,%1),%0\"; +#else /* not MOTOROLA (MIT syntax) */ + return \"lea %1@(%n2),%0\"; +#endif /* not MOTOROLA */ +#endif /* not SGS */ + } + if (GET_CODE (operands[2]) == CONST_INT) + { +#ifndef NO_ADDSUB_Q + if (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) <= 8) + return \"subq%.l %2,%0\"; + /* Using two subqw for 8 < N <= 16 being subtracted from an + address register is faster on all but 68000 */ + if (INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16 + && ADDRESS_REG_P (operands[0]) + && TARGET_68020) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); + return \"subq%.w %#8,%0\;subq%.w %2,%0\"; + } +#endif + if (ADDRESS_REG_P (operands[0]) + && INTVAL (operands[2]) >= -0x8000 + && INTVAL (operands[2]) < 0x8000) + return \"sub%.w %2,%0\"; + } + return \"sub%.l %2,%0\"; +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=a") + (minus:SI (match_operand:SI 1 "general_operand" "0") + (sign_extend:SI + (match_operand:HI 2 "nonimmediate_operand" "rm"))))] + "" + "sub%.w %2,%0") + +(define_insn "subhi3" + [(set (match_operand:HI 0 "general_operand" "=m,r") + (minus:HI (match_operand:HI 1 "general_operand" "0,0") + (match_operand:HI 2 "general_operand" "dn,rmn")))] + "" + "sub%.w %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) + (minus:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dn,rmn")))] + "" + "sub%.w %1,%0") + +(define_insn "subqi3" + [(set (match_operand:QI 0 "general_operand" "=m,d") + (minus:QI (match_operand:QI 1 "general_operand" "0,0") + (match_operand:QI 2 "general_operand" "dn,dmn")))] + "" + "sub%.b %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) + (minus:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dn,dmn")))] + "" + "sub%.b %1,%0") + +(define_expand "subdf3" + [(set (match_operand:DF 0 "general_operand" "") + (minus:DF (match_operand:DF 1 "general_operand" "") + (match_operand:DF 2 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=x,y,y") + (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF") + (match_operand:DF 2 "general_operand" "xH,dmF,0")))] + "TARGET_FPA" + "* +{ + if (rtx_equal_p (operands[0], operands[2])) + return \"fprsub%.d %y1,%0\"; + if (rtx_equal_p (operands[0], operands[1])) + return \"fpsub%.d %y2,%0\"; + if (which_alternative == 0) + return \"fpsub3%.d %w2,%w1,%0\"; + return \"fpsub3%.d %x2,%x1,%0\"; +}") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=f") + (minus:DF (match_operand:DF 1 "general_operand" "0") + (match_operand:DF 2 "general_operand" "fmG")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[2])) + return \"f%&sub%.x %2,%0\"; + return \"f%&sub%.d %f2,%0\"; +}") + +(define_expand "subsf3" + [(set (match_operand:SF 0 "general_operand" "") + (minus:SF (match_operand:SF 1 "general_operand" "") + (match_operand:SF 2 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=x,y,y") + (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF") + (match_operand:SF 2 "general_operand" "xH,rmF,0")))] + "TARGET_FPA" + "* +{ + if (rtx_equal_p (operands[0], operands[2])) + return \"fprsub%.s %w1,%0\"; + if (rtx_equal_p (operands[0], operands[1])) + return \"fpsub%.s %w2,%0\"; + if (which_alternative == 0) + return \"fpsub3%.s %w2,%w1,%0\"; + return \"fpsub3%.s %2,%1,%0\"; +}") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=f") + (minus:SF (match_operand:SF 1 "general_operand" "0") + (match_operand:SF 2 "general_operand" "fdmF")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return \"f%$sub%.x %2,%0\"; + return \"f%$sub%.s %f2,%0\"; +}") + +;; multiply instructions + +(define_insn "mulhi3" + [(set (match_operand:HI 0 "general_operand" "=d") + (mult:HI (match_operand:HI 1 "general_operand" "%0") + (match_operand:HI 2 "general_operand" "dmn")))] + "" + "* +{ +#if defined(MOTOROLA) && !defined(CRDS) + return \"muls%.w %2,%0\"; +#else + return \"muls %2,%0\"; +#endif +}") + +(define_insn "mulhisi3" + [(set (match_operand:SI 0 "general_operand" "=d") + (mult:SI (sign_extend:SI + (match_operand:HI 1 "nonimmediate_operand" "%0")) + (sign_extend:SI + (match_operand:HI 2 "nonimmediate_operand" "dm"))))] + "" + "* +{ +#if defined(MOTOROLA) && !defined(CRDS) + return \"muls%.w %2,%0\"; +#else + return \"muls %2,%0\"; +#endif +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=d") + (mult:SI (sign_extend:SI + (match_operand:HI 1 "nonimmediate_operand" "%0")) + (match_operand:SI 2 "const_int_operand" "n")))] + "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff" + "* +{ +#if defined(MOTOROLA) && !defined(CRDS) + return \"muls%.w %2,%0\"; +#else + return \"muls %2,%0\"; +#endif +}") + +(define_insn "mulsi3" + [(set (match_operand:SI 0 "general_operand" "=d") + (mult:SI (match_operand:SI 1 "general_operand" "%0") + (match_operand:SI 2 "general_operand" "dmsK")))] + "TARGET_68020" + "muls%.l %2,%0") + +(define_insn "umulhisi3" + [(set (match_operand:SI 0 "general_operand" "=d") + (mult:SI (zero_extend:SI + (match_operand:HI 1 "nonimmediate_operand" "%0")) + (zero_extend:SI + (match_operand:HI 2 "nonimmediate_operand" "dm"))))] + "" + "* +{ +#if defined(MOTOROLA) && !defined(CRDS) + return \"mulu%.w %2,%0\"; +#else + return \"mulu %2,%0\"; +#endif +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=d") + (mult:SI (zero_extend:SI + (match_operand:HI 1 "nonimmediate_operand" "%0")) + (match_operand:SI 2 "const_int_operand" "n")))] + "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff" + "* +{ +#if defined(MOTOROLA) && !defined(CRDS) + return \"mulu%.w %2,%0\"; +#else + return \"mulu %2,%0\"; +#endif +}") + +;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the +;; proper matching constraint. This is because the matching is between +;; the high-numbered word of the DImode operand[0] and operand[1]. +(define_expand "umulsidi3" + [(parallel + [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) + (mult:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "nonimmediate_operand" ""))) + (set (subreg:SI (match_dup 0) 0) + (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) + (zero_extend:DI (match_dup 2))) + (const_int 32))))])] + "TARGET_68020" + "") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (mult:SI (match_operand:SI 1 "register_operand" "%0") + (match_operand:SI 2 "nonimmediate_operand" "dm"))) + (set (match_operand:SI 3 "register_operand" "=d") + (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) + (zero_extend:DI (match_dup 2))) + (const_int 32))))] + "TARGET_68020" + "mulu%.l %2,%3:%0") + +; Match immediate case. For 2.4 only match things < 2^31. +; It's tricky with larger values in these patterns since we need to match +; values between the two parallel multiplies, between a CONST_DOUBLE and +; a CONST_INT. +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (mult:SI (match_operand:SI 1 "register_operand" "%0") + (match_operand:SI 2 "const_int_operand" "n"))) + (set (match_operand:SI 3 "register_operand" "=d") + (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) + (match_dup 2)) + (const_int 32))))] + "TARGET_68020 + && (unsigned) INTVAL (operands[2]) <= 0x7fffffff" + "mulu%.l %2,%3:%0") + +(define_expand "mulsidi3" + [(parallel + [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) + (mult:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "nonimmediate_operand" ""))) + (set (subreg:SI (match_dup 0) 0) + (truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_dup 1)) + (sign_extend:DI (match_dup 2))) + (const_int 32))))])] + "TARGET_68020" + "") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (mult:SI (match_operand:SI 1 "register_operand" "%0") + (match_operand:SI 2 "nonimmediate_operand" "dm"))) + (set (match_operand:SI 3 "register_operand" "=d") + (truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_dup 1)) + (sign_extend:DI (match_dup 2))) + (const_int 32))))] + "TARGET_68020" + "muls%.l %2,%3:%0") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (mult:SI (match_operand:SI 1 "register_operand" "%0") + (match_operand:SI 2 "const_int_operand" "n"))) + (set (match_operand:SI 3 "register_operand" "=d") + (truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_dup 1)) + (match_dup 2)) + (const_int 32))))] + "TARGET_68020 + /* This test is a noop on 32 bit machines, + but important for a cross-compiler hosted on 64-bit machines. */ + && INTVAL (operands[2]) <= 0x7fffffff + && INTVAL (operands[2]) >= -0x80000000" + "muls%.l %2,%3:%0") + +(define_expand "muldf3" + [(set (match_operand:DF 0 "general_operand" "") + (mult:DF (match_operand:DF 1 "general_operand" "") + (match_operand:DF 2 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=x,y") + (mult:DF (match_operand:DF 1 "general_operand" "%xH,y") + (match_operand:DF 2 "general_operand" "xH,rmF")))] + "TARGET_FPA" + "* +{ + if (rtx_equal_p (operands[1], operands[2])) + return \"fpsqr%.d %y1,%0\"; + if (rtx_equal_p (operands[0], operands[1])) + return \"fpmul%.d %y2,%0\"; + if (rtx_equal_p (operands[0], operands[2])) + return \"fpmul%.d %y1,%0\"; + if (which_alternative == 0) + return \"fpmul3%.d %w2,%w1,%0\"; + return \"fpmul3%.d %x2,%x1,%0\"; +}") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=f") + (mult:DF (match_operand:DF 1 "general_operand" "%0") + (match_operand:DF 2 "general_operand" "fmG")))] + "TARGET_68881" + "* +{ + if (GET_CODE (operands[2]) == CONST_DOUBLE + && floating_exact_log2 (operands[2]) && !TARGET_68040) + { + int i = floating_exact_log2 (operands[2]); + operands[2] = gen_rtx (CONST_INT, VOIDmode, i); + return \"fscale%.l %2,%0\"; + } + if (REG_P (operands[2])) + return \"f%&mul%.x %2,%0\"; + return \"f%&mul%.d %f2,%0\"; +}") + +(define_expand "mulsf3" + [(set (match_operand:SF 0 "general_operand" "") + (mult:SF (match_operand:SF 1 "general_operand" "") + (match_operand:SF 2 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=x,y") + (mult:SF (match_operand:SF 1 "general_operand" "%xH,y") + (match_operand:SF 2 "general_operand" "xH,rmF")))] + "TARGET_FPA" + "* +{ + if (rtx_equal_p (operands[1], operands[2])) + return \"fpsqr%.s %w1,%0\"; + if (rtx_equal_p (operands[0], operands[1])) + return \"fpmul%.s %w2,%0\"; + if (rtx_equal_p (operands[0], operands[2])) + return \"fpmul%.s %w1,%0\"; + if (which_alternative == 0) + return \"fpmul3%.s %w2,%w1,%0\"; + return \"fpmul3%.s %2,%1,%0\"; +}") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=f") + (mult:SF (match_operand:SF 1 "general_operand" "%0") + (match_operand:SF 2 "general_operand" "fdmF")))] + "TARGET_68881" + "* +{ +#ifdef FSGLMUL_USE_S + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return (TARGET_68040_ONLY + ? \"fsmul%.s %2,%0\" + : \"fsglmul%.s %2,%0\"); +#else + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return (TARGET_68040_ONLY + ? \"fsmul%.x %2,%0\" + : \"fsglmul%.x %2,%0\"); +#endif + return (TARGET_68040_ONLY + ? \"fsmul%.s %f2,%0\" + : \"fsglmul%.s %f2,%0\"); +}") + +;; divide instructions + +(define_insn "divhi3" + [(set (match_operand:HI 0 "general_operand" "=d") + (div:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "dmn")))] + "" + "* +{ +#ifdef MOTOROLA + return \"ext%.l %0\;divs%.w %2,%0\"; +#else + return \"extl %0\;divs %2,%0\"; +#endif +}") + +(define_insn "divhisi3" + [(set (match_operand:HI 0 "general_operand" "=d") + (truncate:HI + (div:SI + (match_operand:SI 1 "general_operand" "0") + (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] + "" + "* +{ +#ifdef MOTOROLA + return \"divs%.w %2,%0\"; +#else + return \"divs %2,%0\"; +#endif +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=d") + (truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "const_int_operand" "n"))))] + "" + "* +{ +#ifdef MOTOROLA + return \"divs%.w %2,%0\"; +#else + return \"divs %2,%0\"; +#endif +}") + +(define_insn "udivhi3" + [(set (match_operand:HI 0 "general_operand" "=d") + (udiv:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "dmn")))] + "" + "* +{ +#ifdef MOTOROLA + return \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\"; +#else + return \"andl %#0xFFFF,%0\;divu %2,%0\"; +#endif +}") + +(define_insn "udivhisi3" + [(set (match_operand:HI 0 "general_operand" "=d") + (truncate:HI + (udiv:SI + (match_operand:SI 1 "general_operand" "0") + (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] + "" + "* +{ +#ifdef MOTOROLA + return \"divu%.w %2,%0\"; +#else + return \"divu %2,%0\"; +#endif +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=d") + (truncate:HI (udiv:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "const_int_operand" "n"))))] + "" + "* +{ +#ifdef MOTOROLA + return \"divu%.w %2,%0\"; +#else + return \"divu %2,%0\"; +#endif +}") + +(define_expand "divdf3" + [(set (match_operand:DF 0 "general_operand" "") + (div:DF (match_operand:DF 1 "general_operand" "") + (match_operand:DF 2 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=x,y,y") + (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF") + (match_operand:DF 2 "general_operand" "xH,rmF,0")))] + "TARGET_FPA" + "* +{ + if (rtx_equal_p (operands[0], operands[2])) + return \"fprdiv%.d %y1,%0\"; + if (rtx_equal_p (operands[0], operands[1])) + return \"fpdiv%.d %y2,%0\"; + if (which_alternative == 0) + return \"fpdiv3%.d %w2,%w1,%0\"; + return \"fpdiv3%.d %x2,%x1,%x0\"; +}") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=f") + (div:DF (match_operand:DF 1 "general_operand" "0") + (match_operand:DF 2 "general_operand" "fmG")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[2])) + return \"f%&div%.x %2,%0\"; + return \"f%&div%.d %f2,%0\"; +}") + +(define_expand "divsf3" + [(set (match_operand:SF 0 "general_operand" "") + (div:SF (match_operand:SF 1 "general_operand" "") + (match_operand:SF 2 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=x,y,y") + (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF") + (match_operand:SF 2 "general_operand" "xH,rmF,0")))] + "TARGET_FPA" + "* +{ + if (rtx_equal_p (operands[0], operands[1])) + return \"fpdiv%.s %w2,%0\"; + if (rtx_equal_p (operands[0], operands[2])) + return \"fprdiv%.s %w1,%0\"; + if (which_alternative == 0) + return \"fpdiv3%.s %w2,%w1,%0\"; + return \"fpdiv3%.s %2,%1,%0\"; +}") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=f") + (div:SF (match_operand:SF 1 "general_operand" "0") + (match_operand:SF 2 "general_operand" "fdmF")))] + "TARGET_68881" + "* +{ +#ifdef FSGLDIV_USE_S + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return (TARGET_68040_ONLY + ? \"fsdiv%.s %2,%0\" + : \"fsgldiv%.s %2,%0\"); +#else + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return (TARGET_68040_ONLY + ? \"fsdiv%.x %2,%0\" + : \"fsgldiv%.x %2,%0\"); +#endif + return (TARGET_68040_ONLY + ? \"fsdiv%.s %f2,%0\" + : \"fsgldiv%.s %f2,%0\"); +}") + +;; Remainder instructions. + +(define_insn "modhi3" + [(set (match_operand:HI 0 "general_operand" "=d") + (mod:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "dmn")))] + "" + "* +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return \"ext%.l %0\;divs%.w %2,%0\;swap %0\"; +#else + return \"extl %0\;divs %2,%0\;swap %0\"; +#endif +}") + +(define_insn "modhisi3" + [(set (match_operand:HI 0 "general_operand" "=d") + (truncate:HI + (mod:SI + (match_operand:SI 1 "general_operand" "0") + (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] + "" + "* +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return \"divs%.w %2,%0\;swap %0\"; +#else + return \"divs %2,%0\;swap %0\"; +#endif +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=d") + (truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "const_int_operand" "n"))))] + "" + "* +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return \"divs%.w %2,%0\;swap %0\"; +#else + return \"divs %2,%0\;swap %0\"; +#endif +}") + +(define_insn "umodhi3" + [(set (match_operand:HI 0 "general_operand" "=d") + (umod:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "dmn")))] + "" + "* +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\;swap %0\"; +#else + return \"andl %#0xFFFF,%0\;divu %2,%0\;swap %0\"; +#endif +}") + +(define_insn "umodhisi3" + [(set (match_operand:HI 0 "general_operand" "=d") + (truncate:HI + (umod:SI + (match_operand:SI 1 "general_operand" "0") + (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] + "" + "* +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return \"divu%.w %2,%0\;swap %0\"; +#else + return \"divu %2,%0\;swap %0\"; +#endif +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=d") + (truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "const_int_operand" "n"))))] + "" + "* +{ + /* The swap insn produces cc's that don't correspond to the result. */ + CC_STATUS_INIT; +#ifdef MOTOROLA + return \"divu%.w %2,%0\;swap %0\"; +#else + return \"divu %2,%0\;swap %0\"; +#endif +}") + +(define_insn "divmodsi4" + [(set (match_operand:SI 0 "general_operand" "=d") + (div:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "dmsK"))) + (set (match_operand:SI 3 "general_operand" "=d") + (mod:SI (match_dup 1) (match_dup 2)))] + "TARGET_68020" + "* +{ + if (find_reg_note (insn, REG_UNUSED, operands[3])) + return \"divs%.l %2,%0\"; + else + return \"divsl%.l %2,%3:%0\"; +}") + +(define_insn "udivmodsi4" + [(set (match_operand:SI 0 "general_operand" "=d") + (udiv:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "dmsK"))) + (set (match_operand:SI 3 "general_operand" "=d") + (umod:SI (match_dup 1) (match_dup 2)))] + "TARGET_68020" + "* +{ + if (find_reg_note (insn, REG_UNUSED, operands[3])) + return \"divu%.l %2,%0\"; + else + return \"divul%.l %2,%3:%0\"; +}") + +;; logical-and instructions + +;; Prevent AND from being made with sp. This doesn't exist in the machine +;; and reload will cause inefficient code. Since sp is a FIXED_REG, we +;; can't allocate pseudos into it. +(define_insn "andsi3" + [(set (match_operand:SI 0 "not_sp_operand" "=m,d") + (and:SI (match_operand:SI 1 "general_operand" "%0,0") + (match_operand:SI 2 "general_operand" "dKs,dmKs")))] + "" + "* +{ + int logval; + if (GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) | 0xffff) == 0xffffffff + && (DATA_REG_P (operands[0]) + || offsettable_memref_p (operands[0]))) + { + if (GET_CODE (operands[0]) != REG) + operands[0] = adj_offsettable_operand (operands[0], 2); + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) & 0xffff); + /* Do not delete a following tstl %0 insn; that would be incorrect. */ + CC_STATUS_INIT; + if (operands[2] == const0_rtx) + return \"clr%.w %0\"; + return \"and%.w %2,%0\"; + } + if (GET_CODE (operands[2]) == CONST_INT + && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 + && (DATA_REG_P (operands[0]) + || offsettable_memref_p (operands[0]))) + { + if (DATA_REG_P (operands[0])) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); + } + else + { + operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); + } + /* This does not set condition codes in a standard way. */ + CC_STATUS_INIT; + return \"bclr %1,%0\"; + } + return \"and%.l %2,%0\"; +}") + +(define_insn "andhi3" + [(set (match_operand:HI 0 "general_operand" "=m,d") + (and:HI (match_operand:HI 1 "general_operand" "%0,0") + (match_operand:HI 2 "general_operand" "dn,dmn")))] + "" + "and%.w %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) + (and:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dn,dmn")))] + "" + "and%.w %1,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) + (and:HI (match_operand:HI 1 "general_operand" "dn,dmn") + (match_dup 0)))] + "" + "and%.w %1,%0") + +(define_insn "andqi3" + [(set (match_operand:QI 0 "general_operand" "=m,d") + (and:QI (match_operand:QI 1 "general_operand" "%0,0") + (match_operand:QI 2 "general_operand" "dn,dmn")))] + "" + "and%.b %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) + (and:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dn,dmn")))] + "" + "and%.b %1,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) + (and:QI (match_operand:QI 1 "general_operand" "dn,dmn") + (match_dup 0)))] + "" + "and%.b %1,%0") + +;; inclusive-or instructions + +(define_insn "iorsi3" + [(set (match_operand:SI 0 "general_operand" "=m,d") + (ior:SI (match_operand:SI 1 "general_operand" "%0,0") + (match_operand:SI 2 "general_operand" "dKs,dmKs")))] + "" + "* +{ + register int logval; + if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) >> 16 == 0 + && (DATA_REG_P (operands[0]) + || offsettable_memref_p (operands[0]))) + { + if (GET_CODE (operands[0]) != REG) + operands[0] = adj_offsettable_operand (operands[0], 2); + /* Do not delete a following tstl %0 insn; that would be incorrect. */ + CC_STATUS_INIT; + return \"or%.w %2,%0\"; + } + if (GET_CODE (operands[2]) == CONST_INT + && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 + && (DATA_REG_P (operands[0]) + || offsettable_memref_p (operands[0]))) + { + if (DATA_REG_P (operands[0])) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); + } + else + { + operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); + operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); + } + CC_STATUS_INIT; + return \"bset %1,%0\"; + } + return \"or%.l %2,%0\"; +}") + +(define_insn "iorhi3" + [(set (match_operand:HI 0 "general_operand" "=m,d") + (ior:HI (match_operand:HI 1 "general_operand" "%0,0") + (match_operand:HI 2 "general_operand" "dn,dmn")))] + "" + "or%.w %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) + (ior:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dn,dmn")))] + "" + "or%.w %1,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) + (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn") + (match_dup 0)))] + "" + "or%.w %1,%0") + +(define_insn "iorqi3" + [(set (match_operand:QI 0 "general_operand" "=m,d") + (ior:QI (match_operand:QI 1 "general_operand" "%0,0") + (match_operand:QI 2 "general_operand" "dn,dmn")))] + "" + "or%.b %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) + (ior:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dn,dmn")))] + "" + "or%.b %1,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) + (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn") + (match_dup 0)))] + "" + "or%.b %1,%0") + +;; xor instructions + +(define_insn "xorsi3" + [(set (match_operand:SI 0 "general_operand" "=do,m") + (xor:SI (match_operand:SI 1 "general_operand" "%0,0") + (match_operand:SI 2 "general_operand" "di,dKs")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) >> 16 == 0 + && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))) + { + if (! DATA_REG_P (operands[0])) + operands[0] = adj_offsettable_operand (operands[0], 2); + /* Do not delete a following tstl %0 insn; that would be incorrect. */ + CC_STATUS_INIT; + return \"eor%.w %2,%0\"; + } + return \"eor%.l %2,%0\"; +}") + +(define_insn "xorhi3" + [(set (match_operand:HI 0 "general_operand" "=dm") + (xor:HI (match_operand:HI 1 "general_operand" "%0") + (match_operand:HI 2 "general_operand" "dn")))] + "" + "eor%.w %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) + (xor:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dn")))] + "" + "eor%.w %1,%0") + + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) + (xor:HI (match_operand:HI 1 "general_operand" "dn") + (match_dup 0)))] + "" + "eor%.w %1,%0") + +(define_insn "xorqi3" + [(set (match_operand:QI 0 "general_operand" "=dm") + (xor:QI (match_operand:QI 1 "general_operand" "%0") + (match_operand:QI 2 "general_operand" "dn")))] + "" + "eor%.b %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) + (xor:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dn")))] + "" + "eor%.b %1,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) + (xor:QI (match_operand:QI 1 "general_operand" "dn") + (match_dup 0)))] + "" + "eor%.b %1,%0") + +;; negation instructions + +(define_insn "negsi2" + [(set (match_operand:SI 0 "general_operand" "=dm") + (neg:SI (match_operand:SI 1 "general_operand" "0")))] + "" + "neg%.l %0") + +(define_insn "neghi2" + [(set (match_operand:HI 0 "general_operand" "=dm") + (neg:HI (match_operand:HI 1 "general_operand" "0")))] + "" + "neg%.w %0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) + (neg:HI (match_dup 0)))] + "" + "neg%.w %0") + +(define_insn "negqi2" + [(set (match_operand:QI 0 "general_operand" "=dm") + (neg:QI (match_operand:QI 1 "general_operand" "0")))] + "" + "neg%.b %0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) + (neg:QI (match_dup 0)))] + "" + "neg%.b %0") + +(define_expand "negsf2" + [(set (match_operand:SF 0 "general_operand" "") + (neg:SF (match_operand:SF 1 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=x,y") + (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))] + "TARGET_FPA" + "fpneg%.s %w1,%0") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=f,d") + (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))] + "TARGET_68881" + "* +{ + if (DATA_REG_P (operands[0])) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, 31); + return \"bchg %1,%0\"; + } + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return \"f%$neg%.x %1,%0\"; + return \"f%$neg%.s %f1,%0\"; +}") + +(define_expand "negdf2" + [(set (match_operand:DF 0 "general_operand" "") + (neg:DF (match_operand:DF 1 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=x,y") + (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))] + "TARGET_FPA" + "fpneg%.d %y1, %0") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=f,d") + (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))] + "TARGET_68881" + "* +{ + if (DATA_REG_P (operands[0])) + { + operands[1] = gen_rtx (CONST_INT, VOIDmode, 31); + return \"bchg %1,%0\"; + } + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return \"f%&neg%.x %1,%0\"; + return \"f%&neg%.d %f1,%0\"; +}") + +;; Sqrt instruction for the 68881 + +(define_insn "sqrtdf2" + [(set (match_operand:DF 0 "general_operand" "=f") + (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))] + "TARGET_68881" + "* +{ + if (FP_REG_P (operands[1])) + return \"fsqrt%.x %1,%0\"; + else + return \"fsqrt%.d %1,%0\"; +}") + +;; Absolute value instructions + +(define_expand "abssf2" + [(set (match_operand:SF 0 "general_operand" "") + (abs:SF (match_operand:SF 1 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=x,y") + (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))] + "TARGET_FPA" + "fpabs%.s %y1,%0") + +(define_insn "" + [(set (match_operand:SF 0 "general_operand" "=f") + (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return \"f%$abs%.x %1,%0\"; + return \"f%$abs%.s %f1,%0\"; +}") + +(define_expand "absdf2" + [(set (match_operand:DF 0 "general_operand" "") + (abs:DF (match_operand:DF 1 "general_operand" "")))] + "TARGET_68881 || TARGET_FPA" + "") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=x,y") + (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))] + "TARGET_FPA" + "fpabs%.d %y1,%0") + +(define_insn "" + [(set (match_operand:DF 0 "general_operand" "=f") + (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return \"f%&abs%.x %1,%0\"; + return \"f%&abs%.d %f1,%0\"; +}") + +;; one complement instructions + +(define_insn "one_cmplsi2" + [(set (match_operand:SI 0 "general_operand" "=dm") + (not:SI (match_operand:SI 1 "general_operand" "0")))] + "" + "not%.l %0") + +(define_insn "one_cmplhi2" + [(set (match_operand:HI 0 "general_operand" "=dm") + (not:HI (match_operand:HI 1 "general_operand" "0")))] + "" + "not%.w %0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) + (not:HI (match_dup 0)))] + "" + "not%.w %0") + +(define_insn "one_cmplqi2" + [(set (match_operand:QI 0 "general_operand" "=dm") + (not:QI (match_operand:QI 1 "general_operand" "0")))] + "" + "not%.b %0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) + (not:QI (match_dup 0)))] + "" + "not%.b %0") + +;; arithmetic shift instructions +;; We don't need the shift memory by 1 bit instruction + +;; On all 68k models, this makes faster code in a special case. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashift:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" + "* +{ + CC_STATUS_INIT; + return \"swap %0\;clr%.w %0\"; +}") + +;; On the 68000, this makes faster code in a special case. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashift:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" + "* +{ + CC_STATUS_INIT; + + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); + return \"asl%.w %2,%0\;swap %0\;clr%.w %0\"; +}") + +(define_insn "ashlsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashift:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "general_operand" "dI")))] + "" + "* +{ + if (operands[2] == const1_rtx) + return \"add%.l %0,%0\"; + return \"asl%.l %2,%0\"; +}") + +(define_insn "ashlhi3" + [(set (match_operand:HI 0 "register_operand" "=d") + (ashift:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "dI")))] + "" + "asl%.w %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) + (ashift:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dI")))] + "" + "asl%.w %1,%0") + +(define_insn "ashlqi3" + [(set (match_operand:QI 0 "register_operand" "=d") + (ashift:QI (match_operand:QI 1 "register_operand" "0") + (match_operand:QI 2 "general_operand" "dI")))] + "" + "asl%.b %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) + (ashift:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dI")))] + "" + "asl%.b %1,%0") + +;; On all 68k models, this makes faster code in a special case. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" + "swap %0\;ext%.l %0") + +;; On the 68000, this makes faster code in a special case. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" + "* +{ + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); + return \"swap %0\;asr%.w %2,%0\;ext%.l %0\"; +}") + +(define_insn "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "general_operand" "dI")))] + "" + "* +{ + return \"asr%.l %2,%0\"; +}") + +(define_insn "ashrhi3" + [(set (match_operand:HI 0 "register_operand" "=d") + (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "dI")))] + "" + "asr%.w %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) + (ashiftrt:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dI")))] + "" + "asr%.w %1,%0") + +(define_insn "ashrqi3" + [(set (match_operand:QI 0 "register_operand" "=d") + (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") + (match_operand:QI 2 "general_operand" "dI")))] + "" + "asr%.b %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) + (ashiftrt:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dI")))] + "" + "asr%.b %1,%0") + +;; logical shift instructions + +;; On all 68k models, this makes faster code in a special case. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (lshift:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" + "* +{ + CC_STATUS_INIT; + return \"swap %0\;clr%.w %0\"; +}") + +;; On the 68000, this makes faster code in a special case. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (lshift:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" + "* +{ + CC_STATUS_INIT; + + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); + return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\"; +}") + +(define_insn "lshlsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (lshift:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "general_operand" "dI")))] + "" + "* +{ + if (operands[2] == const1_rtx) + return \"add%.l %0,%0\"; + return \"lsl%.l %2,%0\"; +}") + +(define_insn "lshlhi3" + [(set (match_operand:HI 0 "register_operand" "=d") + (lshift:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "dI")))] + "" + "lsl%.w %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) + (lshift:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dI")))] + "" + "lsl%.w %1,%0") + +(define_insn "lshlqi3" + [(set (match_operand:QI 0 "register_operand" "=d") + (lshift:QI (match_operand:QI 1 "register_operand" "0") + (match_operand:QI 2 "general_operand" "dI")))] + "" + "lsl%.b %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) + (lshift:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dI")))] + "" + "lsl%.b %1,%0") + +;; On all 68k models, this makes faster code in a special case. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" + "* +{ + CC_STATUS_INIT; + return \"clr%.w %0\;swap %0\"; +}") + +;; On the 68000, this makes faster code in a special case. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" + "* +{ + /* I think lsr%.w sets the CC properly. */ + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); + return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\"; +}") + +(define_insn "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "general_operand" "dI")))] + "" + "* +{ + return \"lsr%.l %2,%0\"; +}") + +(define_insn "lshrhi3" + [(set (match_operand:HI 0 "register_operand" "=d") + (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "dI")))] + "" + "lsr%.w %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) + (lshiftrt:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dI")))] + "" + "lsr%.w %1,%0") + +(define_insn "lshrqi3" + [(set (match_operand:QI 0 "register_operand" "=d") + (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") + (match_operand:QI 2 "general_operand" "dI")))] + "" + "lsr%.b %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) + (lshiftrt:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dI")))] + "" + "lsr%.b %1,%0") + +;; rotate instructions + +(define_insn "rotlsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (rotate:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "general_operand" "dI")))] + "" + "rol%.l %2,%0") + +(define_insn "rotlhi3" + [(set (match_operand:HI 0 "register_operand" "=d") + (rotate:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "dI")))] + "" + "rol%.w %2,%0") + + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) + (rotate:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dI")))] + "" + "rol%.w %1,%0") + +(define_insn "rotlqi3" + [(set (match_operand:QI 0 "register_operand" "=d") + (rotate:QI (match_operand:QI 1 "register_operand" "0") + (match_operand:QI 2 "general_operand" "dI")))] + "" + "rol%.b %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) + (rotate:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dI")))] + "" + "rol%.b %1,%0") + +(define_insn "rotrsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (rotatert:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "general_operand" "dI")))] + "" + "ror%.l %2,%0") + +(define_insn "rotrhi3" + [(set (match_operand:HI 0 "register_operand" "=d") + (rotatert:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "dI")))] + "" + "ror%.w %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) + (rotatert:HI (match_dup 0) + (match_operand:HI 1 "general_operand" "dI")))] + "" + "ror%.w %1,%0") + +(define_insn "rotrqi3" + [(set (match_operand:QI 0 "register_operand" "=d") + (rotatert:QI (match_operand:QI 1 "register_operand" "0") + (match_operand:QI 2 "general_operand" "dI")))] + "" + "ror%.b %2,%0") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) + (rotatert:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "dI")))] + "" + "ror%.b %1,%0") + +;; Special cases of bit-field insns which we should +;; recognize in preference to the general case. +;; These handle aligned 8-bit and 16-bit fields, +;; which can usually be done with move instructions. + +; +; Special case for 32-bit field in memory. This only occurs when 32-bit +; alignment of structure members is specified. +; +; The move is allowed to be odd byte aligned, because that's still faster +; than an odd byte aligned bit field instruction. +; +(define_insn "" + [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o") + (match_operand:SI 1 "immediate_operand" "i") + (match_operand:SI 2 "immediate_operand" "i")) + (match_operand:SI 3 "general_operand" "rmi"))] + "TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[1]) == CONST_INT + && (INTVAL (operands[1]) == 32) + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) % 8) == 0 + && ! mode_dependent_address_p (XEXP (operands[0], 0))" + "* +{ + operands[0] + = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); + + return \"move%.l %3,%0\"; +}") + +(define_insn "" + [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do") + (match_operand:SI 1 "immediate_operand" "i") + (match_operand:SI 2 "immediate_operand" "i")) + (match_operand:SI 3 "general_operand" "d"))] + "TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[1]) == CONST_INT + && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 + && (GET_CODE (operands[0]) == REG + || ! mode_dependent_address_p (XEXP (operands[0], 0)))" + "* +{ + if (REG_P (operands[0])) + { + if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32) + return \"bfins %3,%0{%b2:%b1}\"; + } + else + operands[0] + = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); + + if (GET_CODE (operands[3]) == MEM) + operands[3] = adj_offsettable_operand (operands[3], + (32 - INTVAL (operands[1])) / 8); + if (INTVAL (operands[1]) == 8) + return \"move%.b %3,%0\"; + return \"move%.w %3,%0\"; +}") + + +; +; Special case for 32-bit field in memory. This only occurs when 32-bit +; alignment of structure members is specified. +; +; The move is allowed to be odd byte aligned, because that's still faster +; than an odd byte aligned bit field instruction. +; +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=rm") + (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")))] + "TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) == 32) + && GET_CODE (operands[3]) == CONST_INT + && (INTVAL (operands[3]) % 8) == 0 + && ! mode_dependent_address_p (XEXP (operands[1], 0))" + "* +{ + operands[1] + = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); + + return \"move%.l %1,%0\"; +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=&d") + (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")))] + "TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) + && GET_CODE (operands[3]) == CONST_INT + && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 + && (GET_CODE (operands[1]) == REG + || ! mode_dependent_address_p (XEXP (operands[1], 0)))" + "* +{ + cc_status.flags |= CC_NOT_NEGATIVE; + if (REG_P (operands[1])) + { + if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) + return \"bfextu %1{%b3:%b2},%0\"; + } + else + operands[1] + = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); + + output_asm_insn (\"clr%.l %0\", operands); + if (GET_CODE (operands[0]) == MEM) + operands[0] = adj_offsettable_operand (operands[0], + (32 - INTVAL (operands[1])) / 8); + if (INTVAL (operands[2]) == 8) + return \"move%.b %1,%0\"; + return \"move%.w %1,%0\"; +}") + +; +; Special case for 32-bit field in memory. This only occurs when 32-bit +; alignment of structure members is specified. +; +; The move is allowed to be odd byte aligned, because that's still faster +; than an odd byte aligned bit field instruction. +; +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=rm") + (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")))] + "TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) == 32) + && GET_CODE (operands[3]) == CONST_INT + && (INTVAL (operands[3]) % 8) == 0 + && ! mode_dependent_address_p (XEXP (operands[1], 0))" + "* +{ + operands[1] + = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); + + return \"move%.l %1,%0\"; +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=d") + (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do") + (match_operand:SI 2 "immediate_operand" "i") + (match_operand:SI 3 "immediate_operand" "i")))] + "TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) + && GET_CODE (operands[3]) == CONST_INT + && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 + && (GET_CODE (operands[1]) == REG + || ! mode_dependent_address_p (XEXP (operands[1], 0)))" + "* +{ + if (REG_P (operands[1])) + { + if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) + return \"bfexts %1{%b3:%b2},%0\"; + } + else + operands[1] + = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); + + if (INTVAL (operands[2]) == 8) + return \"move%.b %1,%0\;extb%.l %0\"; + return \"move%.w %1,%0\;ext%.l %0\"; +}") + +;; Bit field instructions, general cases. +;; "o,d" constraint causes a nonoffsettable memref to match the "o" +;; so that its address is reloaded. + +(define_insn "extv" + [(set (match_operand:SI 0 "general_operand" "=d,d") + (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d") + (match_operand:SI 2 "general_operand" "di,di") + (match_operand:SI 3 "general_operand" "di,di")))] + "TARGET_68020 && TARGET_BITFIELD" + "bfexts %1{%b3:%b2},%0") + +(define_insn "extzv" + [(set (match_operand:SI 0 "general_operand" "=d,d") + (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d") + (match_operand:SI 2 "general_operand" "di,di") + (match_operand:SI 3 "general_operand" "di,di")))] + "TARGET_68020 && TARGET_BITFIELD" + "* +{ + cc_status.flags |= CC_NOT_NEGATIVE; + return \"bfextu %1{%b3:%b2},%0\"; +}") + +(define_insn "" + [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") + (match_operand:SI 1 "general_operand" "di,di") + (match_operand:SI 2 "general_operand" "di,di")) + (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)) + (match_operand 3 "immediate_operand" "i,i")))] + "TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[3]) == CONST_INT + && (INTVAL (operands[3]) == -1 + || (GET_CODE (operands[1]) == CONST_INT + && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))" + "* +{ + CC_STATUS_INIT; + return \"bfchg %0{%b2:%b1}\"; +}") + +(define_insn "" + [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") + (match_operand:SI 1 "general_operand" "di,di") + (match_operand:SI 2 "general_operand" "di,di")) + (const_int 0))] + "TARGET_68020 && TARGET_BITFIELD" + "* +{ + CC_STATUS_INIT; + return \"bfclr %0{%b2:%b1}\"; +}") + +(define_insn "" + [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") + (match_operand:SI 1 "general_operand" "di,di") + (match_operand:SI 2 "general_operand" "di,di")) + (const_int -1))] + "TARGET_68020 && TARGET_BITFIELD" + "* +{ + CC_STATUS_INIT; + return \"bfset %0{%b2:%b1}\"; +}") + +(define_insn "insv" + [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") + (match_operand:SI 1 "general_operand" "di,di") + (match_operand:SI 2 "general_operand" "di,di")) + (match_operand:SI 3 "general_operand" "d,d"))] + "TARGET_68020 && TARGET_BITFIELD" + "bfins %3,%0{%b2:%b1}") + +;; Now recognize bit field insns that operate on registers +;; (or at least were intended to do so). + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=d") + (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d") + (match_operand:SI 2 "general_operand" "di") + (match_operand:SI 3 "general_operand" "di")))] + "TARGET_68020 && TARGET_BITFIELD" + "bfexts %1{%b3:%b2},%0") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=d") + (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d") + (match_operand:SI 2 "general_operand" "di") + (match_operand:SI 3 "general_operand" "di")))] + "TARGET_68020 && TARGET_BITFIELD" + "* +{ + cc_status.flags |= CC_NOT_NEGATIVE; + return \"bfextu %1{%b3:%b2},%0\"; +}") + +(define_insn "" + [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") + (match_operand:SI 1 "general_operand" "di") + (match_operand:SI 2 "general_operand" "di")) + (const_int 0))] + "TARGET_68020 && TARGET_BITFIELD" + "* +{ + CC_STATUS_INIT; + return \"bfclr %0{%b2:%b1}\"; +}") + +(define_insn "" + [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") + (match_operand:SI 1 "general_operand" "di") + (match_operand:SI 2 "general_operand" "di")) + (const_int -1))] + "TARGET_68020 && TARGET_BITFIELD" + "* +{ + CC_STATUS_INIT; + return \"bfset %0{%b2:%b1}\"; +}") + +(define_insn "" + [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") + (match_operand:SI 1 "general_operand" "di") + (match_operand:SI 2 "general_operand" "di")) + (match_operand:SI 3 "general_operand" "d"))] + "TARGET_68020 && TARGET_BITFIELD" + "* +{ +#if 0 + /* These special cases are now recognized by a specific pattern. */ + if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16) + return \"move%.w %3,%0\"; + if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8) + return \"move%.b %3,%0\"; +#endif + return \"bfins %3,%0{%b2:%b1}\"; +}") + +;; Special patterns for optimizing bit-field instructions. + +(define_insn "" + [(set (cc0) + (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") + (match_operand:SI 1 "general_operand" "di") + (match_operand:SI 2 "general_operand" "di")))] + "TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[1]) == CONST_INT" + "* +{ + if (operands[1] == const1_rtx + && GET_CODE (operands[2]) == CONST_INT) + { + int width = GET_CODE (operands[0]) == REG ? 31 : 7; + return output_btst (operands, + gen_rtx (CONST_INT, VOIDmode, + width - INTVAL (operands[2])), + operands[0], + insn, 1000); + /* Pass 1000 as SIGNPOS argument so that btst will + not think we are testing the sign bit for an `and' + and assume that nonzero implies a negative result. */ + } + if (INTVAL (operands[1]) != 32) + cc_status.flags = CC_NOT_NEGATIVE; + return \"bftst %0{%b2:%b1}\"; +}") + + +;;; now handle the register cases +(define_insn "" + [(set (cc0) + (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d") + (match_operand:SI 1 "general_operand" "di") + (match_operand:SI 2 "general_operand" "di")))] + "TARGET_68020 && TARGET_BITFIELD + && GET_CODE (operands[1]) == CONST_INT" + "* +{ + if (operands[1] == const1_rtx + && GET_CODE (operands[2]) == CONST_INT) + { + int width = GET_CODE (operands[0]) == REG ? 31 : 7; + return output_btst (operands, + gen_rtx (CONST_INT, VOIDmode, + width - INTVAL (operands[2])), + operands[0], + insn, 1000); + /* Pass 1000 as SIGNPOS argument so that btst will + not think we are testing the sign bit for an `and' + and assume that nonzero implies a negative result. */ + } + if (INTVAL (operands[1]) != 32) + cc_status.flags = CC_NOT_NEGATIVE; + return \"bftst %0{%b2:%b1}\"; +}") + +(define_insn "seq" + [(set (match_operand:QI 0 "general_operand" "=d") + (eq:QI (cc0) (const_int 0)))] + "" + "* + cc_status = cc_prev_status; + OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\"); +") + +(define_insn "sne" + [(set (match_operand:QI 0 "general_operand" "=d") + (ne:QI (cc0) (const_int 0)))] + "" + "* + cc_status = cc_prev_status; + OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\"); +") + +(define_insn "sgt" + [(set (match_operand:QI 0 "general_operand" "=d") + (gt:QI (cc0) (const_int 0)))] + "" + "* + cc_status = cc_prev_status; + OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0); +") + +(define_insn "sgtu" + [(set (match_operand:QI 0 "general_operand" "=d") + (gtu:QI (cc0) (const_int 0)))] + "" + "* cc_status = cc_prev_status; + return \"shi %0\"; ") + +(define_insn "slt" + [(set (match_operand:QI 0 "general_operand" "=d") + (lt:QI (cc0) (const_int 0)))] + "" + "* cc_status = cc_prev_status; + OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ") + +(define_insn "sltu" + [(set (match_operand:QI 0 "general_operand" "=d") + (ltu:QI (cc0) (const_int 0)))] + "" + "* cc_status = cc_prev_status; + return \"scs %0\"; ") + +(define_insn "sge" + [(set (match_operand:QI 0 "general_operand" "=d") + (ge:QI (cc0) (const_int 0)))] + "" + "* cc_status = cc_prev_status; + OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ") + +(define_insn "sgeu" + [(set (match_operand:QI 0 "general_operand" "=d") + (geu:QI (cc0) (const_int 0)))] + "" + "* cc_status = cc_prev_status; + return \"scc %0\"; ") + +(define_insn "sle" + [(set (match_operand:QI 0 "general_operand" "=d") + (le:QI (cc0) (const_int 0)))] + "" + "* + cc_status = cc_prev_status; + OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0); +") + +(define_insn "sleu" + [(set (match_operand:QI 0 "general_operand" "=d") + (leu:QI (cc0) (const_int 0)))] + "" + "* cc_status = cc_prev_status; + return \"sls %0\"; ") + +;; Basic conditional jump instructions. + +(define_insn "beq" + [(set (pc) + (if_then_else (eq (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +{ +#ifdef MOTOROLA + OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\"); +#else + OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\"); +#endif +}") + +(define_insn "bne" + [(set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +{ +#ifdef MOTOROLA + OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\"); +#else + OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\"); +#endif +}") + +(define_insn "bgt" + [(set (pc) + (if_then_else (gt (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +#ifdef MOTOROLA + OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0); +#else + OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0); +#endif +") + +(define_insn "bgtu" + [(set (pc) + (if_then_else (gtu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +#ifdef MOTOROLA + return \"jbhi %l0\"; +#else + return \"jhi %l0\"; +#endif +") + +(define_insn "blt" + [(set (pc) + (if_then_else (lt (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +#ifdef MOTOROLA + OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\"); +#else + OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\"); +#endif +") + +(define_insn "bltu" + [(set (pc) + (if_then_else (ltu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +#ifdef MOTOROLA + return \"jbcs %l0\"; +#else + return \"jcs %l0\"; +#endif +") + +(define_insn "bge" + [(set (pc) + (if_then_else (ge (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +#ifdef MOTOROLA + OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\"); +#else + OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\"); +#endif +") + +(define_insn "bgeu" + [(set (pc) + (if_then_else (geu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +#ifdef MOTOROLA + return \"jbcc %l0\"; +#else + return \"jcc %l0\"; +#endif +") + +(define_insn "ble" + [(set (pc) + (if_then_else (le (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +#ifdef MOTOROLA + OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0); +#else + OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0); +#endif +") + +(define_insn "bleu" + [(set (pc) + (if_then_else (leu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +#ifdef MOTOROLA + return \"jbls %l0\"; +#else + return \"jls %l0\"; +#endif +") + +;; Negated conditional jump instructions. + +(define_insn "" + [(set (pc) + (if_then_else (eq (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +{ +#ifdef MOTOROLA + OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\"); +#else + OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\"); +#endif +}") + +(define_insn "" + [(set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +{ +#ifdef MOTOROLA + OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\"); +#else + OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\"); +#endif +}") + +(define_insn "" + [(set (pc) + (if_then_else (gt (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +#ifdef MOTOROLA + OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0); +#else + OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0); +#endif +") + +(define_insn "" + [(set (pc) + (if_then_else (gtu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +#ifdef MOTOROLA + return \"jbls %l0\"; +#else + return \"jls %l0\"; +#endif +") + +(define_insn "" + [(set (pc) + (if_then_else (lt (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +#ifdef MOTOROLA + OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\"); +#else + OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\"); +#endif +") + +(define_insn "" + [(set (pc) + (if_then_else (ltu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +#ifdef MOTOROLA + return \"jbcc %l0\"; +#else + return \"jcc %l0\"; +#endif +") + +(define_insn "" + [(set (pc) + (if_then_else (ge (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +#ifdef MOTOROLA + OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\"); +#else + OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\"); +#endif +") + +(define_insn "" + [(set (pc) + (if_then_else (geu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +#ifdef MOTOROLA + return \"jbcs %l0\"; +#else + return \"jcs %l0\"; +#endif +") + +(define_insn "" + [(set (pc) + (if_then_else (le (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +#ifdef MOTOROLA + OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0); +#else + OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0); +#endif +") + +(define_insn "" + [(set (pc) + (if_then_else (leu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +#ifdef MOTOROLA + return \"jbhi %l0\"; +#else + return \"jhi %l0\"; +#endif +") + +;; Unconditional and other jump instructions +(define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] + "" + "* +#ifdef MOTOROLA + return \"jbra %l0\"; +#else + return \"jra %l0\"; +#endif +") + +;; We support two different ways of handling dispatch tables. +;; The NeXT uses absolute tables, and other machines use relative. +;; This define_expand can generate either kind. +(define_expand "tablejump" + [(parallel [(set (pc) (match_operand 0 "" "")) + (use (label_ref (match_operand 1 "" "")))])] + "" + " +{ +#ifdef CASE_VECTOR_PC_RELATIVE + operands[0] = gen_rtx (PLUS, SImode, pc_rtx, operands[0]); +#endif +}") + +;; Jump to variable address from dispatch table of absolute addresses. +(define_insn "" + [(set (pc) (match_operand:SI 0 "register_operand" "a")) + (use (label_ref (match_operand 1 "" "")))] + "" + "* +#ifdef MOTOROLA + return \"jmp (%0)\"; +#else + return \"jmp %0@\"; +#endif +") + +;; Jump to variable address from dispatch table of relative addresses. +(define_insn "" + [(set (pc) + (plus:SI (pc) (match_operand:HI 0 "register_operand" "r"))) + (use (label_ref (match_operand 1 "" "")))] + "" + "* +#ifdef ASM_RETURN_CASE_JUMP + ASM_RETURN_CASE_JUMP; +#else +#ifdef SGS +#ifdef ASM_OUTPUT_CASE_LABEL + return \"jmp 6(%%pc,%0.w)\"; +#else +#ifdef CRDS + return \"jmp 2(pc,%0.w)\"; +#else + return \"jmp 2(%%pc,%0.w)\"; +#endif /* end !CRDS */ +#endif +#else /* not SGS */ +#ifdef MOTOROLA + return \"jmp (2,pc,%0.w)\"; +#else + return \"jmp pc@(2,%0:w)\"; +#endif +#endif +#endif +") + +;; Decrement-and-branch insns. +(define_insn "" + [(set (pc) + (if_then_else + (ne (match_operand:HI 0 "general_operand" "+g") + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (set (match_dup 0) + (plus:HI (match_dup 0) + (const_int -1)))] + "" + "* +{ + CC_STATUS_INIT; + if (DATA_REG_P (operands[0])) + return \"dbra %0,%l1\"; + if (GET_CODE (operands[0]) == MEM) + { +#ifdef MOTOROLA +#ifdef NO_ADDSUB_Q + return \"sub%.w %#1,%0\;jbcc %l1\"; +#else + return \"subq%.w %#1,%0\;jbcc %l1\"; +#endif +#else /* not MOTOROLA */ + return \"subqw %#1,%0\;jcc %l1\"; +#endif + } +#ifdef MOTOROLA +#ifdef SGS_CMP_ORDER +#ifdef NO_ADDSUB_Q + return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\"; +#else + return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\"; +#endif +#else /* not SGS_CMP_ORDER */ + return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\"; +#endif +#else /* not MOTOROLA */ + return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\"; +#endif +}") + +(define_insn "" + [(set (pc) + (if_then_else + (ne (match_operand:SI 0 "general_operand" "+g") + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (set (match_dup 0) + (plus:SI (match_dup 0) + (const_int -1)))] + "" + "* +{ + CC_STATUS_INIT; +#ifdef MOTOROLA +#ifdef NO_ADDSUB_Q + if (DATA_REG_P (operands[0])) + return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\"; + if (GET_CODE (operands[0]) == MEM) + return \"sub%.l %#1,%0\;jbcc %l1\"; +#else + if (DATA_REG_P (operands[0])) + return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\"; + if (GET_CODE (operands[0]) == MEM) + return \"subq%.l %#1,%0\;jbcc %l1\"; +#endif /* NO_ADDSUB_Q */ +#ifdef SGS_CMP_ORDER +#ifdef NO_ADDSUB_Q + return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; +#else + return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; +#endif +#else /* not SGS_CMP_ORDER */ + return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\"; +#endif /* not SGS_CMP_ORDER */ +#else /* not MOTOROLA */ + if (DATA_REG_P (operands[0])) + return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\"; + if (GET_CODE (operands[0]) == MEM) + return \"subql %#1,%0\;jcc %l1\"; + return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\"; +#endif /* not MOTOROLA */ +}") + +;; Two dbra patterns that use REG_NOTES info generated by strength_reduce. + +(define_insn "" + [(set (pc) + (if_then_else + (ge (plus:HI (match_operand:HI 0 "general_operand" "+g") + (const_int -1)) + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (set (match_dup 0) + (plus:HI (match_dup 0) + (const_int -1)))] + "find_reg_note (insn, REG_NONNEG, 0)" + "* +{ + CC_STATUS_INIT; +#ifdef MOTOROLA +#ifdef NO_ADDSUB_Q + if (DATA_REG_P (operands[0])) + return \"dbra %0,%l1\"; + if (GET_CODE (operands[0]) == MEM) + return \"sub%.w %#1,%0\;jbcc %l1\"; +#else + if (DATA_REG_P (operands[0])) + return \"dbra %0,%l1\"; + if (GET_CODE (operands[0]) == MEM) + return \"subq%.w %#1,%0\;jbcc %l1\"; +#endif +#ifdef SGS_CMP_ORDER +#ifdef NO_ADDSUB_Q + return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\"; +#else + return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\"; +#endif +#else /* not SGS_CMP_ORDER */ + return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\"; +#endif /* not SGS_CMP_ORDER */ +#else /* not MOTOROLA */ + if (DATA_REG_P (operands[0])) + return \"dbra %0,%l1\"; + if (GET_CODE (operands[0]) == MEM) + return \"subqw %#1,%0\;jcc %l1\"; + return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\"; +#endif /* not MOTOROLA */ +}") + +(define_insn "decrement_and_branch_until_zero" + [(set (pc) + (if_then_else + (ge (plus:SI (match_operand:SI 0 "general_operand" "+g") + (const_int -1)) + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (set (match_dup 0) + (plus:SI (match_dup 0) + (const_int -1)))] + "find_reg_note (insn, REG_NONNEG, 0)" + "* +{ + CC_STATUS_INIT; +#ifdef MOTOROLA +#ifdef NO_ADDSUB_Q + if (DATA_REG_P (operands[0])) + return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\"; + if (GET_CODE (operands[0]) == MEM) + return \"sub%.l %#1,%0\;jbcc %l1\"; +#else + if (DATA_REG_P (operands[0])) + return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\"; + if (GET_CODE (operands[0]) == MEM) + return \"subq%.l %#1,%0\;jbcc %l1\"; +#endif +#ifdef SGS_CMP_ORDER +#ifdef NO_ADDSUB_Q + return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; +#else + return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; +#endif +#else /* not SGS_CMP_ORDER */ + return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\"; +#endif /* not SGS_CMP_ORDER */ +#else /* not MOTOROLA */ + if (DATA_REG_P (operands[0])) + return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\"; + if (GET_CODE (operands[0]) == MEM) + return \"subql %#1,%0\;jcc %l1\"; + return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\"; +#endif /* not MOTOROLA */ +}") + + +;; For PIC calls, in order to be able to support +;; dynamic linker LAZY BINDING, all the procedure calls need to go +;; through the PLT (Procedure Linkage Table) section in PIC mode. +;; +;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra +;; operand to the jbsr statement to indicate that this call should +;; go through the PLT (why? because this is the way that Sun does it). +;; +;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it +;; will create the correct relocation entry (R_68K_PLT32) for `FUNC', +;; that tells the linker editor to create an entry for `FUNC' in PLT +;; section at link time. However, all global objects reference are still +;; done by using `OBJ@GOT'. So, the goal here is to output the function +;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'. +;; We need to have a way to differentiate these two different operands. +;; +;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate +;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs +;; to be changed to recognize function calls symbol_ref operand as a legal +;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will +;; avoid the compiler to load this symbol_ref operand into a register. +;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly +;; since the value is a PC relative offset, not a real address. +;; +;; All global objects are treated in the similar way as in SUN3. The only +;; difference is: on m68k svr4, the reference of such global object needs +;; to end with a suffix "@GOT" so the assembler and linker know to create +;; an entry for it in GOT (Global Offset Table) section. This is done in +;; m68k.c. + +;; Call subroutine with no return value. +(define_expand "call" + [(call (match_operand:QI 0 "memory_operand" "") + (match_operand:SI 1 "general_operand" ""))] + ;; Operand 1 not really used on the m68000. + + "" + " +{ + if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) + SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1; +}") + +;; This is a normal call sequence. +(define_insn "" + [(call (match_operand:QI 0 "memory_operand" "o") + (match_operand:SI 1 "general_operand" "g"))] + ;; Operand 1 not really used on the m68000. + + "! flag_pic" + "* +#ifdef MOTOROLA + return \"jsr %0\"; +#else + return \"jbsr %0\"; +#endif +") + +;; This is a PIC call sequence. +(define_insn "" + [(call (match_operand:QI 0 "memory_operand" "o") + (match_operand:SI 1 "general_operand" "g"))] + ;; Operand 1 not really used on the m68000. + + "flag_pic" + "* + if (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) +#ifdef MOTOROLA + return \"bsr %0@PLTPC\"; +#else + return \"jbsr %0,a1\"; +#endif + return \"jsr %0\"; +") + +;; Call subroutine, returning value in operand 0 +;; (which must be a hard register). +;; See comments before "call" regarding PIC calls. +(define_expand "call_value" + [(set (match_operand 0 "" "") + (call (match_operand:QI 1 "memory_operand" "") + (match_operand:SI 2 "general_operand" "")))] + ;; Operand 2 not really used on the m68000. + "" + " +{ + if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) + SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1; +}") + +;; This is a normal call_value +(define_insn "" + [(set (match_operand 0 "" "=rf") + (call (match_operand:QI 1 "memory_operand" "o") + (match_operand:SI 2 "general_operand" "g")))] + ;; Operand 2 not really used on the m68000. + "! flag_pic" + "* +#ifdef MOTOROLA + return \"jsr %1\"; +#else + return \"jbsr %1\"; +#endif +") + +;; This is a PIC call_value +(define_insn "" + [(set (match_operand 0 "" "=rf") + (call (match_operand:QI 1 "memory_operand" "o") + (match_operand:SI 2 "general_operand" "g")))] + ;; Operand 2 not really used on the m68000. + "flag_pic" + "* + if (GET_CODE (operands[1]) == MEM + && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) +#ifdef MOTOROLA + return \"bsr %1@PLTPC\"; +#else + return \"jbsr %1,a1\"; +#endif + return \"jsr %1\"; +") + +;; Call subroutine returning any type. + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "NEEDS_UNTYPED_CALL" + " +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +}") + +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and +;; all of memory. This blocks insns from being moved across this point. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "") + +(define_insn "nop" + [(const_int 0)] + "" + "nop") + +(define_insn "probe" + [(reg:SI 15)] + "NEED_PROBE" + "* +{ + operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx, + gen_rtx (CONST_INT, VOIDmode, NEED_PROBE)); + return \"tstl %a0\"; +}") + +;; Used for frameless functions which save no regs and allocate no locals. +(define_insn "return" + [(return)] + "USE_RETURN_INSN" + "* +{ + if (current_function_pops_args == 0) + return \"rts\"; + operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args); + return \"rtd %0\"; +}") + +(define_insn "indirect_jump" + [(set (pc) (match_operand:SI 0 "address_operand" "p"))] + "" + "jmp %a0") + +;; This should not be used unless the add/sub insns can't be. + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=a") + (match_operand:QI 1 "address_operand" "p"))] + "" + "lea %a1,%0") + +;; This is the first machine-dependent peephole optimization. +;; It is useful when a floating value is returned from a function call +;; and then is moved into an FP register. +;; But it is mainly intended to test the support for these optimizations. + +(define_peephole + [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) + (set (match_operand:DF 0 "register_operand" "=f") + (match_operand:DF 1 "register_operand" "ad"))] + "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" + "* +{ + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"move%.l %1,%@\", xoperands); + output_asm_insn (\"move%.l %1,%-\", operands); + return \"fmove%.d %+,%0\"; +} +") + +;; Optimize a stack-adjust followed by a push of an argument. +;; This is said to happen frequently with -msoft-float +;; when there are consecutive library calls. + +(define_peephole + [(set (reg:SI 15) (plus:SI (reg:SI 15) + (match_operand:SI 0 "immediate_operand" "n"))) + (set (match_operand:SF 1 "push_operand" "=m") + (match_operand:SF 2 "general_operand" "rmfF"))] + "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) >= 4 + && ! reg_mentioned_p (stack_pointer_rtx, operands[2])" + "* +{ + if (INTVAL (operands[0]) > 4) + { + rtx xoperands[2]; + xoperands[0] = stack_pointer_rtx; + xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4); +#ifndef NO_ADDSUB_Q + if (INTVAL (xoperands[1]) <= 8) + output_asm_insn (\"addq%.w %1,%0\", xoperands); + else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020) + { + xoperands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (xoperands[1]) - 8); + output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); + } + else +#endif + if (INTVAL (xoperands[1]) <= 0x7FFF) + output_asm_insn (\"add%.w %1,%0\", xoperands); + else + output_asm_insn (\"add%.l %1,%0\", xoperands); + } + if (FP_REG_P (operands[2])) + return \"fmove%.s %2,%@\"; + return \"move%.l %2,%@\"; +}") + +;; Speed up stack adjust followed by a fullword fixedpoint push. + +(define_peephole + [(set (reg:SI 15) (plus:SI (reg:SI 15) + (match_operand:SI 0 "immediate_operand" "n"))) + (set (match_operand:SI 1 "push_operand" "=m") + (match_operand:SI 2 "general_operand" "g"))] + "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) >= 4 + && ! reg_mentioned_p (stack_pointer_rtx, operands[2])" + "* +{ + if (INTVAL (operands[0]) > 4) + { + rtx xoperands[2]; + xoperands[0] = stack_pointer_rtx; + xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4); +#ifndef NO_ADDSUB_Q + if (INTVAL (xoperands[1]) <= 8) + output_asm_insn (\"addq%.w %1,%0\", xoperands); + else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020) + { + xoperands[1] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (xoperands[1]) - 8); + output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); + } + else +#endif + if (INTVAL (xoperands[1]) <= 0x7FFF) + output_asm_insn (\"add%.w %1,%0\", xoperands); + else + output_asm_insn (\"add%.l %1,%0\", xoperands); + } + if (operands[2] == const0_rtx) + return \"clr%.l %@\"; + return \"move%.l %2,%@\"; +}") + +;; Speed up pushing a single byte but leaving four bytes of space. + +(define_peephole + [(set (mem:QI (pre_dec:SI (reg:SI 15))) + (match_operand:QI 1 "general_operand" "dami")) + (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))] + "! reg_mentioned_p (stack_pointer_rtx, operands[1])" + "* +{ + rtx xoperands[4]; + + if (GET_CODE (operands[1]) == REG) + return \"move%.l %1,%-\"; + + xoperands[1] = operands[1]; + xoperands[2] + = gen_rtx (MEM, QImode, + gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, + gen_rtx (CONST_INT, VOIDmode, 3))); + xoperands[3] = stack_pointer_rtx; + output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands); + return \"\"; +}") + +(define_peephole + [(set (match_operand:SI 0 "register_operand" "=d") + (const_int 0)) + (set (strict_low_part (subreg:HI (match_dup 0) 0)) + (match_operand:HI 1 "general_operand" "rmn"))] + "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + if (operands[1] == const0_rtx + && (DATA_REG_P (operands[0]) + || GET_CODE (operands[0]) == MEM) + /* clr insns on 68000 read before writing. + This isn't so on the 68010, but we have no alternative for it. */ + && (TARGET_68020 + || !(GET_CODE (operands[0]) == MEM + && MEM_VOLATILE_P (operands[0])))) + return \"clr%.w %0\"; + } + return \"move%.w %1,%0\"; +}") + +;; dbCC peepholes +;; +;; Turns +;; loop: +;; [ ... ] +;; jCC label ; abnormal loop termination +;; dbra dN, loop ; normal loop termination +;; +;; Into +;; loop: +;; [ ... ] +;; dbCC dN, loop +;; jCC label +;; +;; Which moves the jCC condition outside the inner loop for free. +;; +(define_peephole + [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" + [(cc0) (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc))) + (parallel + [(set (pc) + (if_then_else + (ge (plus:HI (match_operand:HI 0 "register_operand" "+d") + (const_int -1)) + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (set (match_dup 0) + (plus:HI (match_dup 0) + (const_int -1)))])] + "DATA_REG_P (operands[0])" + "* +{ + CC_STATUS_INIT; + output_dbcc_and_branch (operands); + return \"\"; +}") + +(define_peephole + [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" + [(cc0) (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc))) + (parallel + [(set (pc) + (if_then_else + (ge (plus:SI (match_operand:SI 0 "register_operand" "+d") + (const_int -1)) + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (set (match_dup 0) + (plus:SI (match_dup 0) + (const_int -1)))])] + "DATA_REG_P (operands[0])" + "* +{ + CC_STATUS_INIT; + output_dbcc_and_branch (operands); + return \"\"; +}") + + +;; FPA multiply and add. +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=x,y,y") + (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y") + (match_operand:DF 2 "general_operand" "xH,y,y")) + (match_operand:DF 3 "general_operand" "xH,y,dmF")))] + "TARGET_FPA" + "@ + fpma%.d %1,%w2,%w3,%0 + fpma%.d %x1,%x2,%x3,%0 + fpma%.d %x1,%x2,%x3,%0") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=x,y,y") + (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y") + (match_operand:SF 2 "general_operand" "xH,y,ydmF")) + (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))] + "TARGET_FPA" + "@ + fpma%.s %1,%w2,%w3,%0 + fpma%.s %1,%2,%3,%0 + fpma%.s %1,%2,%3,%0") + +;; FPA Multiply and subtract +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=x,y,y") + (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y") + (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y") + (match_operand:DF 3 "general_operand" "x,y,rmF"))))] + "TARGET_FPA" + "@ + fpms%.d %3,%w2,%w1,%0 + fpms%.d %x3,%2,%x1,%0 + fpms%.d %x3,%2,%x1,%0") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=x,y,y") + (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF") + (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y") + (match_operand:SF 3 "general_operand" "x,y,yrmF"))))] + "TARGET_FPA" + "@ + fpms%.s %3,%w2,%w1,%0 + fpms%.s %3,%2,%1,%0 + fpms%.s %3,%2,%1,%0") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=x,y,y") + (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y") + (match_operand:DF 2 "general_operand" "x,y,rmF")) + (match_operand:DF 3 "general_operand" "xH,rmF,y")))] + "TARGET_FPA" + "@ + fpmr%.d %2,%w1,%w3,%0 + fpmr%.d %x2,%1,%x3,%0 + fpmr%.d %x2,%1,%x3,%0") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=x,y,y") + (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y") + (match_operand:SF 2 "general_operand" "x,y,yrmF")) + (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] + "TARGET_FPA" + "@ + fpmr%.s %2,%w1,%w3,%0 + fpmr%.s %x2,%1,%x3,%0 + fpmr%.s %x2,%1,%x3,%0") + +;; FPA Add and multiply +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=x,y,y") + (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y") + (match_operand:DF 2 "general_operand" "x,y,rmF")) + (match_operand:DF 3 "general_operand" "xH,rmF,y")))] + "TARGET_FPA" + "@ + fpam%.d %2,%w1,%w3,%0 + fpam%.d %x2,%1,%x3,%0 + fpam%.d %x2,%1,%x3,%0") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=x,y,y") + (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y") + (match_operand:SF 2 "general_operand" "x,y,yrmF")) + (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] + "TARGET_FPA" + "@ + fpam%.s %2,%w1,%w3,%0 + fpam%.s %x2,%1,%x3,%0 + fpam%.s %x2,%1,%x3,%0") + +;;FPA Subtract and multiply +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=x,y,y") + (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y") + (match_operand:DF 2 "general_operand" "x,y,rmF")) + (match_operand:DF 3 "general_operand" "xH,rmF,y")))] + "TARGET_FPA" + "@ + fpsm%.d %2,%w1,%w3,%0 + fpsm%.d %x2,%1,%x3,%0 + fpsm%.d %x2,%1,%x3,%0") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=x,y,y") + (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y") + (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y") + (match_operand:DF 3 "general_operand" "x,y,rmF"))))] + "TARGET_FPA" + "@ + fpsm%.d %3,%w2,%w1,%0 + fpsm%.d %x3,%2,%x1,%0 + fpsm%.d %x3,%2,%x1,%0") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=x,y,y") + (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y") + (match_operand:SF 2 "general_operand" "x,y,yrmF")) + (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] + "TARGET_FPA" + "@ + fpsm%.s %2,%w1,%w3,%0 + fpsm%.s %x2,%1,%x3,%0 + fpsm%.s %x2,%1,%x3,%0") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=x,y,y") + (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF") + (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y") + (match_operand:SF 3 "general_operand" "x,y,yrmF"))))] + "TARGET_FPA" + "@ + fpsm%.s %3,%w2,%w1,%0 + fpsm%.s %x3,%2,%x1,%0 + fpsm%.s %x3,%2,%x1,%0") + +(define_insn "tstxf" + [(set (cc0) + (match_operand:XF 0 "nonimmediate_operand" "fm"))] + "TARGET_68881" + "* +{ + cc_status.flags = CC_IN_68881; + return \"ftst%.x %0\"; +}") + + +(define_expand "cmpxf" + [(set (cc0) + (compare (match_operand:XF 0 "general_operand" "f,mG") + (match_operand:XF 1 "general_operand" "fmG,f")))] + "TARGET_68881" + " +{ + if (CONSTANT_P (operands[0])) + operands[0] = force_const_mem (XFmode, operands[0]); + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (XFmode, operands[1]); +}") + +(define_insn "" + [(set (cc0) + (compare (match_operand:XF 0 "nonimmediate_operand" "f,mG") + (match_operand:XF 1 "nonimmediate_operand" "fmG,f")))] + "TARGET_68881" + "* +{ + cc_status.flags = CC_IN_68881; +#ifdef SGS_CMP_ORDER + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return \"fcmp%.x %0,%1\"; + else + return \"fcmp%.x %0,%f1\"; + } + cc_status.flags |= CC_REVERSED; + return \"fcmp%.x %1,%f0\"; +#else + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return \"fcmp%.x %1,%0\"; + else + return \"fcmp%.x %f1,%0\"; + } + cc_status.flags |= CC_REVERSED; + return \"fcmp%.x %f0,%1\"; +#endif +}") + +(define_insn "extendsfxf2" + [(set (match_operand:XF 0 "general_operand" "=fm,f") + (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))] + "TARGET_68881" + "* +{ + if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) + { + if (REGNO (operands[0]) == REGNO (operands[1])) + { + /* Extending float to double in an fp-reg is a no-op. + NOTICE_UPDATE_CC has already assumed that the + cc will be set. So cancel what it did. */ + cc_status = cc_prev_status; + return \"\"; + } + return \"f%$move%.x %1,%0\"; + } + if (FP_REG_P (operands[0])) + return \"f%$move%.s %f1,%0\"; + return \"fmove%.x %f1,%0\"; +}") + + +(define_insn "extenddfxf2" + [(set (match_operand:XF 0 "general_operand" "=fm,f") + (float_extend:XF + (match_operand:DF 1 "general_operand" "f,m")))] + "TARGET_68881" + "* +{ + if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) + { + if (REGNO (operands[0]) == REGNO (operands[1])) + { + /* Extending float to double in an fp-reg is a no-op. + NOTICE_UPDATE_CC has already assumed that the + cc will be set. So cancel what it did. */ + cc_status = cc_prev_status; + return \"\"; + } + return \"fmove%.x %1,%0\"; + } + if (FP_REG_P (operands[0])) + return \"f%&move%.d %f1,%0\"; + return \"fmove%.x %f1,%0\"; +}") + +(define_insn "truncxfdf2" + [(set (match_operand:DF 0 "general_operand" "=m,!r") + (float_truncate:DF + (match_operand:XF 1 "general_operand" "f,f")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[0])) + { + output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return \"move%.l %+,%0\"; + } + return \"fmove%.d %f1,%0\"; +}") + +(define_insn "truncxfsf2" + [(set (match_operand:SF 0 "general_operand" "=dm") + (float_truncate:SF + (match_operand:XF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.s %f1,%0") + +(define_insn "floatsixf2" + [(set (match_operand:XF 0 "general_operand" "=f") + (float:XF (match_operand:SI 1 "general_operand" "dmi")))] + "TARGET_68881" + "fmove%.l %1,%0") + +(define_insn "floathixf2" + [(set (match_operand:XF 0 "general_operand" "=f") + (float:XF (match_operand:HI 1 "general_operand" "dmn")))] + "TARGET_68881" + "fmove%.w %1,%0") + +(define_insn "floatqixf2" + [(set (match_operand:XF 0 "general_operand" "=f") + (float:XF (match_operand:QI 1 "general_operand" "dmn")))] + "TARGET_68881" + "fmove%.b %1,%0") + +(define_insn "ftruncxf2" + [(set (match_operand:XF 0 "general_operand" "=f") + (fix:XF (match_operand:XF 1 "general_operand" "fFm")))] + "TARGET_68881" + "* +{ + if (FP_REG_P (operands[1])) + return \"fintrz%.x %f1,%0\"; + return \"fintrz%.x %f1,%0\"; +}") + +(define_insn "fixxfqi2" + [(set (match_operand:QI 0 "general_operand" "=dm") + (fix:QI (match_operand:XF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.b %1,%0") + +(define_insn "fixxfhi2" + [(set (match_operand:HI 0 "general_operand" "=dm") + (fix:HI (match_operand:XF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.w %1,%0") + +(define_insn "fixxfsi2" + [(set (match_operand:SI 0 "general_operand" "=dm") + (fix:SI (match_operand:XF 1 "general_operand" "f")))] + "TARGET_68881" + "fmove%.l %1,%0") + +(define_expand "addxf3" + [(set (match_operand:XF 0 "general_operand" "") + (plus:XF (match_operand:XF 1 "general_operand" "") + (match_operand:XF 2 "general_operand" "")))] + "TARGET_68881" + " +{ + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (XFmode, operands[1]); + if (CONSTANT_P (operands[2])) + operands[2] = force_const_mem (XFmode, operands[2]); +}") + +(define_insn "" + [(set (match_operand:XF 0 "general_operand" "=f") + (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0") + (match_operand:XF 2 "nonimmediate_operand" "fmG")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[2])) + return \"fadd%.x %2,%0\"; + return \"fadd%.x %f2,%0\"; +}") + +(define_expand "subxf3" + [(set (match_operand:XF 0 "general_operand" "") + (minus:XF (match_operand:XF 1 "general_operand" "") + (match_operand:XF 2 "general_operand" "")))] + "TARGET_68881" + " +{ + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (XFmode, operands[1]); + if (CONSTANT_P (operands[2])) + operands[2] = force_const_mem (XFmode, operands[2]); +}") + +(define_insn "" + [(set (match_operand:XF 0 "general_operand" "=f") + (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0") + (match_operand:XF 2 "nonimmediate_operand" "fmG")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[2])) + return \"fsub%.x %2,%0\"; + return \"fsub%.x %f2,%0\"; +}") + +(define_expand "mulxf3" + [(set (match_operand:XF 0 "general_operand" "") + (mult:XF (match_operand:XF 1 "general_operand" "") + (match_operand:XF 2 "general_operand" "")))] + "TARGET_68881" + " +{ + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (XFmode, operands[1]); + if (CONSTANT_P (operands[2])) + operands[2] = force_const_mem (XFmode, operands[2]); +}") + +(define_insn "" + [(set (match_operand:XF 0 "general_operand" "=f") + (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0") + (match_operand:XF 2 "nonimmediate_operand" "fmG")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[2])) + return \"fmul%.x %2,%0\"; + return \"fmul%.x %f2,%0\"; +}") + +(define_expand "divxf3" + [(set (match_operand:XF 0 "general_operand" "") + (div:XF (match_operand:XF 1 "general_operand" "") + (match_operand:XF 2 "general_operand" "")))] + "TARGET_68881" + " +{ + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (XFmode, operands[1]); + if (CONSTANT_P (operands[2])) + operands[2] = force_const_mem (XFmode, operands[2]); +}") + +(define_insn "" + [(set (match_operand:XF 0 "general_operand" "=f") + (div:XF (match_operand:XF 1 "nonimmediate_operand" "0") + (match_operand:XF 2 "nonimmediate_operand" "fmG")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[2])) + return \"fdiv%.x %2,%0\"; + return \"fdiv%.x %f2,%0\"; +}") + +(define_insn "negxf2" + [(set (match_operand:XF 0 "general_operand" "=f") + (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fmF")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return \"fneg%.x %1,%0\"; + return \"fneg%.x %f1,%0\"; +}") + +(define_insn "absxf2" + [(set (match_operand:XF 0 "general_operand" "=f") + (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fmF")))] + "TARGET_68881" + "* +{ + if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) + return \"fabs%.x %1,%0\"; + return \"fabs%.x %f1,%0\"; +}") + +(define_insn "sqrtxf2" + [(set (match_operand:XF 0 "general_operand" "=f") + (sqrt:XF (match_operand:DF 1 "nonimmediate_operand" "fm")))] + "TARGET_68881" + "* +{ + return \"fsqrt%.x %1,%0\"; +}") diff --git a/gnu/usr.bin/gcc2/arch/m68k/tconfig.h b/gnu/usr.bin/gcc2/arch/m68k/tconfig.h new file mode 100644 index 000000000000..4aaac859dc59 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/tconfig.h @@ -0,0 +1,50 @@ +/* Configuration for GNU C-compiler for Motorola 68000 family. + Copyright (C) 1987 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + + $Id: tconfig.h,v 1.1 1993/11/25 01:26:27 paulus Exp $ +*/ + + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +#define HOST_WORDS_BIG_ENDIAN + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ +#include "tm.h" + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +/* If compiled with GNU C, use the built-in alloca */ +#ifdef __GNUC__ +/* Use an arg in this macro because that's what some other + system does--let's avoid conflict. */ +#define alloca(x) __builtin_alloca(x) +#endif diff --git a/gnu/usr.bin/gcc2/arch/m68k/tm.h b/gnu/usr.bin/gcc2/arch/m68k/tm.h new file mode 100644 index 000000000000..aab990a223c7 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/m68k/tm.h @@ -0,0 +1,94 @@ +/* $Id: tm.h,v 1.1 1993/11/25 01:26:29 paulus Exp $ */ + +#include +#include "da30/m68k.h" + +/* See m68k.h. 7 means 68020 with 68881. */ + +#define TARGET_DEFAULT 7 + +/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified. + This will control the use of inline 68881 insns in certain macros. */ + +#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ -D__HAVE_FPU__} %{posix:-D_POSIX_SOURCE}" + +/* Names to predefine in the preprocessor for this target machine. */ + +#define CPP_PREDEFINES "-Dmc68000 -Dmc68020 -Dunix -D__BSD_NET2__ -D__NetBSD__ -Dda30" + +/* Specify -k to assembler for PIC code generation. */ + +#define ASM_SPEC "%{fpic:-k} %{fPIC:-k}" + +/* Support -static, -symbolic and -shared options (at least minimally). + Also use -dp when doing dynamic linking. Don't include a startup + file when linking a shared library. */ + +#define LINK_SPEC \ + "%{static:-Bstatic} %{shared:-Bshareable} %{symbolic:-Bsymbolic} \ + %{!static:%{!shared:-dp}}" + +#define STARTFILE_SPEC \ + "%{!shared:%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}" + +/* No more libg.a; no libraries if making shared object */ + +#define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" + +/* Make gcc agree with */ + +#define SIZE_TYPE "unsigned int" +#define PTRDIFF_TYPE "int" +#undef WCHAR_TYPE +#define WCHAR_TYPE "short unsigned int" +#define WCHAR_UNSIGNED 1 +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 16 + +/* NetBSD does have atexit. */ + +#define HAVE_ATEXIT + +/* Every structure or union's size must be a multiple of 2 bytes. */ + +#define STRUCTURE_SIZE_BOUNDARY 16 + +/* This is BSD, so it wants DBX format. */ + +#define DBX_DEBUGGING_INFO + +/* Do not break .stabs pseudos into continuations. */ + +#define DBX_CONTIN_LENGTH 0 + +/* This is the char to use for continuation (in case we need to turn + continuation back on). */ + +#define DBX_CONTIN_CHAR '?' + +/* Don't use the `xsfoo;' construct in DBX output; this system + doesn't support it. */ + +#define DBX_NO_XREFS + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 + +/* + * Some imports from svr4.h in support of shared libraries. + * Currently, we need the DECLARE_OBJECT_SIZE stuff. + */ + +#define SIZE_ASM_OP ".size" + +#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ + do { \ + if (!flag_inhibit_size_directive) \ + { \ + fprintf (FILE, "\t%s ", SIZE_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (decl))); \ + } \ + ASM_OUTPUT_LABEL(FILE, NAME); \ + } while (0)