Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

these have been renamed

Browse Source
This commit is contained in:
cgd 1995-12-20 00:11:15 +00:00
parent 1ebd4658b5
commit c87e761abf
2 changed files with 0 additions and 526 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

291
sys/arch/alpha/tc/asic.c
View File

@ -1,291 +0,0 @@
/* $NetBSD: asic.c,v 1.5 1995/08/03 00:52:00 cgd Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Keith Bostic, Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <machine/autoconf.h>
#include <machine/pte.h>
#include <machine/rpb.h>
#include <alpha/tc/tc.h>
#include <alpha/tc/asic.h>
struct asic_softc {
struct device sc_dv;
struct abus sc_bus;
caddr_t sc_base;
};
/* Definition of the driver for autoconfig. */
int asicmatch __P((struct device *, void *, void *));
void asicattach __P((struct device *, struct device *, void *));
int asicprint(void *, char *);
struct cfdriver asiccd =
{ NULL, "asic", asicmatch, asicattach, DV_DULL, sizeof(struct asic_softc) };
void asic_intr_establish __P((struct confargs *, int (*)(void *), void *));
void asic_intr_disestablish __P((struct confargs *));
caddr_t asic_cvtaddr __P((struct confargs *));
int asic_matchname __P((struct confargs *, char *));
int asic_intr __P((void *));
int asic_intrnull __P((void *));
struct asic_slot {
struct confargs as_ca;
u_int64_t as_bits;
intr_handler_t as_handler;
void *as_val;
} asic_slots[ASIC_MAX_NSLOTS] = {
{ { "lance", /* XXX */ 0, 0x000c0000, },
ASIC_INTR_LANCE, asic_intrnull, (void *)(long)ASIC_SLOT_LANCE, },
{ { "scc", /* XXX */ 1, 0x00100000, },
ASIC_INTR_SCC_0, asic_intrnull, (void *)(long)ASIC_SLOT_SCC0, },
{ { "scc", /* XXX */ 2, 0x00180000, },
ASIC_INTR_SCC_1, asic_intrnull, (void *)(long)ASIC_SLOT_SCC1, },
{ { "dallas_rtc", /* XXX */ 3, 0x00200000, },
0, asic_intrnull, (void *)(long)ASIC_SLOT_RTC, },
{ { "AMD79c30", /* XXX */ 4, 0x00240000, },
0 /* XXX */, asic_intrnull, (void *)(long)ASIC_SLOT_ISDN, },
};
caddr_t asic_base; /* XXX XXX XXX */
int
asicmatch(parent, cfdata, aux)
struct device *parent;
void *cfdata;
void *aux;
{
struct cfdata *cf = cfdata;
struct confargs *ca = aux;
/* It can only occur on the turbochannel, anyway. */
if (ca->ca_bus->ab_type != BUS_TC)
return (0);
/* Make sure that we're looking for this type of device. */
if (!BUS_MATCHNAME(ca, "IOCTL "))
return (0);
/* See if the unit number is valid. */
switch (hwrpb->rpb_type) {
#if defined(DEC_3000_500) || defined(DEC_3000_300)
case ST_DEC_3000_500:
case ST_DEC_3000_300:
if (cf->cf_unit > 0)
return (0);
break;
#endif
default:
return (0);
}
return (1);
}
void
asicattach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct asic_softc *sc = (struct asic_softc *)self;
struct confargs *ca = aux;
struct confargs *nca;
int i;
extern int cputype;
sc->sc_base = BUS_CVTADDR(ca);
asic_base = sc->sc_base; /* XXX XXX XXX */
sc->sc_bus.ab_dv = (struct device *)sc;
sc->sc_bus.ab_type = BUS_ASIC;
sc->sc_bus.ab_intr_establish = asic_intr_establish;
sc->sc_bus.ab_intr_disestablish = asic_intr_disestablish;
sc->sc_bus.ab_cvtaddr = asic_cvtaddr;
sc->sc_bus.ab_matchname = asic_matchname;
BUS_INTR_ESTABLISH(ca, asic_intr, sc);
#ifdef DEC_3000_300
if (cputype == ST_DEC_3000_300) {
*(volatile u_int *)ASIC_REG_CSR(sc->sc_base) |=
ASIC_CSR_FASTMODE;
wbflush();
printf(": slow mode\n");
} else
#endif
printf(": fast mode\n");
/* Try to configure each CPU-internal device */
for (i = 0; i < ASIC_MAX_NSLOTS; i++) {
nca = &asic_slots[i].as_ca;
nca->ca_bus = &sc->sc_bus;
/* Tell the autoconfig machinery we've found the hardware. */
config_found(self, nca, asicprint);
}
}
int
asicprint(aux, pnp)
void *aux;
char *pnp;
{
struct confargs *ca = aux;
if (pnp)
printf("%s at %s", ca->ca_name, pnp);
printf(" offset 0x%lx", ca->ca_offset);
return (UNCONF);
}
void
asic_intr_establish(ca, handler, val)
struct confargs *ca;
int (*handler) __P((void *));
void *val;
{
#ifdef DIAGNOSTIC
if (ca->ca_slot == ASIC_SLOT_RTC)
panic("setting clock interrupt incorrectly");
#endif
/* XXX SHOULD NOT BE THIS LITERAL */
if (asic_slots[ca->ca_slot].as_handler != asic_intrnull)
panic("asic_intr_establish: slot %d twice", ca->ca_slot);
asic_slots[ca->ca_slot].as_handler = handler;
asic_slots[ca->ca_slot].as_val = val;
}
void
asic_intr_disestablish(ca)
struct confargs *ca;
{
if (ca->ca_slot == ASIC_SLOT_RTC)
panic("asic_intr_disestablish: can'd do clock interrupt");
/* XXX SHOULD NOT BE THIS LITERAL */
if (asic_slots[ca->ca_slot].as_handler == asic_intrnull)
panic("asic_intr_disestablish: slot %d missing intr",
ca->ca_slot);
asic_slots[ca->ca_slot].as_handler = asic_intrnull;
asic_slots[ca->ca_slot].as_val = (void *)(long)ca->ca_slot;
}
caddr_t
asic_cvtaddr(ca)
struct confargs *ca;
{
return
(((struct asic_softc *)ca->ca_bus->ab_dv)->sc_base + ca->ca_offset);
}
int
asic_matchname(ca, name)
struct confargs *ca;
char *name;
{
return (strcmp(name, ca->ca_name) == 0);
}
/*
* asic_intr --
* ASIC interrupt handler.
*/
int
asic_intr(val)
void *val;
{
register struct asic_softc *sc = val;
register int i, ifound;
int gifound;
u_int32_t sir, junk;
volatile u_int32_t *sirp, *junkp;
sirp = (volatile u_int32_t *)ASIC_REG_INTR(sc->sc_base);
gifound = 0;
do {
ifound = 0;
wbflush();
MAGIC_READ;
wbflush();
sir = *sirp;
for (i = 0; i < ASIC_MAX_NSLOTS; i++)
if (sir & asic_slots[i].as_bits) {
(void)(*asic_slots[i].as_handler)
(asic_slots[i].as_val);
ifound = 1;
}
gifound |= ifound;
} while (ifound);
return (gifound);
}
int
asic_intrnull(val)
void *val;
{
panic("uncaught IOCTL ASIC intr for slot %ld\n", (long)val);
}
#ifdef DEC_3000_500
/*
* flamingo_set_leds --
* Set the LEDs on the 400/500/600/800's.
*/
void
flamingo_set_leds(value)
u_int value;
{
register struct asic_softc *sc = asiccd.cd_devs[0];
/*
* The 500's use the 7th bit of the SSR for FEPROM
* selection.
*/
*(volatile u_int *)ASIC_REG_CSR(sc->sc_base) &= ~0x7f;
*(volatile u_int *)ASIC_REG_CSR(sc->sc_base) |= value & 0x7f;
wbflush();
DELAY(10000);
}
#endif

235
sys/arch/alpha/tc/asic.h
View File

@ -1,235 +0,0 @@
/* $NetBSD: asic.h,v 1.2 1995/03/28 18:14:22 jtc Exp $ */
/*
* Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*-
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* The Mach Operating System project at Carnegie-Mellon University,
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)asic.h 8.1 (Berkeley) 6/10/93
*/
/*
* Slot definitions
*/
#define ASIC_SLOT_0_START 0x000000
#define ASIC_SLOT_1_START 0x040000
#define ASIC_SLOT_2_START 0x080000
#define ASIC_SLOT_3_START 0x0c0000
#define ASIC_SLOT_4_START 0x100000
#define ASIC_SLOT_5_START 0x140000
#define ASIC_SLOT_6_START 0x180000
#define ASIC_SLOT_7_START 0x1c0000
#define ASIC_SLOT_8_START 0x200000
#define ASIC_SLOT_9_START 0x240000
#define ASIC_SLOT_10_START 0x280000
#define ASIC_SLOT_11_START 0x2c0000
#define ASIC_SLOT_12_START 0x300000
#define ASIC_SLOT_13_START 0x340000
#define ASIC_SLOT_14_START 0x380000
#define ASIC_SLOT_15_START 0x3c0000
#define ASIC_SLOTS_END 0x3fffff
/*
* Register offsets (slot 1)
*/
#define ASIC_SCSI_DMAPTR ASIC_SLOT_1_START+0x000
#define ASIC_SCSI_NEXTPTR ASIC_SLOT_1_START+0x010
#define ASIC_LANCE_DMAPTR ASIC_SLOT_1_START+0x020
#define ASIC_SCC_T1_DMAPTR ASIC_SLOT_1_START+0x030
#define ASIC_SCC_R1_DMAPTR ASIC_SLOT_1_START+0x040
#define ASIC_SCC_T2_DMAPTR ASIC_SLOT_1_START+0x050
#define ASIC_SCC_R2_DMAPTR ASIC_SLOT_1_START+0x060
#define ASIC_FLOPPY_DMAPTR ASIC_SLOT_1_START+0x070
#define ASIC_ISDN_X_DMAPTR ASIC_SLOT_1_START+0x080
#define ASIC_ISDN_X_NEXTPTR ASIC_SLOT_1_START+0x090
#define ASIC_ISDN_R_DMAPTR ASIC_SLOT_1_START+0x0a0
#define ASIC_ISDN_R_NEXTPTR ASIC_SLOT_1_START+0x0b0
#define ASIC_BUFF0 ASIC_SLOT_1_START+0x0c0
#define ASIC_BUFF1 ASIC_SLOT_1_START+0x0d0
#define ASIC_BUFF2 ASIC_SLOT_1_START+0x0e0
#define ASIC_BUFF3 ASIC_SLOT_1_START+0x0f0
#define ASIC_CSR ASIC_SLOT_1_START+0x100
#define ASIC_INTR ASIC_SLOT_1_START+0x110
#define ASIC_IMSK ASIC_SLOT_1_START+0x120
#define ASIC_CURADDR ASIC_SLOT_1_START+0x130
#define ASIC_ISDN_X_DATA ASIC_SLOT_1_START+0x140
#define ASIC_ISDN_R_DATA ASIC_SLOT_1_START+0x150
#define ASIC_LANCE_DECODE ASIC_SLOT_1_START+0x160
#define ASIC_SCSI_DECODE ASIC_SLOT_1_START+0x170
#define ASIC_SCC0_DECODE ASIC_SLOT_1_START+0x180
#define ASIC_SCC1_DECODE ASIC_SLOT_1_START+0x190
#define ASIC_FLOPPY_DECODE ASIC_SLOT_1_START+0x1a0
#define ASIC_SCSI_SCR ASIC_SLOT_1_START+0x1b0
#define ASIC_SCSI_SDR0 ASIC_SLOT_1_START+0x1c0
#define ASIC_SCSI_SDR1 ASIC_SLOT_1_START+0x1d0
/* System Status and control Register (SSR). */
#define ASIC_CSR_DMAEN_T1 0x80000000 /* rw */
#define ASIC_CSR_DMAEN_R1 0x40000000 /* rw */
#define ASIC_CSR_DMAEN_T2 0x20000000 /* rw */
#define ASIC_CSR_DMAEN_R2 0x10000000 /* rw */
#define ASIC_CSR_FASTMODE 0x08000000 /* rw */
#define ASIC_CSR_xxx 0x07800000 /* unused/reserved */
#define ASIC_CSR_FLOPPY_DIR 0x00400000 /* rw */
#define ASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw */
#define ASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */
#define ASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */
#define ASIC_CSR_SCSI_DIR 0x00040000 /* rw */
#define ASIC_CSR_DMAEN_SCSI 0x00020000 /* rw */
#define ASIC_CSR_DMAEN_LANCE 0x00010000 /* rw */
/* low 16 bits are rw gp outputs */
/* System Interrupt Register (and Interrupt Mask Register). */
#define ASIC_INTR_T1_PAGE_END 0x80000000 /* rz */
#define ASIC_INTR_T1_READ_E 0x40000000 /* rz */
#define ASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */
#define ASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */
#define ASIC_INTR_T2_PAGE_END 0x08000000 /* rz */
#define ASIC_INTR_T2_READ_E 0x04000000 /* rz */
#define ASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */
#define ASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */
#define ASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz */
#define ASIC_INTR_ISDN_PTR_LOAD 0x00400000 /* rz */
#define ASIC_INTR_ISDN_OVRUN 0x00200000 /* rz */
#define ASIC_INTR_ISDN_READ_E 0x00100000 /* rz */
#define ASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz */
#define ASIC_INTR_SCSI_OVRUN 0x00040000 /* rz */
#define ASIC_INTR_SCSI_READ_E 0x00020000 /* rz */
#define ASIC_INTR_LANCE_READ_E 0x00010000 /* rz */
#define ASIC_INTR_ISDN 0x00002000 /* ro */
#define ASIC_INTR_SEC_CON 0x00000200 /* ro */
#define ASIC_INTR_LANCE 0x00000100 /* ro */
#define ASIC_INTR_SCC_1 0x00000080 /* ro */
#define ASIC_INTR_SCC_0 0x00000040 /* ro */
#define ASIC_INTR_ALT_CON 0x00000008 /* ro */
/* DMA pointer registers (SCSI, Comm, ...) */
#define ASIC_DMAPTR_MASK 0xffffffe0
#define ASIC_DMAPTR_SHIFT 5
# define ASIC_DMAPTR_SET(reg,val) \
(reg) = (((val)<<ASIC_DMAPTR_SHIFT)&ASIC_DMAPTR_MASK)
# define ASIC_DMAPTR_GET(reg,val) \
(val) = (((reg)&ASIC_DMAPTR_MASK)>>ASIC_DMAPTR_SHIFT)
#define ASIC_DMA_ADDR(p) (((unsigned)p) << (5-2))
/* For the LANCE DMA pointer register initialization the above suffices */
/* More SCSI DMA registers */
#define ASIC_SCR_STATUS 0x00000004
#define ASIC_SCR_WORD 0x00000003
/* Various Decode registers */
#define ASIC_DECODE_HW_ADDRESS 0x000003f0
#define ASIC_DECODE_CHIP_SELECT 0x0000000f
/*
* Asic register addresses at offset from base.
*/
#define ASIC_REG_SCSI_DMAPTR(base) ((base) + ASIC_SCSI_DMAPTR)
#define ASIC_REG_SCSI_DMANPTR(base) ((base) + ASIC_SCSI_NEXTPTR)
#define ASIC_REG_LANCE_DMAPTR(base) ((base) + ASIC_LANCE_DMAPTR)
#define ASIC_REG_SCC_T1_DMAPTR(base) ((base) + ASIC_SCC_T1_DMAPTR)
#define ASIC_REG_SCC_R1_DMAPTR(base) ((base) + ASIC_SCC_R1_DMAPTR)
#define ASIC_REG_SCC_T2_DMAPTR(base) ((base) + ASIC_SCC_T2_DMAPTR)
#define ASIC_REG_SCC_R2_DMAPTR(base) ((base) + ASIC_SCC_R2_DMAPTR)
#define ASIC_REG_FLOPPY_DMAPTR(base) ((base) + ASIC_FLOPPY_DMAPTR)
#define ASIC_REG_ISDN_X_DMAPTR(base) ((base) + ASIC_ISDN_X_DMAPTR)
#define ASIC_REG_ISDN_X_NEXTPTR(base) ((base) + ASIC_ISDN_X_NEXTPTR)
#define ASIC_REG_ISDN_R_DMAPTR(base) ((base) + ASIC_ISDN_R_DMAPTR)
#define ASIC_REG_ISDN_R_NEXTPTR(base) ((base) + ASIC_ISDN_R_NEXTPTR)
#define ASIC_REG_BUFF0(base) ((base) + ASIC_BUFF0)
#define ASIC_REG_BUFF1(base) ((base) + ASIC_BUFF1)
#define ASIC_REG_BUFF2(base) ((base) + ASIC_BUFF2)
#define ASIC_REG_BUFF3(base) ((base) + ASIC_BUFF3)
#define ASIC_REG_CSR(base) ((base) + ASIC_CSR)
#define ASIC_REG_INTR(base) ((base) + ASIC_INTR)
#define ASIC_REG_IMSK(base) ((base) + ASIC_IMSK)
#define ASIC_REG_CURADDR(base) ((base) + ASIC_CURADDR)
#define ASIC_REG_ISDN_X_DATA(base) ((base) + ASIC_ISDN_X_DATA)
#define ASIC_REG_ISDN_R_DATA(base) ((base) + ASIC_ISDN_R_DATA)
#define ASIC_REG_LANCE_DECODE(base) ((base) + ASIC_LANCE_DECODE)
#define ASIC_REG_SCSI_DECODE(base) ((base) + ASIC_SCSI_DECODE)
#define ASIC_REG_SCC0_DECODE(base) ((base) + ASIC_SCC0_DECODE)
#define ASIC_REG_SCC1_DECODE(base) ((base) + ASIC_SCC1_DECODE)
#define ASIC_REG_FLOPPY_DECODE(base) ((base) + ASIC_FLOPPY_DECODE)
#define ASIC_REG_SCSI_SCR(base) ((base) + ASIC_SCSI_SCR)
#define ASIC_REG_SCSI_SDR0(base) ((base) + ASIC_SCSI_SDR0)
#define ASIC_REG_SCSI_SDR1(base) ((base) + ASIC_SCSI_SDR1)
/*
* And slot assignments.
*/
#define ASIC_SYS_ETHER_ADDRESS(base) ((base) + ASIC_SLOT_2_START)
#define ASIC_SYS_LANCE(base) ((base) + ASIC_SLOT_3_START)
#ifdef _KERNEL
#define ASIC_SLOT_LANCE 0 /* ASIC slots for interrupt lookup. */
#define ASIC_SLOT_SCC0 1
#define ASIC_SLOT_SCC1 2
#define ASIC_SLOT_RTC 3
#define ASIC_SLOT_ISDN 4
#define ASIC_MAX_NSLOTS 5 /* clock + 2 scc + lance + isdn */
caddr_t asic_base;
#endif