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Only use CPACR register for ARM11 and CORTEX cores.

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Add VFP ids for other CORTEX CPUs.
This commit is contained in:
matt 2012-09-22 19:45:53 +00:00
parent f370af7faf
commit c872068c8a
3 changed files with 51 additions and 25 deletions
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17
sys/arch/arm/include/armreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: armreg.h,v 1.67 2012/09/22 01:44:12 matt Exp $ */
/* $NetBSD: armreg.h,v 1.68 2012/09/22 19:45:53 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@ -321,6 +321,15 @@
#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
/* ARMv6/ARMv7 Co-Processor Access Control Register (CP15, 0, c1, c0, 2) */
#define CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */
#define CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */
#define CPACR_CPn(n) (3 << (2*n))
#define CPACR_NOACCESS 0 /* reset value */
#define CPACR_PRIVED 1 /* Privileged mode access */
#define CPACR_RESERVED 2
#define CPACR_ALL 3 /* Privileged and User mode access */
/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */
#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
@ -570,8 +579,10 @@ ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */
ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
/* c1 registers */
ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Register */
ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Register */
ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
/* c2 registers */
ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */

10
sys/arch/arm/include/vfpreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: vfpreg.h,v 1.5 2012/09/22 01:44:12 matt Exp $ */
/* $NetBSD: vfpreg.h,v 1.6 2012/09/22 19:45:53 matt Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@ -45,6 +45,9 @@
#define VFP_FPSID_ARCH_MSK 0x000f0000 /* Architecture */
#define VFP_FPSID_ARCH_V1 0x00000000 /* Arch VFPv1 */
#define VFP_FPSID_ARCH_V2 0x00010000 /* Arch VFPv2 */
#define VFP_FPSID_ARCH_V3_2 0x00020000 /* Arch VFPv3 (subarch v2) */
#define VFP_FPSID_ARCH_V3 0x00030000 /* Arch VFPv3 (no subarch) */
#define VFP_FPSID_ARCH_V3_3 0x00040000 /* Arch VFPv3 (subarch v3) */
#define VFP_FPSID_PART_MSK 0x0000ff00 /* Part number */
#define VFP_FPSID_PART_VFP10 0x00001000 /* VFP10 */
#define VFP_FPSID_PART_VFP11 0x00002000 /* VFP11 */
@ -56,7 +59,10 @@
#define FPU_VFP10_ARM10E 0x410001a0 /* Really a VFPv2 part */
#define FPU_VFP11_ARM11 0x410120b0
#define FPU_VFP30_CORTEXA9 0x41033090
#define FPU_VFP_CORTEXA5 0x41023050
#define FPU_VFP_CORTEXA7 0x41023070
#define FPU_VFP_CORTEXA8 0x410330c0
#define FPU_VFP_CORTEXA9 0x41033090
#define VFP_FPEXC_EX 0x80000000 /* Exception status bit */
#define VFP_FPEXC_EN 0x40000000 /* VFP Enable bit */

49
sys/arch/arm/vfp/vfp_init.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: vfp_init.c,v 1.6 2012/09/22 01:44:12 matt Exp $ */
/* $NetBSD: vfp_init.c,v 1.7 2012/09/22 19:45:54 matt Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@ -216,29 +216,35 @@ vfp_attach(void)
{
struct cpu_info * const ci = curcpu();
const char *model = NULL;
void *uh;
uh = install_coproc_handler(VFP_COPROC, vfp_test);
undefined_test = 0;
bool vfp_p = false;
#ifdef FPU_VFP
uint32_t cpacr = armreg_cpacr_read();
cpacr &= ~__BITS(21,20);
cpacr &= ~__BITS(23,22);
if (CPU_ID_ARM11_P(curcpu()->ci_arm_cpuid)
|| CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid)) {
const uint32_t cpacr_vfp = CPACR_CPn(VFP_COPROC);
const uint32_t cpacr_vfp2 = CPACR_CPn(VFP_COPROC2);
cpacr |= __SHIFTIN(1, __BITS(21,20));
cpacr |= __SHIFTIN(1, __BITS(23,22));
armreg_cpacr_write(cpacr);
cpacr = armreg_cpacr_read();
if ((cpacr & __BITS(23,22)) == 0) {
aprint_normal_dev(ci->ci_dev, "NEON not present\n");
}
if ((cpacr & __BITS(21,20)) == 0) {
aprint_normal_dev(ci->ci_dev, "VFP not present\n");
/*
* We first need to enable access to the coprocessors.
*/
uint32_t cpacr = armreg_cpacr_read();
cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp);
cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp2);
armreg_cpacr_write(cpacr);
/*
* If we could enable them, then they exist.
*/
cpacr = armreg_cpacr_read();
vfp_p = __SHIFTOUT(cpacr, cpacr_vfp2) != CPACR_NOACCESS
|| __SHIFTOUT(cpacr, cpacr_vfp) != CPACR_NOACCESS;
}
#endif
void *uh = install_coproc_handler(VFP_COPROC, vfp_test);
undefined_test = 0;
const uint32_t fpsid = read_fpsid();
remove_coproc_handler(uh);
@ -258,8 +264,11 @@ vfp_attach(void)
case FPU_VFP11_ARM11:
model = "VFP11";
break;
case FPU_VFP30_CORTEXA9:
model = "NEON MPE w/ VFP 3.0";
case FPU_VFP_CORTEXA5:
case FPU_VFP_CORTEXA7:
case FPU_VFP_CORTEXA8:
case FPU_VFP_CORTEXA9:
model = "NEON MPE (VFP 3.0+)";
break;
default:
aprint_normal_dev(ci->ci_dev, "unrecognized VFP version %x\n",