Finish the switch to the softintr(9) framework.
To make this work, we now have to use separate handler lists for hardware and software interrupts as the soft interrupt handlers do not return an `interrupt handled' status. Thanks to Matt Fredette for providing an initial set of patches on port-sparc.
This commit is contained in:
pk
parent
21bf723223
commit
c822c6bd84
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@ -1,4 +1,4 @@
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/* $NetBSD: audioamd.c,v 1.13 2002/10/15 13:49:52 jdc Exp $ */
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/* $NetBSD: audioamd.c,v 1.14 2002/12/09 16:11:50 pk Exp $ */
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/* NetBSD: am7930_sparc.c,v 1.44 1999/03/14 22:29:00 jonathan Exp */
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/*
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@ -64,20 +64,9 @@
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/* interrupt interfaces */
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#ifdef AUDIO_C_HANDLER
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int am7930hwintr __P((void *));
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#if defined(SUN4M)
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#define AUDIO_SET_SWINTR do { \
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if (CPU_ISSUN4M) \
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raise(0, 4); \
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else \
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ienab_bis(IE_L4); \
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} while(0);
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#else
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#define AUDIO_SET_SWINTR ienab_bis(IE_L4)
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#endif /* defined(SUN4M) */
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#else
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struct auio *auiop;
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#endif /* AUDIO_C_HANDLER */
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int am7930swintr __P((void *));
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struct auio *auiop;
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void am7930swintr __P((void *));
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/*
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* interrupt-handler status
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@ -102,6 +91,7 @@ struct audioamd_softc {
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/* sc_au is special in that the hardware interrupt handler uses it */
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struct auio sc_au; /* recv and xmit buffers, etc */
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#define sc_intrcnt sc_au.au_intrcnt /* statistics */
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void *sc_sicookie; /* softintr(9) cookie */
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};
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void audioamd_mainbus_attach __P((struct device *,
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@ -306,8 +296,6 @@ audioamd_attach(sc, pri)
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int pri;
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{
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printf(" softpri %d\n", PIL_AUSOFT);
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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@ -315,8 +303,8 @@ audioamd_attach(sc, pri)
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am7930_init(&sc->sc_am7930, AUDIOAMD_POLL_MODE);
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#ifndef AUDIO_C_HANDLER
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auiop = &sc->sc_au;
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#ifndef AUDIO_C_HANDLER
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(void)bus_intr_establish(sc->sc_bt, pri, IPL_AUDIO,
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BUS_INTR_ESTABLISH_FASTTRAP,
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(int (*) __P((void *)))amd7930_trap, NULL);
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@ -324,9 +312,16 @@ audioamd_attach(sc, pri)
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(void)bus_intr_establish(sc->sc_bt, pri, IPL_AUDIO, 0,
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am7930hwintr, sc);
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#endif
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(void)bus_intr_establish(sc->sc_bt, PIL_AUSOFT, IPL_AUDIO,
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BUS_INTR_ESTABLISH_SOFTINTR,
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am7930swintr, sc);
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sc->sc_sicookie = softintr_establish(IPL_SOFTAUDIO, am7930swintr, sc);
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if (sc->sc_sicookie == NULL) {
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printf("\n%s: cannot establish software interrupt\n",
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sc->sc_am7930.sc_dev.dv_xname);
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return;
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}
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printf(" softpri %d\n", IPL_SOFTAUDIO);
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evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
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sc->sc_am7930.sc_dev.dv_xname, "intr");
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@ -436,6 +431,9 @@ am7930hwintr(v)
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/* clear interrupt */
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k = audioamd_codec_dread(sc, AM7930_DREG_IR);
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if ((k & (AM7930_IR_DTTHRSH|AM7930_IR_DRTHRSH|AM7930_IR_DSRI|
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AM7930_IR_DERI|AM7930_IR_BBUFF)) == 0)
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return (0);
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/* receive incoming data */
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d = au->au_rdata;
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@ -445,7 +443,7 @@ am7930hwintr(v)
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au->au_rdata++;
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if (d == e) {
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DPRINTFN(1, ("am7930hwintr: swintr(r) requested"));
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AUDIO_SET_SWINTR;
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softintr_schedule(sc->sc_sicookie);
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}
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}
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@ -457,7 +455,7 @@ am7930hwintr(v)
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au->au_pdata++;
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if (d == e) {
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DPRINTFN(1, ("am7930hwintr: swintr(p) requested"));
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AUDIO_SET_SWINTR;
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softintr_schedule(sc->sc_sicookie);
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}
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}
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@ -466,13 +464,13 @@ am7930hwintr(v)
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}
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#endif /* AUDIO_C_HANDLER */
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int
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void
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am7930swintr(sc0)
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void *sc0;
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{
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struct audioamd_softc *sc = sc0;
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struct auio *au;
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int s, ret = 0;
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int s;
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DPRINTFN(1, ("audiointr: sc=%p\n", sc););
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@ -480,17 +478,14 @@ am7930swintr(sc0)
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s = splaudio();
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if (au->au_rdata > au->au_rend && sc->sc_rintr != NULL) {
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splx(s);
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ret = 1;
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(*sc->sc_rintr)(sc->sc_rarg);
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s = splaudio();
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}
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if (au->au_pdata > au->au_pend && sc->sc_pintr != NULL) {
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splx(s);
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ret = 1;
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(*sc->sc_pintr)(sc->sc_parg);
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} else
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splx(s);
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return (ret);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: fd.c,v 1.96 2002/11/01 11:31:53 mrg Exp $ */
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/* $NetBSD: fd.c,v 1.97 2002/12/09 16:11:50 pk Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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@ -174,6 +174,8 @@ struct fdc_softc {
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#define sc_nstat sc_io.fdcio_nstat
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#define sc_status sc_io.fdcio_status
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#define sc_intrcnt sc_io.fdcio_intrcnt
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void *sc_sicookie; /* softintr(9) cookie */
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};
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extern struct fdcio *fdciop; /* I/O descriptor used in fdintr.s */
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@ -302,7 +304,7 @@ void fdctimeout __P((void *arg));
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void fdcpseudointr __P((void *arg));
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int fdc_c_hwintr __P((void *));
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void fdchwintr __P((void));
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int fdcswintr __P((void *));
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void fdcswintr __P((void *));
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int fdcstate __P((struct fdc_softc *));
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void fdcretry __P((struct fdc_softc *fdc));
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void fdfinish __P((struct fd_softc *fd, struct buf *bp));
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@ -318,23 +320,6 @@ static void establish_chip_type __P((
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bus_space_handle_t));
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#if PIL_FDSOFT == 4
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#define IE_FDSOFT IE_L4
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#else
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#error 4
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#endif
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#if defined(SUN4M)
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#define FD_SET_SWINTR do { \
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if (CPU_ISSUN4M) \
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raise(0, PIL_FDSOFT); \
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else \
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ienab_bis(IE_L4); \
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} while(0)
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#else
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#define FD_SET_SWINTR ienab_bis(IE_FDSOFT)
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#endif /* defined(SUN4M) */
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#define OBP_FDNAME (CPU_ISSUN4M ? "SUNW,fdtwo" : "fd")
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int
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code = '2';
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}
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printf(" softpri %d: chip 8207%c\n", PIL_FDSOFT, code);
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/*
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* Configure controller; enable FIFO, Implied seek, no POLL mode?.
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* Note: CFG_EFIFO is active-low, initial threshold value: 8
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@ -651,13 +634,13 @@ fdcattach(fdc, pri)
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}
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}
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if (bus_intr_establish(fdc->sc_bustag, PIL_FDSOFT, IPL_BIO,
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BUS_INTR_ESTABLISH_SOFTINTR,
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fdcswintr, fdc) == NULL) {
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printf("%s: cannot register interrupt handler\n",
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fdc->sc_sicookie = softintr_establish(IPL_SOFTFDC, fdcswintr, fdc);
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if (fdc->sc_sicookie == NULL) {
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printf("\n%s: cannot register soft interrupt handler\n",
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fdc->sc_dev.dv_xname);
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return (-1);
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}
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printf(" softpri %d: chip 8207%c\n", IPL_SOFTFDC, code);
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evcnt_attach_dynamic(&fdc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
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fdc->sc_dev.dv_xname, "intr");
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@ -1320,7 +1303,7 @@ fdc_c_hwintr(arg)
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fdc->sc_istatus = FDC_ISTATUS_ERROR;
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else
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fdc->sc_istatus = FDC_ISTATUS_DONE;
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FD_SET_SWINTR;
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softintr_schedule(fdc->sc_sicookie);
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return (1);
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case FDC_ITASK_DMA:
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/* Proceed with pseudo-dma below */
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default:
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printf("fdc: stray hard interrupt: itask=%d\n", fdc->sc_itask);
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fdc->sc_istatus = FDC_ISTATUS_SPURIOUS;
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FD_SET_SWINTR;
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softintr_schedule(fdc->sc_sicookie);
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return (1);
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}
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@ -1347,7 +1330,7 @@ fdc_c_hwintr(arg)
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if ((msr & NE7_NDM) == 0) {
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fdcresult(fdc);
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fdc->sc_istatus = FDC_ISTATUS_DONE;
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FD_SET_SWINTR;
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softintr_schedule(fdc->sc_sicookie);
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#ifdef FD_DEBUG
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if (fdc_debug > 1)
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printf("fdc: overrun: tc = %d\n", fdc->sc_tc);
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@ -1368,14 +1351,14 @@ fdc_c_hwintr(arg)
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fdc->sc_istatus = FDC_ISTATUS_DONE;
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FTC_FLIP;
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fdcresult(fdc);
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FD_SET_SWINTR;
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softintr_schedule(fdc->sc_sicookie);
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break;
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}
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}
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return (1);
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}
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int
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void
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fdcswintr(arg)
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void *arg;
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{
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@ -1384,7 +1367,7 @@ fdcswintr(arg)
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if (fdc->sc_istatus == FDC_ISTATUS_NONE)
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/* This (software) interrupt is not for us */
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return (0);
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return;
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switch (fdc->sc_istatus) {
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case FDC_ISTATUS_ERROR:
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@ -1398,7 +1381,7 @@ fdcswintr(arg)
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s = splbio();
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fdcstate(fdc);
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splx(s);
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return (1);
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return;
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}
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int
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@ -1,4 +1,4 @@
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/* $NetBSD: zs.c,v 1.92 2002/10/09 08:56:25 jdc Exp $ */
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/* $NetBSD: zs.c,v 1.93 2002/12/09 16:11:51 pk Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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@ -96,19 +96,6 @@ int zs_def_cflag = (CREAD | CS8 | HUPCL);
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*/
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#define PCLK (9600 * 512) /* PCLK pin input clock rate */
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/*
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* Select software interrupt bit based on TTY ipl.
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*/
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#if PIL_TTY == 1
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# define IE_ZSSOFT IE_L1
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#elif PIL_TTY == 4
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# define IE_ZSSOFT IE_L4
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#elif PIL_TTY == 6
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# define IE_ZSSOFT IE_L6
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#else
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# error "no suitable software interrupt bit"
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#endif
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#define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2))
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/* The layout of this is hardware-dependent (padding, order). */
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@ -192,9 +179,12 @@ CFATTACH_DECL(zs_obio, sizeof(struct zsc_softc),
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extern struct cfdriver zs_cd;
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/* softintr(9) cookie, shared by all instances of this driver */
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static void *zs_sicookie;
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/* Interrupt handlers. */
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static int zshard __P((void *));
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static int zssoft __P((void *));
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static void zssoft __P((void *));
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static int zs_get_speed __P((struct zs_chanstate *));
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@ -435,7 +425,15 @@ zs_attach(zsc, zsd, pri)
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return;
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}
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printf(" softpri %d\n", PIL_TTY);
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if (!didintr) {
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zs_sicookie = softintr_establish(IPL_SOFTSERIAL, zssoft, NULL);
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if (zs_sicookie == NULL) {
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printf("\n%s: cannot establish soft int handler\n",
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zsc->zsc_dev.dv_xname);
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return;
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}
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}
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printf(" softpri %d\n", IPL_SOFTSERIAL);
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/*
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* Initialize software state for each channel.
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@ -520,10 +518,6 @@ zs_attach(zsc, zsd, pri)
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prevpri = pri;
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bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0,
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zshard, NULL);
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bus_intr_establish(zsc->zsc_bustag, PIL_TTY,
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IPL_SOFTSERIAL,
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BUS_INTR_ESTABLISH_SOFTINTR,
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zssoft, NULL);
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} else if (pri != prevpri)
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panic("broken zs interrupt scheme");
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@ -606,13 +600,8 @@ zshard(arg)
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/* We are at splzs here, so no need to lock. */
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if (softreq && (zssoftpending == 0)) {
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zssoftpending = IE_ZSSOFT;
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#if defined(SUN4M)
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if (CPU_ISSUN4M)
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raise(0, PIL_TTY);
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else
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#endif
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ienab_bis(IE_ZSSOFT);
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zssoftpending = 1;
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softintr_schedule(zs_sicookie);
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}
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return (rval);
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}
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@ -620,7 +609,7 @@ zshard(arg)
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/*
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* Similar scheme as for zshard (look at all of them)
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*/
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static int
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static void
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zssoft(arg)
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void *arg;
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{
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@ -629,7 +618,7 @@ zssoft(arg)
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/* This is not the only ISR on this IPL. */
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if (zssoftpending == 0)
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return (0);
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return;
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/*
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* The soft intr. bit will be set by zshard only if
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@ -649,7 +638,6 @@ zssoft(arg)
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(void)zsc_intr_soft(zsc);
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}
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splx(s);
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return (1);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.4 2002/12/06 15:36:45 pk Exp $ */
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/* $NetBSD: intr.h,v 1.5 2002/12/09 16:11:52 pk Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -60,10 +60,33 @@
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#if defined(_KERNEL) && !defined(_LOCORE)
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void *
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softintr_establish __P((int level, void (*fun)(void *), void *arg));
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softintr_establish(int level, void (*fun)(void *), void *arg);
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void
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softintr_disestablish __P((void *cookie));
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softintr_disestablish(void *cookie);
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#define softintr_schedule(cookie) setsoftint()
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/*
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* NB that softintr_schedule() casts the cookie to an int *.
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* This is to get the sic_pilreq member of the softintr_cookie
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* structure, which is otherwise internal to intr.c.
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*/
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#if defined(SUN4M) || defined(SUN4D)
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extern void raise __P((int, int));
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#if !(defined(SUN4) || defined(SUN4C))
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#define softintr_schedule(cookie) raise(0, *((int *) (cookie)))
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#else /* both defined */
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#define softintr_schedule(cookie) do { \
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if (CPU_ISSUN4M || CPU_ISSUN4D) \
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raise(0, *((int *)(cookie))); \
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else \
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ienab_bis(*((int *)(cookie))); \
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} while (0)
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#endif /* SUN4 || SUN4C */
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#else /* SUN4M || SUN4D */
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#define softintr_schedule(cookie) ienab_bis(*((int *) (cookie)))
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#endif /* SUN4M || SUN4D */
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#if 0
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void softintr_schedule(void *cookie);
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#endif
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#endif /* KERNEL && !_LOCORE */
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.c,v 1.61 2002/12/06 16:04:12 pk Exp $ */
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/* $NetBSD: intr.c,v 1.62 2002/12/09 16:11:53 pk Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
|
|
@ -409,6 +409,41 @@ struct intrhand *intrhand[15] = {
|
|||
NULL, /* 14 = counter 1 = profiling timer */
|
||||
};
|
||||
|
||||
/*
|
||||
* Soft interrupts use a separate set of handler chains.
|
||||
* This is necessary since soft interrupt handlers do not return a value
|
||||
* and therefore cannot be mixed with hardware interrupt handlers on a
|
||||
* shared handler chain.
|
||||
*/
|
||||
struct intrhand *sintrhand[15] = { NULL };
|
||||
|
||||
static void ih_insert(struct intrhand **head, struct intrhand *ih)
|
||||
{
|
||||
struct intrhand **p, *q;
|
||||
/*
|
||||
* This is O(N^2) for long chains, but chains are never long
|
||||
* and we do want to preserve order.
|
||||
*/
|
||||
for (p = head; (q = *p) != NULL; p = &q->ih_next)
|
||||
continue;
|
||||
*p = ih;
|
||||
ih->ih_next = NULL;
|
||||
}
|
||||
|
||||
static void ih_remove(struct intrhand **head, struct intrhand *ih)
|
||||
{
|
||||
struct intrhand **p, *q;
|
||||
|
||||
for (p = head; (q = *p) != ih; p = &q->ih_next)
|
||||
continue;
|
||||
if (q == NULL)
|
||||
panic("intr_remove: intrhand %p fun %p arg %p",
|
||||
ih, ih->ih_fun, ih->ih_arg);
|
||||
|
||||
*p = q->ih_next;
|
||||
q->ih_next = NULL;
|
||||
}
|
||||
|
||||
static int fastvec; /* marks fast vectors (see below) */
|
||||
#ifdef DIAGNOSTIC
|
||||
extern int sparc_interrupt4m[];
|
||||
|
|
@ -425,7 +460,6 @@ intr_establish(level, classipl, ih)
|
|||
int classipl;
|
||||
struct intrhand *ih;
|
||||
{
|
||||
struct intrhand **p, *q;
|
||||
#ifdef DIAGNOSTIC
|
||||
struct trapvec *tv;
|
||||
int displ;
|
||||
|
|
@ -466,14 +500,7 @@ intr_establish(level, classipl, ih)
|
|||
/* pre-shift to PIL field in %psr */
|
||||
ih->ih_classipl = (classipl << 8) & PSR_PIL;
|
||||
|
||||
/*
|
||||
* This is O(N^2) for long chains, but chains are never long
|
||||
* and we do want to preserve order.
|
||||
*/
|
||||
for (p = &intrhand[level]; (q = *p) != NULL; p = &q->ih_next)
|
||||
continue;
|
||||
*p = ih;
|
||||
ih->ih_next = NULL;
|
||||
ih_insert(&intrhand[level], ih);
|
||||
splx(s);
|
||||
}
|
||||
|
||||
|
|
@ -482,16 +509,7 @@ intr_disestablish(level, ih)
|
|||
int level;
|
||||
struct intrhand *ih;
|
||||
{
|
||||
struct intrhand **p, *q;
|
||||
|
||||
for (p = &intrhand[level]; (q = *p) != ih; p = &q->ih_next)
|
||||
continue;
|
||||
if (q == NULL)
|
||||
panic("intr_disestablish: level %d intrhand %p fun %p arg %p",
|
||||
level, ih, ih->ih_fun, ih->ih_arg);
|
||||
|
||||
*p = q->ih_next;
|
||||
q->ih_next = NULL;
|
||||
ih_remove(&intrhand[level], ih);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -544,6 +562,20 @@ intr_fasttrap(level, vec)
|
|||
splx(s);
|
||||
}
|
||||
|
||||
/*
|
||||
* This is a softintr cookie. NB that sic_pilreq MUST be the
|
||||
* first element in the struct, because the softintr_schedule()
|
||||
* macro in intr.h casts cookies to int * to get it. On a
|
||||
* sun4m, sic_pilreq is an actual processor interrupt level that
|
||||
* is passed to raise(), and on a sun4 or sun4c sic_pilreq is a
|
||||
* bit to set in the interrupt enable register with ienab_bis().
|
||||
*/
|
||||
struct softintr_cookie {
|
||||
int sic_pilreq; /* MUST be first! */
|
||||
int sic_level;
|
||||
struct intrhand sic_hand;
|
||||
};
|
||||
|
||||
/*
|
||||
* softintr_init(): initialise the MI softintr system.
|
||||
*/
|
||||
|
|
@ -564,15 +596,47 @@ softintr_establish(level, fun, arg)
|
|||
void (*fun) __P((void *));
|
||||
void *arg;
|
||||
{
|
||||
struct softintr_cookie *sic;
|
||||
struct intrhand *ih;
|
||||
int pilreq;
|
||||
|
||||
ih = malloc(sizeof(*ih), M_DEVBUF, 0);
|
||||
bzero(ih, sizeof(*ih));
|
||||
/*
|
||||
* On a sun4m, the processor interrupt level is stored
|
||||
* in the softintr cookie to be passed to raise().
|
||||
*
|
||||
* On a sun4 or sun4c the appropriate bit to set
|
||||
* in the interrupt enable register is stored in
|
||||
* the softintr cookie to be passed to ienab_bis().
|
||||
*/
|
||||
pilreq = level;
|
||||
if (CPU_ISSUN4 || CPU_ISSUN4C) {
|
||||
/* Select the most suitable of three available softint levels */
|
||||
if (level >= 1 && level < 4)
|
||||
pilreq = IE_L1;
|
||||
else if (level >= 4 && level < 6)
|
||||
pilreq = IE_L4;
|
||||
else {
|
||||
pilreq = IE_L6;
|
||||
}
|
||||
}
|
||||
|
||||
sic = malloc(sizeof(*sic), M_DEVBUF, 0);
|
||||
sic->sic_level = level;
|
||||
sic->sic_pilreq = pilreq;
|
||||
ih = &sic->sic_hand;
|
||||
ih->ih_fun = (int (*) __P((void *)))fun;
|
||||
ih->ih_arg = arg;
|
||||
ih->ih_next = 0;
|
||||
intr_establish(1, level, ih);
|
||||
return (void *)ih;
|
||||
|
||||
/*
|
||||
* Always run the handler at the requested level, which might
|
||||
* be higher than the hardware can provide.
|
||||
*
|
||||
* pre-shift to PIL field in %psr
|
||||
*/
|
||||
ih->ih_classipl = (level << 8) & PSR_PIL;
|
||||
|
||||
ih_insert(&sintrhand[level], ih);
|
||||
return (void *)sic;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -583,11 +647,31 @@ void
|
|||
softintr_disestablish(cookie)
|
||||
void *cookie;
|
||||
{
|
||||
struct softintr_cookie *sic = cookie;
|
||||
|
||||
intr_disestablish(1, cookie);
|
||||
ih_remove(&sintrhand[sic->sic_level], &sic->sic_hand);
|
||||
free(cookie, M_DEVBUF);
|
||||
}
|
||||
|
||||
#if 0
|
||||
void
|
||||
softintr_schedule(cookie)
|
||||
void *cookie;
|
||||
{
|
||||
struct softintr_cookie *sic = cookie;
|
||||
if (CPU_ISSUN4M || CPU_ISSUN4D) {
|
||||
#if defined(SUN4M) || defined(SUN4D)
|
||||
extern void raise(int,int);
|
||||
raise(0, sic->sic_pilreq);
|
||||
#endif
|
||||
} else {
|
||||
#if defined(SUN4) || defined(SUN4C)
|
||||
ienab_bis(sic->sic_pilreq);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef MULTIPROCESSOR
|
||||
/*
|
||||
* Called by interrupt stubs, etc., to lock/unlock the kernel.
|
||||
|
|
|
|||
Loading…
Reference in New Issue