Calculate busclock and cpuclock for 8245-based boards from PLL_CFG and HID1.
Print the clocks after netboot's welcome-message. Make sure DUART-mode is enabled for eumb-systems. Support for communication with the satellite processor via the 2nd UART. Currently only KuroBox and Synology make use of it. Synology also resets the board via its satellite. Fixed console speed for KuroBox and QNAP (it is 115200).
This commit is contained in:
phx
parent
6f0c1d2e97
commit
c73646bf00
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@ -1,4 +1,4 @@
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/* $NetBSD: brdsetup.c,v 1.9 2010/05/02 13:31:14 phx Exp $ */
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/* $NetBSD: brdsetup.c,v 1.10 2010/05/08 14:40:08 phx Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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@ -31,6 +31,8 @@
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#include <sys/param.h>
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#include <powerpc/oea/spr.h>
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#include <lib/libsa/stand.h>
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#include <lib/libsa/net.h>
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#include <lib/libkern/libkern.h>
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@ -40,30 +42,89 @@
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const unsigned dcache_line_size = 32; /* 32B linesize */
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const unsigned dcache_range_size = 4 * 1024; /* 16KB / 4-way */
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static uint32_t ns_per_tick;
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void brdsetup(void);
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void setup_82C686B(void);
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void setup_83C553F(void);
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static inline u_quad_t mftb(void);
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unsigned uartbase;
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unsigned uart1base; /* console */
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unsigned uart2base; /* optional satellite processor */
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#define THR 0
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#define DLB 0
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#define DMB 1
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#define DHB 1
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#define IER 1
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#define FCR 2
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#define LCR 3
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#define LCR_DLAB 0x80
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#define LCR_PEVEN 0x18
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#define LCR_PNONE 0x00
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#define LCR_8BITS 0x03
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#define MCR 4
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#define MCR_RTS 0x02
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#define MCR_DTR 0x01
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#define LSR 5
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#define DCR 11
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#define LSR_THRE 0x20
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#define UART_READ(r) *(volatile char *)(uartbase + (r))
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#define UART_WRITE(r, v) *(volatile char *)(uartbase + (r)) = (v)
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#define LSR_THRE 0x20
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#define DCR 0x11
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#define UART_READ(base, r) *(volatile char *)(base + (r))
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#define UART_WRITE(base, r, v) *(volatile char *)(base + (r)) = (v)
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static __inline uint32_t
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cputype(void)
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{
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uint32_t pvr;
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__asm volatile ("mfpvr %0" : "=r"(pvr));
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return pvr >> 16;
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}
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static void
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init_uart(unsigned base, unsigned speed, uint8_t lcr)
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{
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unsigned div;
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div = busclock / speed / 16;
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UART_WRITE(base, LCR, 0x80); /* turn on DLAB bit */
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UART_WRITE(base, FCR, 0x00);
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UART_WRITE(base, DHB, div >> 8); /* set speed */
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UART_WRITE(base, DLB, div & 0xff);
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UART_WRITE(base, LCR, lcr);
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UART_WRITE(base, FCR, 0x07); /* FIFO on, TXRX FIFO reset */
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UART_WRITE(base, IER, 0x00); /* make sure INT disabled */
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}
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/* talk to satellite processor */
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static void
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send_sat(char *msg)
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{
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unsigned savedbase;
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savedbase = uart1base;
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uart1base = uart2base;
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while (*msg)
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putchar(*msg++);
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uart1base = savedbase;
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}
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void
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brdsetup(void)
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{
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unsigned pchb, pcib, div;
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static uint8_t pci_to_memclk[] = {
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30, 30, 10, 10, 20, 10, 10, 10,
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10, 20, 20, 15, 20, 15, 20, 30,
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30, 40, 15, 40, 20, 25, 20, 40,
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25, 20, 10, 20, 15, 15, 20, 00
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};
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static uint8_t mem_to_cpuclk[] = {
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25, 30, 45, 20, 20, 00, 10, 30,
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30, 20, 45, 30, 25, 35, 30, 35,
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20, 25, 20, 30, 35, 40, 40, 20,
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30, 25, 40, 30, 30, 25, 35, 00
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};
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uint32_t extclk;
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unsigned pchb, pcib, val;
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/* BAT to arrange address space */
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@ -72,6 +133,9 @@ brdsetup(void)
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pcicfgwrite(pchb, 0x78, 0xfc000000);
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brdtype = BRD_UNKNOWN;
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extclk = EXT_CLK_FREQ; /* usually 33MHz */
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busclock = 0;
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if (pcifinddev(0x10ad, 0x0565, &pcib) == 0) {
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brdtype = BRD_SANDPOINTX3;
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setup_83C553F();
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@ -86,31 +150,7 @@ brdsetup(void)
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brdtype = BRD_KUROBOX;
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consname = "eumb";
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consport = 0x4600;
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consspeed = 57600;
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if (pcifinddev(0x10ec, 0x8169, &pcib) == 0) /* KURO-BOX/HG */
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ticks_per_sec = 133000000 / 4;
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/* Stop Watchdog */
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uartbase = 0xfc000000 + 0x4500;
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div = (ticks_per_sec * 4) / 9600 / 16;
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UART_WRITE(DCR, 0x01); /* 2 independent UART */
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UART_WRITE(LCR, 0x80); /* turn on DLAB bit */
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UART_WRITE(FCR, 0x00);
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UART_WRITE(DMB, div >> 8);
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UART_WRITE(DLB, div & 0xff);
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UART_WRITE(LCR, 0x03 | 0x18); /* 8 E 1 */
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UART_WRITE(MCR, 0x03); /* RTS DTR */
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UART_WRITE(FCR, 0x07); /* FIFO_EN | RXSR | TXSR */
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UART_WRITE(IER, 0x00); /* make sure INT disabled */
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printf("AAAAFFFFJJJJ>>>>VVVV>>>>ZZZZVVVVKKKK");
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}
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else if (PCI_VENDOR(pcicfgread(pcimaketag(0, 15, 0), PCI_ID_REG)) ==
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0x8086) { /* PCI_VENDOR_INTEL */
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brdtype = BRD_QNAPTS101;
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consname = "eumb";
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consport = 0x4600;
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consspeed = 57600; /* XXX unverified */
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ticks_per_sec = 133000000 / 4; /* TS-101 is 266MHz */
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consspeed = 115200;
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}
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else if (PCI_VENDOR(pcicfgread(pcimaketag(0, 15, 0), PCI_ID_REG)) ==
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0x11ab) { /* PCI_VENDOR_MARVELL */
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@ -118,15 +158,56 @@ brdsetup(void)
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consname = "eumb";
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consport = 0x4500;
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consspeed = 115200;
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/* XXX assume 133MHz bus clock, valid for 266MHz models */
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ticks_per_sec = 133000000 / 4;
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}
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else if (PCI_VENDOR(pcicfgread(pcimaketag(0, 15, 0), PCI_ID_REG)) ==
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0x8086) { /* PCI_VENDOR_INTEL */
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brdtype = BRD_QNAPTS101;
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consname = "eumb";
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consport = 0x4600;
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consspeed = 115200;
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}
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/* determine clock frequencies */
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if (busclock == 0) {
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if (cputype() == MPC8245) {
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/* PLL_CFG from PCI host bridge register 0xe2 */
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val = pcicfgread(pchb, 0xe0);
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busclock = (extclk *
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pci_to_memclk[(val >> 19) & 0x1f] + 10) / 10;
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/* PLLRATIO from HID1 */
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__asm ("mfspr %0,1009" : "=r"(val));
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cpuclock = ((uint64_t)busclock *
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mem_to_cpuclk[val >> 27] + 10) / 10;
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} else
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busclock = 100000000; /* 100MHz bus clock default */
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}
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ticks_per_sec = busclock >> 2;
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ns_per_tick = 1000000000 / ticks_per_sec;
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/* now prepare serial console */
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if (strcmp(consname, "eumb") != 0)
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uartbase = 0xfe000000 + consport; /* 0x3f8, 0x2f8 */
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else
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uartbase = 0xfc000000 + consport; /* 0x4500, 0x4600 */
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if (strcmp(consname, "eumb") == 0) {
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uart1base = 0xfc000000 + consport; /* 0x4500, 0x4600 */
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UART_WRITE(uart1base, DCR, 0x01); /* enable DUART mode */
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uart2base = uart1base ^ 0x0300;
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} else
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uart1base = 0xfe000000 + consport; /* 0x3f8, 0x2f8 */
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/* configure 2nd UART when needed */
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switch (brdtype) {
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case BRD_KUROBOX:
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init_uart(uart2base, 9600, LCR_8BITS | LCR_PEVEN);
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/* Stop Watchdog */
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send_sat("AAAAFFFFJJJJ>>>>VVVV>>>>ZZZZVVVVKKKK");
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break;
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case BRD_SYNOLOGY:
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init_uart(uart2base, 9600, LCR_8BITS | LCR_PNONE);
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/* beep, power LED on, status LED off */
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send_sat("247");
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break;
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case BRD_QNAPTS101:
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init_uart(uart2base, 9600, LCR_8BITS | LCR_PNONE);
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break;
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}
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}
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void
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@ -139,16 +220,23 @@ putchar(int c)
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timo = 0x00100000;
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do {
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lsr = UART_READ(LSR);
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lsr = UART_READ(uart1base, LSR);
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} while (timo-- > 0 && (lsr & LSR_THRE) == 0);
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if (timo > 0)
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UART_WRITE(THR, c);
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UART_WRITE(uart1base, THR, c);
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}
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void
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_rtt(void)
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{
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run(0, 0, 0, 0, (void *)0xFFF00100); /* reset entry */
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switch (brdtype) {
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case BRD_SYNOLOGY:
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send_sat("C");
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break;
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default:
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run(0, 0, 0, 0, (void *)0xFFF00100); /* reset entry */
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break;
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}
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/* NOTREACHED */
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}
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@ -168,7 +256,7 @@ getsecs(void)
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{
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u_quad_t tb = mftb();
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return (tb / TICKS_PER_SEC);
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return (tb / ticks_per_sec);
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}
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/*
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u_long tbh, tbl, scratch;
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tb = mftb();
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tb += (n * 1000 + NS_PER_TICK - 1) / NS_PER_TICK;
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tb += (n * 1000 + ns_per_tick - 1) / ns_per_tick;
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tbh = tb >> 32;
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tbl = tb;
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asm volatile ("1: mftbu %0; cmpw %0,%1; blt 1b; bgt 2f; mftb %0; cmpw 0, %0,%2; blt 1b; 2:" : "=&r"(scratch) : "r"(tbh), "r"(tbl));
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@ -1,10 +1,9 @@
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/* $NetBSD: globals.h,v 1.12 2010/05/02 13:31:14 phx Exp $ */
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/* $NetBSD: globals.h,v 1.13 2010/05/08 14:40:08 phx Exp $ */
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/* clock feed */
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#ifndef TICKS_PER_SEC
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#define TICKS_PER_SEC (100000000 / 4) /* 100MHz front bus */
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#ifndef EXT_CLK_FREQ
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#define EXT_CLK_FREQ 33333333 /* external clock (PCI clock) */
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#endif
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#define NS_PER_TICK (1000000000 / TICKS_PER_SEC)
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/* brd type */
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extern int brdtype;
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@ -20,6 +19,7 @@ extern char *consname;
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extern int consport;
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extern int consspeed;
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extern int ticks_per_sec;
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extern uint32_t cpuclock, busclock;
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unsigned mpc107memsize(void);
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@ -1,4 +1,4 @@
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/* $NetBSD: main.c,v 1.24 2010/05/02 13:31:14 phx Exp $ */
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/* $NetBSD: main.c,v 1.25 2010/05/08 14:40:08 phx Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -58,7 +58,8 @@ int brdtype;
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char *consname = CONSNAME;
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int consport = CONSPORT;
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int consspeed = CONSSPEED;
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int ticks_per_sec = TICKS_PER_SEC;
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int ticks_per_sec;
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uint32_t busclock, cpuclock;
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void
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main(void)
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@ -89,7 +90,8 @@ main(void)
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case BRD_SYNOLOGY:
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printf("Synology DS"); break;
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}
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printf(", %dMB SDRAM\n", memsize >> 20);
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printf(", cpu %u MHz, bus %u MHz, %dMB SDRAM\n",
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cpuclock / 1000000, busclock / 1000000, memsize >> 20);
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n = pcilookup(PCI_CLASS_IDE, lata, sizeof(lata)/sizeof(lata[0]));
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if (n == 0)
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