Integrate Phil Budne's latest changes to the scn driver. From his README:
* Uses Counter/Timer dynamicly for rate generation; You can have both 19200 and 38400 on one duart, and 57600 on another! * Improved scninfo program to dump driver internal information. implemented counters for parity err, framing err, break * Delays changes until transmitter idle to avoid "glitches" * Cleaned up scn_softc member names * Untested support for sc26c92 (I don't yet have any to test with); + Will use alternate rate tables (include 115.2kbps and 230.4kbps) + Will raise FIFO rx interrupt threshold and watchdog timer at higher rates. + Unknown (to me) how fast pc532 MC145406 driver chips can go NOTE: It seems like it may be a BAD idea to use a sc26c92 as a console port for now; the PROM doesn't know to reset the chip back to scn2692 mode!!
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@ -1,7 +1,7 @@
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/* $NetBSD: scnreg.h,v 1.8 1996/12/23 08:37:10 matthias Exp $ */
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/* $NetBSD: scnreg.h,v 1.9 1997/03/13 10:24:15 matthias Exp $ */
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/*
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* Copyright (c) 1996 Phil Budne.
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* Copyright (c) 1996, 1997 Philip L. Budne.
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* Copyright (c) 1993 Philip A. Nelson.
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* All rights reserved.
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*
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@ -67,25 +67,33 @@
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* MR (mode register) -- per channel
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*/
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/* MR0 (scn26c92 only) */
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#define MR0_BR_EXTND1 1
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#define MR0_BR_EXTEND2 4
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#define MR0_TXINT 0x30
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#define MR0_RXINT 0x40
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#define MR0_RXWD 0x80
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/* MR0 (scn26c92 only) need to use CR_CMD_MR0 before access */
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#define MR0_MODE 0x07 /* extended baud rate mode (MR0A only) */
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#define MR0_TXINT 0x30 /* Tx int threshold */
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#define MR0_RXINT 0x40 /* Rx int threshold (along with MR1_FFULL) */
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#define MR0_RXWD 0x80 /* Rx watchdog (8 byte-times after last rx) */
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#define MR0_MODE_0 0x00 /* Normal mode */
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#define MR0_MODE_1 0x01 /* Extended mode 1 */
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#define MR0_MODE_2 0x04 /* Extended mode 2 */
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#define MR0_TXINT_EMPTY 0x00 /* TxInt when 8 FIFO bytes empty (default) */
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#define MR0_TXINT_4 0x10 /* TxInt when 4 or more FIFO bytes empty */
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#define MR0_TXINT_6 0x20 /* TxInt when 6 or more FIFO bytes empty */
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#define MR0_TXINT_TXRDY 0x30 /* TxInt when 1 or more FIFO bytes empty */
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/* MR1 (need to use CR_CMD_MR1 before each access) */
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#define MR1_BITS5 0x00
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#define MR1_BITS6 0x01
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#define MR1_BITS7 0x02
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#define MR1_BITS8 0x03
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#define MR1_CS5 0x00
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#define MR1_CS6 0x01
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#define MR1_CS7 0x02
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#define MR1_CS8 0x03
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#define MR1_PEVEN 0x00
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#define MR1_PODD 0x04
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#define MR1_PNONE 0x10
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#define MR1_RXBLK 0x20 /* "block" error mode */
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#define MR1_FFULL 0x40 /* wait until FIFO full for rxint */
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#define MR1_FFULL 0x40 /* wait until FIFO full for rxint (cf MR0) */
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#define MR1_RXRTS 0x80 /* auto RTS input flow ctrl */
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/* MR2 (any access to MR after MR1) */
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@ -1,7 +1,7 @@
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/* $NetBSD: scnvar.h,v 1.2 1996/12/23 08:37:11 matthias Exp $ */
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/* $NetBSD: scnvar.h,v 1.3 1997/03/13 10:24:16 matthias Exp $ */
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/*
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* Copyright (c) 1996 Phil Budne.
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* Copyright (c) 1996, 1997 Philip L. Budne.
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* Copyright (c) 1993 Philip A. Nelson.
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* All rights reserved.
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*
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@ -31,7 +31,7 @@
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* scnvar.h: definitions for pc532 2681/2692 duart driver
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* scnvar.h: definitions for pc532 2681/2692/26c96 duart driver
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*/
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/* Constants. */
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@ -83,14 +83,10 @@
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#define IPCR_DELTA_DCDB IPCR_DELTA_IP2
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#define IPCR_DELTA_DCDA IPCR_DELTA_IP3
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#define SP_GRP0 0x00
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#define SP_GRP1 0x10
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#define SP_BOTH 0x20
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#define SCN_OP_BIS(SC,VAL) ((SC)->sc_duart->base[DU_OPSET] = (VAL))
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#define SCN_OP_BIC(SC,VAL) ((SC)->sc_duart->base[DU_OPCLR] = (VAL))
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#define SCN_OP_BIS(SC,VAL) ((SC)->duart->base[DU_OPSET] = (VAL))
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#define SCN_OP_BIC(SC,VAL) ((SC)->duart->base[DU_OPCLR] = (VAL))
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#define SCN_DCD(SC) (((SC)->duart->base[DU_IP] & (SC)->sc_ip_dcd) == 0)
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#define SCN_DCD(SC) (((SC)->sc_duart->base[DU_IP] & (SC)->sc_ip_dcd) == 0)
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/* pc532 duarts are auto-sized to byte-wide */
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#define CH_SZ 8
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#define SCN_REG(n) (n) /* n'th reg at n'th byte!! */
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/* The DUART description struct; for data common to both channels */
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struct duart_info {
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struct duart {
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volatile u_char *base;
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int i_speed[2], o_speed[2]; /* Channel A and B speeds. */
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char i_code[2], o_code[2]; /* Channel A and B speeds. */
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char speed_grp; /* BRG speed group */
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char acr_bits; /* ACR bits 0-6 */
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char imr_int_bits; /* IMR bits current set. */
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char opcr_bits; /* OPCR bits to set */
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char hwflags;
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#define SCN_HW_2692 1
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#define SCN_HW_26C92 2
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struct chan {
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int32_t ispeed, ospeed;
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u_char icode, ocode;
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u_char mr0; /* MR0[7:3] */
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u_char new_mr1; /* held changes */
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u_char new_mr2; /* held changes */
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} chan[2];
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enum scntype { SCNUNK, SCN2681, SCN2692, SC26C92 } type;
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u_int16_t counter; /* C/T generated bps, or zero */
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u_int16_t ocounter; /* last C/T generated bps, or zero */
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u_char mode; /* ACR[7] + MR0[2:0] */
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u_char acr; /* ACR[6:0]*/
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u_char imr; /* IMR bits */
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u_char opcr; /* OPCR bits */
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};
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#define SCN_RING_BITS 9 /* 512 byte buffers */
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@ -119,24 +120,24 @@ struct duart_info {
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/* scn channel state */
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struct scn_softc {
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struct device scn_dev;
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struct tty *scn_tty;
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/* XXXPLB: prefix with scn_; */
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int unit; /* unit number of this line (base 0) */
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struct duart_info *duart; /* pointer to duart struct */
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volatile u_char *chbase; /* per-channel registers (CH_xxx) */
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u_char lstatus; /* last line status (sr) */
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u_char scn_swflags; /* from config / TIOCxFLAGS */
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struct device sc_dev;
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struct tty *sc_tty;
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int sc_unit; /* unit number of this line (base 0) */
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struct duart *sc_duart; /* pointer to duart struct */
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volatile u_char *sc_chbase; /* per-channel registers (CH_xxx) */
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u_char sc_swflags; /* from config / TIOCxFLAGS */
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#define SCN_SW_SOFTCAR 0x01
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#define SCN_SW_CLOCAL 0x02
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#define SCN_SW_CRTSCTS 0x04
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#define SCN_SW_MDMBUF 0x08 /* not implemented */
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/* I wish there was a TS_DIALOUT flag! */
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u_char scn_dialout; /* set if open for dialout */
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#define SCN_DIALOUT(SCN) ((SCN)->scn_dialout)
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#define SCN_SETDIALOUT(SCN) (SCN)->scn_dialout = 1
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#define SCN_CLRDIALOUT(SCN) (SCN)->scn_dialout = 0
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u_char sc_dialout; /* set if open for dialout */
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#define SCN_DIALOUT(SCN) ((SCN)->sc_dialout)
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#define SCN_SETDIALOUT(SCN) (SCN)->sc_dialout = 1
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#define SCN_CLRDIALOUT(SCN) (SCN)->sc_dialout = 0
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u_char sc_heldchanges; /* waiting for output done */
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/* bits in input port register */
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u_char sc_ip_dcd;
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/* interrupt mask bits */
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u_char sc_tx_int;
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/* error counts */
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u_long framing_errors; /* NYI */
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u_long overrun_errors;
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u_long parity_errors; /* NYI */
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u_long break_interrupts; /* NYI */
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/* counters */
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u_long sc_framing_errors;
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u_long sc_parity_errors;
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u_long sc_fifo_overruns;
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u_long sc_breaks;
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/* ring buffer for rxrdy interrupt */
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u_int sc_rbget; /* ring buffer `get' index */
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short sc_rbuf[SCN_RING_SIZE]; /* status + data */
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long sc_fotime; /* last fifo overrun message */
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long sc_rotime; /* last ring overrun message */
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u_long ring_overruns; /* number of ring buffer overruns */
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u_long sc_ring_overruns; /* number of ring buffer overruns */
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/* Flags to communicate with scntty_softint() */
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volatile char sc_rx_blocked; /* input block at ring */
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};
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